Co-Simulation of interconnected power electronics

using Simulink-PSpice interface and components

defined in C/C++ and SystemC

Bao Nguyen, Senior Pilot Engineer, MathWorks

Kishore Karnane, Product Management Director, Cadence

© 2016 The MathWorks, Inc.

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AGENDA

 Challenges in Analog/Mixed-Signal Design

 The SLPS Co-Simulation Interface

 The Device Modeling Interface (DMI) and Exporting Models from Simulink
– Demo

 Conclusion

2
Analog/Mixed-Signal Design
Example: Field-oriented Control of a Permanent-Magnet-Synchrone-Machine

This control technique is common in motor drive systems for hybrid electric vehicles,
manufacturing machinery, and industrial automation
vexp
Field-Oriented Power
PWM PMSM
Controller Inverter
Load
I
v

Digital Analog Electro-

mechanical
Target: Target:
• MCU (SW) • Transitor-level
• FPGA, ASIC (HW) Design
3
Challenges in Classical Mixed-Signal Design

Limited analog SPECIFICATION Specification

design isolated from
abstractions verification

IMPLEMENTATION IMPLEMENTATION
Design trade-
offs difficult Digital Analog

C/C++
SPICE

TEST & VERIFICATION

No run-time HDL
analog/digital
links

Slow design INTEGRATION

iterations Disconnected
Digital Analog
Hardware Hardware teams

4
Model-Based Design

RESEARCH REQUIREMENTS  „Executable Specification“

DESIGN
 Simulink as multi-domain
Environment Models
simulation environment
Digital Models Analog Models
– Time-continuous and time-discrete

TEST & VERIFICATION

Timing and Control Logic
(sampled)
Algorithms
– Event-triggered
IMPLEMENTATION
– Mathematical and physical algorithm
modeling
HDL C/C++ SPICE

FPGA ASIC MCU DSP Silicon

– Robustness through environment
TEST
SYSTEM modeling

INTEGRATION  Automatic code generation (C/C++,

HDL)
 Continuous Verification 5
Model-Based Design for Analog/Mixed-Signal

 Bottom-Up Workflow

TEST & VERIFICATION

RESEARCH REQUIREMENTS

DESIGN
– Starting point:
Environment Models
Transistor-level schematic
Digital Models Analog Models

Timing and Control Logic – Needs

Algorithms  Input stimuli generation
 Integration in surrounding multi-domain
system
IMPLEMENTATION
 Analysis in time/frequency domain
HDL C/C++ SPICE

FPGA ASIC MCU DSP Silicon

TEST
SYSTEM – Solution
 Co-simulation with OrCAD PSpice using
INTEGRATION SLPS

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Model-Based Design for Analog/Mixed-Signal

 Top-Down Workflow

TEST & VERIFICATION

RESEARCH REQUIREMENTS

DESIGN
– Starting point:
Environment Models
 Mathematical Model
Digital Models Analog Models
 Physical Model

Timing and Control Logic

– Needs
Algorithms
 Simulation speed (proof of
concept)
IMPLEMENTATION  Reuse of existing testbench
HDL C/C++ SPICE
 Sign-off Transistor-level simulation

FPGA ASIC MCU DSP Silicon

TEST
SYSTEM
– Solution
 Co-simulation with Simulink and
INTEGRATION PSpice using SLPS
 Model integration through
automatic C code generation
and PSpice DMI
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What is SLPS?

 SLPS = Simulink + PSpice Co-Simulation

– Simulink
 Multi-domain simulation environment for dynamic systems
 Algorithm development and verification platform

– PSpice:
 SPICE-based simulator
 Simulation of electrical and electronic circuits
 Circuit design platform  Hardware

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How does SLPS work?

 Simulink plays the master role

 The SLPS-block in Simulink builds
the interface between both
simulators
 Both simulators work with their
own time-step-control algorithm
– guarantees the optimal compromise
out of simulation accuracy and
performance.

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Step 1: Algorithm Design and Verification

Time-discrete Physical Models of

PWM Mechanical
Generator Load Scenarios

Time-continuous
PI Controllers
(speed, current)

Physical Models
of
Electrical Components
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Step 1: Algorithm Design and Verification

Load Scenario: with Load

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Step 1: Algorithm Design and Verification

Load Scenario: with Load and Vibration

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Step 2: Schematic Entry (PSpice)

IGBT

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Step 3: Simulink/PSpice Co-Simulation (SLPS)

SLPS
Co-Simulation
Interface

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Step 3: Simulink/PSpice Co-Simulation (SLPS)

Simulink / PSpice
Co-Simulation
Simulink Simulation (SLPS)

wm_ref, wm

wm_ref, wm
Te [Nm]

Te [Nm]
Vs_abc [V]

Vs_abc [V]
Is_abc [A]
Is_abc [A]

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Automotive Engineering
Interdisciplinary Design Challenge

Vehicle
Electronics

Emission and
Safety &
Fuel
Quality
Economy

Comfort &
Performance

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Automotive Engineering
Interdisciplinary Design Challenge

Vehicle Electronics
Explosion of Interconnected Electronic Systems with Embedded Software
having some very challenging Power Density issues created by System
miniatuarization for reliability, form & functions.

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Automotive Engineering
Interdisciplinary Design Challenge

PSpice Solution
Design Trends
System Design linked to System
Interconnected • Mixed Signal Control “Drive By Implementation
Systems Wire” over bus protocols
Mixed Signal Accuracy
accelerated with System Model
Embedded • Complex Algorithmic Control, Abstractions
Software Configurability and
Maintenance Virtual Prototyping –
Model/HIL/SW Co-Simulation for
early S/W Validation
System • Reliability, smaller space,
Miniaturization increased Functions packaged Implementation across multiple
in Lower Power consumption design fabrics –
Chip/Package/Board

• Smaller form factors handling Analog Behavioral and New

Power Density huge power transfer are Technology Physical Device
driving higher power density modeling

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PSpice complex device macro-model

Physical device compact model Every complex device on

PCB - a system model
SystemC model supporting embedded in mixed-signal
embedded S/W and different device model
abstraction levels

Analog behavioral

Digital C/C++ with embedded SW

block

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PSpice Models

Algorithmic Models Model Abstractions

(MATLAB, Simulink, C/C++)

Architectural
System Models (SystemC)

Functional
Digital Models with
IO/Timing/Constraint
Behavioral
Digital Functional Models
Gate Level

PSpice Behavioral Models

Circuit Level

Compact Device Models Physical

Implementation

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System Design Exploration to Implementation

PSpice PCB PSpice System

Block in Simulink Design

Simulink Coder
to PSpice Block

PSpice PCB
Implementation

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Device Modeling Interface

Digital
Devices
Analog
Behavioral DMI Model Code
Devices
Physical
Devices

Communicating C/C++, SystemC, VerilogA,

PSpice Simulator with PSpice MATLAB, Simulink

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Device Modeling Interface Libraries

PSpice Device User Information

PSpice Engine Functions

Pspice Digital API PSpice Base

Definitions

PSpice Common
Model API Definitions

PSpice Common API Definitions

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Device Modeling Interface – Embedded Coder Steps

Generate Generate Device Compile Associate

C++ Code User Information and PSpice
for Simulink and register with generating model with
Model Engine Function DLL, LIB symbol and
Simulate

 Requires Embedded Coder license

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Device Modeling Interface – Steps for integrating Simulink
models

Top Level Simulink

Analog Model
Schematic
Embedded Coder

Generated
C++ Code
OrCAD
Capture Embedded Coder

Code
Embedded
inside DMI
Embedded Coder

Associate
Compile and
PSpice Model
generate dll
with a Symbol
PSpice
PSpice

Run Simulation
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Simulink Model Example

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Simulink-PSpice Target Configuration – Code Generation

Embedded Coder
Target C++ Code

Custom Template
Makefile

27
Simulink-PSpice Target Configuration – Custom Code

DMI‘s Libraries Path

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Simulink-PSpice Target Configuration – Interface

Fucnction Prototype

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Simulink-PSpice Target Configuration – Templates

Custom DMI
Wrapper Code
Template

30
Simulink Simulation Results

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PSpice Model Example

32
PSpice DMI Library

Generated by
Embedded Coder

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PSpice Simulation Results

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Demo

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Q&A

 MathWorks’s Point-of-Contact:
– Bao Nguyen [email protected]
– Corey Mathis [email protected]

 Cadence’s Point-of-Contact :
– Kishore Karnane [email protected]

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Conclusion

 SLPS is a needed tool because of:

– Introduction of newest technologies and efficient methods.
– Possibility to verify and optimize SW-Algorithms with HW-Models.
– Reconnaissance and compensation of errors during the specification and
implementation reducing development time.

 DMI increase the possibilities:

– System Level Simulation importing C/C++/SystemC and Simulink Blocks into a
unique simulator.
– Hardware in the Loop, getting the results in a completely reliable environment to
test the new critical functions.

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Conclusion

HiL DMI PSpice SLPS Simulink

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