Lectures 2-4:

Introduction to System
Design, VHDL Basics
TIE-50206 Logic Synthesis
Arto Perttula
Tampere University of Technology
Fall 2015
Contents
• 1. Introduction to System Design
– Abstraction
– Main phases
• 2. VHDL basics
– Entity – the interface
• Ports, generics
– Architecture – the behavior
• Signals, types
• Process, component instantiation, control statements
– Library, package
Arto Perttula 19.10.2015 2
Acknowledgements
• Prof. Pong P. Chu provided ”official” slides for
the book which is gratefully acknowledged
– See also: http://academic.csuohio.edu/chu_p/
• Most slides were originally made by Ari Kulmala
– and other previous lecturers (Teemu Pitkänen, Konsta
Punkka, Mikko Alho, Erno Salminen…)

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1a. Representation (View) and Abstraction

1. INTRODUCTION TO
SYSTEM DESIGN
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Examples of Different Views
• View: different perspectives of a system
1. Behavioral view:
– Describe functionalities and i/o behavior
– Treat system as a black box
2. Structural view:
– Describe the internal implementation
(components and interconnections)
– Essentially a block diagram (or schematic)
3. Physical view:
– Add more info to structural view: component size, component locations, routing wires
– E.g., layout of a print circuit board

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Examples of Different Views (2)
inputs:
button0_in, button1_in
...

outputs:
led0_out
audio_out
...

Function:
When user presses
button1, then...
When...

1. Behavioral 2. Structural 3. Physical

higher abstraction
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Complexity Management
• Q: How to manage complexity for a chip with 10 million transistors?
• A: Abstraction – a simplified model of a system
– Show the selected features
– Ignore many details
• E.g., timing of an inverter

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Levels of Abstraction in HDL
1. Transistor level, lowest abstraction
2. Gate level
3. Register transfer level (RTL)
– Typical level nowadays in addition to structural
4. Behavioral (Processor) level, highest abstraction
5. (Manager view: everything works just by snapping fingers…)
• Characteristics of each level
– Basic building blocks
– Signal representation
– Time representation
– Behavioral representation
– Physical representation
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 Summary of Abstractions
Example Course
Level block

ELT-
xxxx

DigiPer.
Dig Suunn
adder
divide Dig.Suunn.
FSM
this
SW CPU MEM
behavioral NOC System
I/O ACC design

This course focuses on RTL

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Behavioral Description
• An untimed algorithm description with no notation of time or registers (or
even interface)
• The tools automatically place the registers according to the constraints set
by the designer
• E.g., FFT described in Matlab/C
• The designer gives constraints to a behavioral synthesis tool
– Maximum latency, clock frequency, throughput, area
– Interface
• The tool explores the design space and creates the timing-aware circuit
• Not very well supported yet

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Register-Transfer Level (RTL)
• Typically, HW description languages use RT level
• The idea is to represent the combinational logic before registers
– The logic between registers, i.e., between register transfers
• The registers are ”implied” not explicitly defined in VHDL
– Synchronous processes imply registers and are covered later lectures
• Combinatorial logic is created by synthesis tool and depends on
1. Right-hand-side of the signal assignment (e.g. x_r <= a+b;)
2. Preceding control structures (if sel=’1’, for(i=0;i<9;i++)…)
Explicitly defined Implied by coding style Note that you can
create purely
x_r combinatorial logic
inputs

Comb.
D Q using RTL
logic
abstraction
11
Register-Transfer Level (RTL) (2)
• RT (Register Transfer) is a bit misleading term
• Two meanings:
1. Loosely: represent the module level
2. Formally: a design methodology in which the system operation is described by how the data is manipulated
and moved among registers

Time_instant Value of a_r Value of b_r Value of c_r

Clock
tick
T0 x0
T1 x1 foo(x0)

T2 x2 foo(x1) bar(foo(x0))
a_r b_r c_r
...,x1,x0 D Q foo() D Q bar() D Q
12
 Key for Success: Hierarchy

• All systems are designed and

implemented hierarchically
• The same component can be
replicated and used in many
products
• Usually only knowledge of
external behavior is required,
not the internals
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Structural VHDL Description
• Circuit is described in terms of its components
• High-level block diagram
• Black-box components, modularity
• For large circuits, low-level descriptions quicky become impractical
• Hierarchy is very essential to manage complex designs

Syntax:
Corresponds to the entity

Parameters

Ports

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Example
• A hierarchical two-digit decimal counter
– pulse=1 when q is 9
– p100=1 when both q_ten and q_one are 9
– However, if en goes 0 when q=9, something strange happens…
• Let’s concentrare on the structure…
Top-level block diagram, ”hundred_counter”
Single
counter
component

15
Example Implemented in VHDL
Top-level entity

Instantiate the counters as in schematic and

connect the signals to ports.
Notation for mapping ports:
<port name in the component> =>
<signal name or port in higher
level>

”We will use an existing

component called
dec_counter”
Internal signals
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1b. Development Tasks

1. INTRODUCTION TO
SYSTEM DESIGN
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System Development
• Developing a digital system is a refining and validating process
• Main tasks:
I. requirements

I-III. verification
capture, specification

II. design, synthesis

III. physical design

time IV. fabrication, testing

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I. Specification
• Capture the
1. use cases, requirements
2. non-functional requirements (performance, cost, power consumption,
silicon area)
• Usually informal, natural language (English, Finnish) completed with
tables and illustrations
– Formal methods are being studied and their importance will increase

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II. Design, Synthesis
• A refinement process that realizes a description with components from the lower
abstraction level
– Manual/automated
• The resulting description is a structural view in the lower abstraction level
– A synthesis from VHDL code obtains netlist (gates and flip-flops)
– Estimates the size, maximum frequency and power consumption
• Type of synthesis:
– High-level synthesis
– RT level synthesis
– Gate level synthesis
– Technology mapping
• Emphasis of this course

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III. Physical Design
• Placement of cells and routing of wires
– Refinement from structural view to physical view
– Derive layout of a netlist
• Circuit extraction:
– Determine wire resistance and capacitance accurately to estimate
timing and power
• Others
– Derivation of power grid and clock distribution network, assurance of
signal integrity etc.

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I-III. Verification
• Check whether a design meets the specification and performance
goals
• Concern the correctness of the initial design and the refinement
processes
• Two aspects
1. Functionality (e.g., is the answer 42?)
2. Non-functional (e.g., performance)
• Takes ~40-80% of design time

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I-III. Methods of Verification
1. Simulation
– Spot check: cannot verify the absence of errors
– Can be computationally intensive
2. Hardware emulation with reconfigurable HW
– Almost real-time, connection to external devices
3. Timing analysis
– Just check the worst case delay, automated
4. Formal verification
– Apply formal mathematical techniques to determine certain properties, applicable only in small scale
– E.g., equivalence checking between two models
5. Specification/code review
– Explain the design/specification to others and they comment it
– Surprisingly powerfull!

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IV. Testing
• Testing is the process of detecting physical defects of a die or a package
occured at the time of manufacturing
– Testing and verification are different tasks in chip design
• Difficult for large circuit
– Must add auxiliary testing circuit into design
– E.g., built-in self test (BIST), scan chain etc.
– Some tests with specialized test-SW running on chip
• Locating the fault is not always needed
– Faulty chips simply discarded
• Basic tests are done at wafer-level
– Sub-set of tests also for packaged chips
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1c. Development Flow

1. INTRODUCTION TO
SYSTEM DESIGN
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EDA Software
• EDA (Electronic Design Automation) software can automate many tasks
• Mandatory for success together with re-use!
• Can software replace human hardware designer? (e.g., C-program to chip)
• Synthesis software
– Should be treated as a tool to perform transformation and local optimization
– Cannot alter the original architecture or convert a poor design into a good one
– See also the so called ”Mead & Conway revolution”
• EDA tools abstraction level in functional description has not increased
significantly since mid-90’s when RT-level gained popularity
– Increased abstraction always causes some penalty in performance, area etc.
when increasing abstraction, but significant improvement in time to design
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Design Flow
data file process

Synthesis Physical Design Verification

• Medium design targeting FPGA RTL 1 1

description testbench

• Circuit up to 50,000 gates synthesis 3 simulation 2

• Note the test bench development at netlist delay file

the same time as RTL (or before

that) placement & 54 simulation 4
routing

• Large design targeting FPGA needs

configuration delay file
also file

– Design partition
device simulation/

– More verification timing

7 6
programming analysis

– I/O-verification, external interfaces FPGA 8

chip
2a. Basics

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Why (V)HDL?
• Interoperability
• Technology independence
• Design reuse
• Several levels of abstraction
• Readability
• Standard language
• Widely supported
 Improved productivity

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What Is VHDL?
• VHDL = VHSIC Hardware Description Language
– (VHSIC = Very High Speed IC)

• Design specification language

• Design entry language
• Design simulation language
• Design documentation language
• An alternative to schematics
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A Brief VHDL History
• Developed in the early 1980’s
– For managing design problems that involved large circuits and multiple teams of
engineers
– Originally for documentation, synthesis developed soon after
– Funded by U.S. Department of Defence
• First publicly available version released in 1985
• IEEE standard in 1987 (IEEE 1076-1987)
– IEEE = Institute of Electrical and Electronics Engineers
• An improved version of the language was released in 1994
– IEEE standard 1076-1993
– No major differences to ’87, but some shortcuts added
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VHDL
• Parallel programming language(!) for hardware
– Allows sequential code portions also
• Modular
– Interface specification is separated from the functional specification
• Allows many solutions to a problem example.vhd
• The coding style matters!
– Different solutions will be slower and/or larger than others Interface
– Save money!
• Case-insensitive language Declarations
– Examples (usually) show reserved words in CAPITALS
• Widely used language Functionality
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 My First VHDL Example
ENTITY eg1 IS
PORT (
clk
rst_n
: IN
: IN
STD_LOGIC;
STD_LOGIC; eg1
a,b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
both_1_out: OUT STD_LOGIC; both_1_out
siwa_out : OUT STD_LOGIC C
);
END eg1;
ARCHITECTURE rtl OF eg1 IS
SIGNAL c : STD_LOGIC;
BEGIN a 2
both_1_out <= c;
c <= a(0) AND b(0);
PROCESS ( clk, rst_n ) b 2
BEGIN
IF rst_n = ‘0’ THEN b(0) 00
siwa_out <= ‘0’;
ELSIF clk‘EVENT AND clk = '1' THEN ’0’ 01 siwa_out
IF a = ‘00' THEN
siwa_out <= b(0);
’0’ 10
ELSIF a = ‘11' then DFF
siwa_out <= b(1); 11
ELSE
siwa_out <= ‘0’; b(1) 19.10.2015
END IF; clk
END IF;
END PROCESS;
END rtl;
rst_n
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VHDL Environment
(ModelSim)

(Quartus)
C <= A AND B

(Tools used in this course are shown in parentheses)

Physical design 34
 Interface

Entities – Interfaces Declarations

Functionality

• A black box with interface definition

– Functionality will be defined in architecture
• Defines the inputs/outputs of a component (pins)
• Defines the generic parameters (e.g., signal width)
• A way to represent modularity in VHDL
• Similar to symbol in schematic
8
• Reserved word ENTITY A_in eq_out
B_in comparator
8
ENTITY comparator IS
PORT (
a_in : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
eq_out : OUT STD_LOGIC
);
END comparator;

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 Interface

Architecture – Internals Declarations

Functionality

• Every entity has at least one architecture

• Architecture specifies the internals of a design unit and is coupled to a
certain entity entity X
– Defines functionality
A_in C_out
• One entity can have several architectures X
B_in
• Architectures can describe design on many levels
– Gate level
– RTL (Register Transfer Level) arch 1 arch 2
– Structural ”It is ”It is
logical logical
etc.
– Behavioral level
AND” XOR”

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Architecture (2)
• Example:
ARCHITECTURE rtl OF comparator IS
BEGIN
eq_out <= ’1’ WHEN (a_in = b_in) ELSE ’0’;
END rtl;

• Two main approaches

1. Define new functionality with control statements, e.g., if-for-case, (rtl), shown
above
2. Instantiate existing components and define interconnections between them
(structural)
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 Interface

Ports Declarations
Functionality

• Provide communication channels (=pins) between the component and its environment
• Each port must have a name, direction and a type
– An entity may omit port declaration, e.g., in test bench
• Port directions:
1. IN: A value of a port can be read inside the component, but cannot be assigned. Multiple reads
of port are allowed.
2. OUT: Assignment can be made to a port, but data from a port cannot be read. Multiple
assignments are allowed.
3. INOUT: Bi-directional, assignments can be made and data can be read. Multiple assignments
are allowed. (not recommended inside a chip)
4. BUFFER: An out port with read capability. May have at most one assignment (not recommended)

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 Interface

Signals Declarations
Functionality

• Used for communication inside the architecture, carry data

– Ports behave like signals
• Can be interpreted as
a) Wires (connecting logic gates)
b) ”wires with memory” (i.e., FF’s, latches etc.)
• VHDL allows many types of signals
– Bit vectors, integers, even multidimensional arrays and records
• Declared in the architecture body’s declaration section
• Signal declaration:
SIGNAL signal_name : data_type;
• Signal assignment:
signal_name <= new_value;
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 Interface

Other Declarations Declarations

Functionality

• Functions, procedures (subprograms)

– Much like in conventional programming languages
• Component declaration
– ”We will use an adder which looks like this”
• Configuration
– ”We will use exactly this adder component instead of that other
one”
– Binds certain architecture to the component instance

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 Interface

Libraries And Packages Declarations

Functionality

• Frequently used functions and types can be grouped in a package

• Libraries include several compiled packages and other design units
• Packages typically contain
– Constants
• Like header.h in conventional programming languages
– General-purpose functions
• E.g., Log2(x)
– Design-specigic definitions
• E.g., own data types, records (structs)

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Design Units
• Segments of VHDL code that can be compiled separately and stored in a library
• Library = directory of compiled VHDL files
VHDL library

entity
VHDL declaration
source package
files declaration

architecture
architecture package configuration
architecture
body
body body declaration
body

Select an entity or configuration into simulation 42

Structure of VHDL Entity
entity declaration:
• Usually 1 entity plus 1 architecture per file in
ports, generics
out

– File named according to entity

architecture

arch declarations:
• Architectures contains usually either signals,
functions,
a) processes, or types

b) instantiations arch body:

concurrent statements
component instantiations,
processes
(signal assignments,
if-for-case)

entity_name.vhd
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Relation Between Circuit And VHDL
Realization Examples GENERIC VHDL STRUCTURE

A : IN
B : IN
Sel : IN
add C : OUT
A
Adder
B

0
Multiplier 1 C
mul signal add, mul
Components +, *
declaration

sel Mux realization

Component instantiation
Signal assignments
19.10.2015
Even Parity Detection Circuit
Truth table:
• Input: a(2), a(1), a(0)
• Output: even
Boolean function:

Logic with basic gates:

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 Even Parity Detection Circuit at Gate-Level VHDL
Defines packages
that are used in the
design p1

The interface of a
block ”even_detector”
Input a, 3 bits
Output even, 1 bit
p4

Signals used internally

Functionality of the
block (gate level
representation).
The order of
assigments does
NOT matter here.

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2b. VHDL Processes

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Process
• Basic modeling concept of VHDL
• The whole process is a concurrent statement
– i.e., processes are executed in parallel
• Contains a set of statements that are executed sequentially
• VHDL description can always be broken up to interconnected processes
• Keyword PROCESS entity
arch
process P2
P1
port P3 P4
a_v tmp_v

signal
variable
19.10.2015 48
Process (2)
• Processes are the basic building blocks of functional (in most cases
that means RTL) description
• Practically every design has at least one process
• In VHDL, the flip-flops are generated with (synchronous) processes
– No reserved word for registers in VHDL
– Synthesis/simulation tools recognize certain process structures that
imply registers (set of D-flip-flops)
– To be covered later

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Process (3)
• Resides in the architecture’s body
• A process is like a circuit part, which can be
a) active (known as activated)
b) inactive (known as suspended)
• It’s statements will be executed sequentially top-down until the end of the process
– Written order of statements matters, unlike in concurrent statements
• However, all signal assignments take place when process exits
– Forgetting this is a Top-3 mistake for beginners
b <= 1; -- b was 5
c <= b; -- c gets the old value of b, i.e. 5
– Last assignment to a signal will be kept

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Process’s Sensitivity List
• A process is activated when any of the signals in the sensitivity list changes its value
• Process must contain either sensitivity list or wait statement(s), but NOT both
– Similar behavior, but sensitivity list is much more common
• General format:
label: PROCESS[(sensitivity_list)]
process_declarative_part
BEGIN
process_statements
[wait_statement] Either but not both
END PROCESS;

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Example Sensitivity List
process triggered: all
staments executed
• Process with sensitivity list:
ex_p: PROCESS(a,b)
BEGIN
c <= a AND b;
END PROCESS ex_p;
• Process is executed when value of a or b changes
– Type of a and b can be arbitrary: scalar, array, enumeration, or record
– ex_p is a user defined label (recommended)

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Example (2)
• The same process with wait statement:
PROCESS Wait for change on a or b,
BEGIN as in prev slide
WAIT ON a,b;
c <= a AND b;
END PROCESS;
• Bad process with incomplete sensitivity
list: Trigger only when
PROCESS(a) a changes
BEGIN
c <= a AND b; Not evaluated when b changes
(simulation does not match synthesis
END PROCESS; !!!). superbad. 19.10.2015 53
 Example: Last Assignment Is Kept
ENTITY Pitfall1 IS
END Pitfall1;
ARCHITECTURE behav OF
Pitfall1 IS
SIGNAL A, B, C :
std_logic;
BEGIN
A <= ’1’ AFTER 5
ns,
Input wave ’0’ AFTER 15 ns,
generation, ’1’ AFTER 25 ns;
(sim only) B <= ’1’ AFTER 0
ns,
’0’ AFTER 10 ns,
’1’ AFTER 20 ns;
PROCESS (A, B)
OK BEGIN -- process
C <= A;
...
C <= B;
END PROCESS;
END behav;

Only the last assignment, C <= B; ,is kept.

However, this is also useful. In a complex process, designer can assign a default 19.10.2015 54
value at first and then overrride it later in some branch.
 Concurrent vs. Sequential VHDL
-- architecture -- process

Modeling style
Location Inside architecture Inside process or function
Example statements process, component instance, concurrent if, for, switch-case, signal assignment,
signal assignment variable assignment

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Concurrent vs. Sequential VHDL: Example
ARCHITECTURE rtl OF rotate_left IS
SIGNAL rot_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
shift : PROCESS(rst, clk)
BEGIN
IF (rst = ’1’) THEN
rot_r <= (others =>’0’); -- reset the register
Concurrent

Sequential ELSIF (clk = ’1’ AND clk’EVENT) THEN

IF (load_en_in = ’1’) THEN
rot_r <= data_in; -- store new value
ELSE
rot_r (7 DOWNTO 1)<= rot_r(6 DOWNTO 0);
rot_r (0) <= rot_r(7);
END IF;
END IF;
END PROCESS;
q_out <= rot_r; -- connect DFF’s output to output port
END concurrent_and_sequential;

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2c. Signals, Variables, Constants

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Signals
• Signals carry the data
• Two possible assignment styles:
1. Sequential signal assignments
– Inside a process
– Evaluated only whenever a process is triggered, e.g., every clock cycle
2. Concurrent signal assignments
– Outside any process
– Used in the concurrent portion of the architecture
• Typically these are simple signal-to-output or signal-to-signal assignments
– ”Always-on” assignments, continuously evaluated
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Signals (2)
• Signal assignment operator is <=
– NOTE: Sequential and concurrent signal assignments look similar
– They are distinguished by their location on code (inside or outside a process)
– General form:
target <= [transport] expr
[after t_expr{, expr after t_expr}];
– Assigns a future and/or current value(s)
• Entity’s ports are also signals
– Note that an out-port cannot be read
• Signal is declared outside the processes
– In the architecture declaration
• Location and right-hand side of the assignment infer some combinatorial logic (e.g.,
addition) or just a simple wire
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1. Sequential Signal Assignments
• Signal assignment inside a process (or a subprogram)
• Assignments are executed every time an event occurs on any of the signals in the sensitivity list of the process
• A process can have only one driver for a signal
– Assignments are scheduled and do not occur until the process has been suspended
– The last assignment takes effect when the process suspends
• Example: data_in has changed from 5 to 1 (note that order of assignments does not actually matter here)

PROCESS (clk, rst_n) rst_n

BEGIN
IF (rst_n = ‘0’) THEN
. . . data_in b_r c_r
ELSIF (clk’EVENT AND clk=‘1’) THEN
b_r <= data_in; -- b is set to 1
c_r <= b_r; -- c gets the old value of b, i.e. 5
END IF;
END; clk

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2a) Concurrent Signal Assignments
• Happens outside a process
• Assignment is executed any time an event occurs in the right-hand side
• Examples
a <= ‘1’; -- These two are
data_out <= data_r; -- the most common

• (test bench code can use delays, after ignored in synthesis):

color <= red after 5 ns, yellow after 1 ns;
line <= transport b after 1 ps;

-- After/transport delays are used only in

-- simulation. Synthesis does create an
-- assignment but without any delay (just
-- a wire)

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1,2) Conditional Signal Assignment
• Concurrently:
target <= value1 WHEN cond1 ELSE
value2 WHEN cond2 ELSE
value3;
• Equivalent process:
PROCESS(cond1,cond2,value1,value2,value3)
BEGIN
IF cond1 THEN
target <= value1;
ELSIF cond2
target <= value2;
ELSE
target <= value3;
END IF;
END PROCESS;

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1,2) Selected Signal Assignments
• Concurrently:
WITH expression SELECT
target <= value1 WHEN choice1,
value2 WHEN choice2, Note that only a single case branch is
value3 WHEN OTHERS;
• Equivalent process: executed. (No need for break commands
PROCESS(expression,value1,value2,value3) like in C)
BEGIN
CASE expression IS
WHEN choice1 => Unfortunately, case has some limitations
target <= value1; compared to if-elsif. Expression must be
WHEN choice2 =>
target <= value2; ’locally static’ , i.e. value can be
WHEN OTHERS => determined inside the design where it
target <= value3;
END CASE; appears. E.g. actual value of a generic
END PROCESS; can be set from upper level, so it’s not
locally static
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VHDL Semantics
• If a process is executed and a certain signal is not assigned, it will keep its previous value
– Good and bad sides…
– Example:

implies

--’0’ to create XNOR

= results in latch!
(in comb. processes, always include the else-branch)

Note that this feature simplifies sequential processes.

Note also that eq is never nullified in example. Once it’s high, it stays high until the
end of the world.
Variables
• A storage facility with a single current value
• Variable value changes instantly as opposed to signal
– Somewhat alike to variables in C/C++
– But differs in many ways from regular programming languages
• Can be used in:
1. Processes
2. Functions
3. Procedures
• No global variables in VHDL’87. They are local to a process or a function.

PROCESS (...)
VARIABLE Q1_v : STD_LOGIC;
BEGIN -- PROCESS
Q1_v := ‘0’;
Q2_v := not Q1_v; -- Q2 sees the “new” value of Q1

Arto Perttula 19.10.2015 65

Variables (2)
• Note: variable assignment operator is :=
• Variables should only be used as an intermediate storage
– Short-hand notation to beautify the code
tmp_v := arr_a(i) and arr_b(i) and
arr_c(enable_index_c)…;
tf (tmp_v = ’1’) then
d_out <= tmp_v or…
• Variables in processes retain their values during simulation, but in functions and procedures they
do not
• However, never re-use variable value between iterations!
– Re-using the variable value may result in combinatorial feedback loop, which can be a catastrophe
– Re-using the variable obfuscates the code
• Variables are slightly faster to simulate than signals
• Not recommended for processes. More info later why not.

Arto Perttula 19.10.2015 66

Constants
• An object that has a constant value and cannot be changed
• the value of contant is assigned when constant is declared
• May be declared globally (within packages) or locally
– Constant declarations can be located in any declaration are
• Clarify the code because magic numbers get a symbolical,
decriptive name

CONSTANT send_data_c : BOOLEAN := TRUE;

CONSTANT base_addr_c : STD_LOGIC_VECTOR(8-1 DOWNTO 0)
:= “10010001”;
Arto Perttula 19.10.2015 67
2d. Types in VHDL

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
Arto Perttula 19.10.2015 68
Types
• VHDL is strongly typed language
1. Scalar types
– integer types
– enumeration types
– physical types
– real (floating point) types
2. Composite types
– array types
– record types
3. File types
4. Access types
Arto Perttula 19.10.2015 69
http://www.cs.umbc.edu/help/VHDL/types.html

• types-+-scalar----+-discrete-------+-integer-------+-integer
• | | | +-natural
• | | | +-positive
• | | |
• | | -enumeration---+-boolean
• | | +-bit
• | | +-character
• | | +-file_open_kind
• | | +-file_open_status
• | | +-severity_level
• | |
• | +-floating point-+-----------------real
• | |
• | +-physical-------+-----------------delay_length
• | +-----------------time
• |
• +-composite-+-array----------+-constrained-
• | | |
• | | +-unconstrained-+-bit_vector
• | | +-string
• | |
• | +-record-
• |
• +-file-
• |
• +-access

Arto Perttula 19.10.2015 70

1a. Scalar Types: Integer
• Minimum range (in VHDL ’87):
– Symmetric 32-bit range
– From -2147483647 to +2147483647
– i.e., –(231-1) to 231–1
– Simulator dependent, can be larger
• Predefined integer types (built-in standard package):
TYPE INTEGER IS RANGE -xxxx TO yyyy;
SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGER’HIGH
SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER’HIGH

• Examples of user defined integer types:

TYPE bit_int IS INTEGER RANGE 0 TO 1;
TYPE byte IS INTEGER RANGE 0 TO 255;
TYPE word IS INTEGER RANGE 0 TO 65535;
-- You should define integer range explicitly to avoid
-- area and delay overheads.

Arto Perttula 19.10.2015 71

Peculiarities of Integer
• Omitting negative values does not increase maximum value
– Although in C/C++ it does
– Note thename; unsigned is separate type (vector)
– There is no (confusing) specifier long either
• VHDL standard defines that integer must support 32-bit ”one’s complement range”
– This way inverse number is always valid
• However, RTL Synthesis standard specifies that signed integer should be
represented in two’s complement, supporting range of -(231) to 231-1
– The range of the used tool can be checked with attribute, integer’low and
integer’high
– ModelSim and Quartus support this range
– http://ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&isnumber=18052&arnumber=836335&punum
ber=6748
Arto Perttula 19.10.2015 72
1b. Scalar Types: Enumeration
• Has a set of user defined values
• Ordered
• Pre-defined: BIT, BOOLEAN, SEVERITY_LEVEL, CHARACTER
• Examples of enumeration type declarations:
TYPE SEVERITY_LEVEL IS (NOTE,WARNING,ERROR,FAILURE);
TYPE BIT IS (‘0’, ‘1’); -- package STD
TYPE mybit IS (‘0’, ‘1’, ‘X’, ‘Z’);
TYPE opcode IS (add, sub, lda);
TYPE state IS (idle, start, read, stop);
• NOTE:
– Enumeration literals can be overloaded. Look definitions of BIT and mybit.
– Type of the enumeration literal must be determinable from the context
Arto Perttula 19.10.2015 73
1c. Scalar Types: Real
• REAL is the only predefined floating point type
• Minimum range from -1E38 to +1E38
– Simulator (implementation) dependent
• Examples:
TYPE int_real IS REAL RANGE -2147483647.0 TO +2147483647.0; Not
-- Conversion from integer to real as follows
r := REAL(i);
necessarily
synthesizable
!
• NOTE:
– Some synthesis tools may support floating point types. To be safe, use only in simulation.
– Fixed-point representation is often accurate enough
– http://www.eda.org/fphdl/

Arto Perttula 19.10.2015 74

1d. Scalar Types: Physical
• Represent physical quantities
• TIME: minimum range from -2147483647 to +2147483647, 32 bit range
– only for simulation
– not synthesizable, there isn’t logic to produce accurate arbitrary delay
– very much simulator dependent
TYPE TIME IS RANGE -1E18 to 1E18
UNITS
fs; Not
ps = 1000 fs;
ns = 1000 ps; synthesizable
us = 1000 ns;
ms = 1000 us; !
sec = 1000 ms;
min = 60 sec;
END UNITS;

Arto Perttula 19.10.2015 75

2a. Composite Type: Array
• A collection of one or more values or objects of the same type
• Strong typing forces you to define a new array type before using it
• Unconstrained and constrained declarations possible
– Unconstrained declarations are good for re-using and generic
descriptions
• Support slicing: one-dimendional array is created constraining a
larger array
• Arrays can be returned from functions
• Multidimensional arrays possible
– >3D may not be supported in synthesis
Arto Perttula 19.10.2015 76
2a. Composite Type: Array (2)
• Indexed with regular parentheses ’()’
• Examples:
TYPE bit_vector IS ARRAY ( NATURAL RANGE <> ) OF BIT
TYPE defvec IS ARRAY (1 to 10) OF BIT;

TYPE string IS ARRAY ( POSITIVE RANGE <> )

OF BIT;

TYPE matrix IS ARRAY ( INTEGER RANGE <>,

INTEGER RANGE <>)
OF BIT;

-- using unconstrained array needs bounds

SIGNAL addr_r : bit_vector (7 downto 0);
SIGNAL ctrl_c : defvec;
Arto Perttula 19.10.2015 77
2b. Composite Type: Record
• Collection of objects with same class
– constant, variable or signal
• Elements can be of any type
• Fields can be referenced with selected name notation (recname.fieldname)
TYPE location IS RECORD
x : INTEGER;
y: INTEGER;
END RECORD;
TYPE ififo IS RECORD
rd_ptr: INTEGER;
wr_ptr: INTEGER;
data : real_array;
END RECORD;
SIGNAL coord_r : location;
...
coord_r.x <= 42;
y_out <= coord_r.y;

Arto Perttula 19.10.2015 78

3. File Handling: VHDL ’87
• Sequential stream of objects
– Last file element is end of file (EOF) mark
– File elements can be read (file is IN mode)
– Elements can be written to file (file is OUT mode)
• Built-in file type declaration:
TYPE <type_name> IS FILE OF <object_type>;
• User’s file object declaration
FILE file_identifier : <type_name> IS MODE <file_name>;
• Procedure READ(file,data) reads data from file
• Procedure WRITE(file,data) writes data to file
• Function ENDFILE(file) checks EOF
Not
synthesizable
• Package STD.TEXTIO contains functions for text file manipulation
• File path is relative to simulation directory
!
– Not the VHDL source code directory
Arto Perttula 19.10.2015 79
3. File Example in VHDL ’87
access_files : process (clk, rst_n)
-- vhd'87 syntax
file my_in_file : text is in "input.txt";
file my_out_file : text is out "output.txt";
variable in_line_v, out_line_v : line;
variable tmp_v : integer := 0;
begin
if rst_n = '0' then
-- …
elsif (clk'event and clk = '1') then
while (not ENDFILE(my_in_file)) loop

READLINE(my_in_file, in_line_v);
READ(in_line_v, tmp_v);
-- many flavors of read() available

WRITE(out_line_v, tmp_v);
WRITELINE(my_out_file, out_line_v);
end loop;
end if;
end process access_files;

Arto Perttula 19.10.2015 80

3. Whole ’87 Example (2)
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity test_file87 is
end test_file87;
architecture behav of test_file87 is
signal clk : std_logic := '0';
signal rst_n : std_logic;
begin -- behav
rst_n <= '0', '1' after 50 ns;
clk <= not clk after 10 ns;
access_files : process (clk, rst_n)
-- vhd'87 syntax
file my_in_file : text is in "input.txt";
file my_out_file : text is out "output.txt";
variable in_line_v, out_line_v : line; -- type "LINE" is a pointer to a string
variable tmp_v : integer := 0;
begin
if rst_n = '0' then -- asynchronous reset (active low)

elsif (clk'event and clk = '1') then -- rising clock edge

while (not ENDFILE(my_in_file)) loop

-- This loop reads the whole file in single clk cycle.
-- Only the first string from each line is converted to
-- integer and the rest are ignored.
-- Runtime error occurs if a line does not start with integer.
READLINE(my_in_file, in_line_v);
READ(in_line_v, tmp_v); -- many flavors of read() available
WRITE(out_line_v, tmp_v);
WRITELINE(my_out_file, out_line_v);
end loop;

end if;
end process access_files;
end behav;

Arto Perttula 19.10.2015 81

3. File Types: VHDL ’93
• Quite silmilar to ’87 but files can be opened and closed as needed
• File operations in VHDL ’93:
FILE_OPEN(<file_identifier>, <file_name>, <file_mode>);
FILE_OPEN(<status>, <file_identifier>, <file_name>, <file_mode>); Not
FILE_CLOSE(<file_identifier>); synthesizable
!
• File modes are:
– READ_MODE (file is read-only)
– WRITE_MODE (file is write-only, initially empty)
– APPEND_MODE (file is write-only, output will be added to the end of the file)
Common usage
for files: testbench
check ok?
design under output vectors,
input vectors verification trace, statistics
clk (DUV)

19.10.2015 82
More Complex Example in VHDL’93
access_files : process (clk, rst_n)
-- vhd'93 syntax, only these 2 lines differ from previous in minimal case
file my_in_file : text open read_mode is "input.txt";
file my_out_file : text open write_mode is "output.txt";
variable in_line_v, out_line_v : line;
variable tmp_v : integer;
variable valid_number : boolean := false;
variable curr_line : integer := 0;
begin
if rst_n = '0' then -- asynchronous reset (active low)
…
elsif (clk'event and clk = '1') then -- rising clock edge
valid_number := false;
-- Loop until finding a line that is not a comment.
while valid_number = false and not(endfile(my_in_file)) loop

READLINE(my_in_file, in_line_v); -- a) read from file, b) from terminal: READLINE(input, in_line_v);

READ (in_line_v, tmp_v, valid_number); -- 3rd param tells if ok
curr_line := curr_line+1; -- just for reporting

if valid_number = false then

report "Skipped the line “ & integer'image(curr_line) & " ( it’s comment or malformed)” severity note;
next; -- start new loop interation
end if;

-- Another way for debug printing, LF = line feed = new line

write (output,string'(“Got value " & integer'image(tmp_v)& " at t:" & time'image(now) & LF));

WRITE(out_line_v, tmp_v);
WRITELINE(my_out_file, out_line_v); -- a) write to file, b) to terminal: WRITELINE(output, out_line_v);
end loop;
end if;
end process access_files;

Arto Perttula 19.10.2015 83

4. Access Types
• Very similar to C pointers (suitable for LIFO/FIFO modelling)
• Two predefined functions NEW and DEALLOCATE
• Only variables can be declared as access type
• Very rare. Not synthesizable.
• Example declaration and usage of new and deallocate:
TYPE point_loc IS ACCESS LOCATION;
VARIABLE pl1_v, pl2_v, pl3_v: point_loc;

pl1_v := NEW location; -- new object is created

pl2_v := pl1; -- pl1 points to same obj as pl2
Not
pl3_v := NEW location; synthesizable
pl1_v := pl3_v; !
DEALLOCATE(pl2_v);

Arto Perttula 19.10.2015 84

 Summary of VHDL Types
Type name Sim. only Note

std_logic, std_logic_vector Actually enumeration, you’ll need pkg ieee_1164,

use these instead of bit/bit_vector, use downto indexing

integer Limit range for synthesis

unsigned, signed Similar to std_logic_vector, but safer for artihmetic
most common

array E.g. std_logic_vector is array. Define the array type first and then
signal/constnat/variable of that type

enumeration bit and std_logic are actually enumerations,

use this at least for states of an FSM
record Synthesizable, but not very common
file x For reading input data and storing trace/log during simulation-based verification

physical x For detailed gate-level simulation with timing

real x Quite rare because cannot be (always) synthesized
access x Very rare

Arto Perttula 19.10.2015 85

2e. Packages

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
Arto Perttula 19.10.2015 86
Packages
• Meant for encapsulating data which can be shared globally among several design units
• Consists of declaration part and optionally body part design_0.
• Package declaration can contain: vhd
– type and subtype declarations
– subprograms
– constants, alias declarations System_ design_1.
– file declarations pkg.vhd vhd
– global signal declarations
– component declarations

…
• Package body consists of
– type and subtype declarations
– subprogram declarations and bodies
design_n.
– deferred constants (avoids some re-compilation, rare concept)
vhd
– file declarations

Arto Perttula 19.10.2015 87

Package Example
PACKAGE example_pkg IS
CONSTANT example_c : STD_LOGIC := ’1’;
FUNCTION integer_to_vector
(size : INTEGER; number : INTEGER)
RETURN STD_LOGIC_VECTOR;
END example_pkg;

PACKAGE BODY example_pkg IS

FUNCTION integer_to_vector
(size : INTEGER; number : INTEGER)
RETURN STD_LOGIC_VECTOR IS
... --insert the implementation here
END integer_to_vector;
END example_pkg;
Arto Perttula 19.10.2015 88
Package Example (2)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_NUMERIC.all;

PACKAGE io_pkg IS
CONSTANT addr_width_c : NATURAL := 16;
CONSTANT data_width_c : NATURAL := 16;
CONSTANT stat_c : NATURAL := 1;
CONSTANT total_out_c : NATURAL := 10;
TYPE o_bits_arr IS ARRAY (0 to total_out-1)
OF NATURAL;
FUNCTION inmux(
data : STD_LOGIC_VECTOR(data_width_c-1 downto 0);
sel : NATURAL)
RETURN STD_LOGIC_VECTOR;
END io_pkg;

-- Function inmux will be defined in package body

Arto Perttula 19.10.2015 89

Libraries
• Collection of compiled VHDL design units (database)
1. Packages (declaration + body)
2. Entities (entity declaration)
3. Architectures (architecture body)
4. Configurations (defines comp-arch pairs)
• Some pre-defined, e.g., STD and IEEE
• One can also create own libraries
– At least a library called work
• To use, e.g., package, it must be compiled to some library first
(typically to work)
Arto Perttula 19.10.2015 90
Libraries (2)
• All entity names etc. must be unique within a library
• If you make two different entities with the same name,
e.g., fifo, you must compile them into separate
libraries
• You must define which fifo to use for each component
instance
– Either during instantiation or with separate configuration

Arto Perttula 19.10.2015 91

Using Packages And Components
1. Packages and entities are first compiled into some library (subdirectory on hard
disk)
– Compilation command in ModelSim is vcom
2. Command vlib tells the path to ModelSim
– VHDL file can refer to that library with symbolic name like ieee or work
3. In VHDL file, introduce first what libraries are used
– work is the default name, no need to introduce
4. Then, tell what packages are used
5. Then, tell what stuff is used from the package
– Function name, types etc., usually ”all”
library <libname>;
use <libname>.<pkg_name>.<stuff>;
Arto Perttula 19.10.2015 92
Using Packages And Components (2)

• Standard IEEE packages are the most common

– Compiled automatically during the ModelSim installation
– Referred using symbolic name ieee
– Most common package is std_logic_1164
• Sometimes, you need others
– E.g., special simulation models for FPGA-related primitive
components

Arto Perttula 19.10.2015 93

Browsing the Package Contents
a) Read the files directly from installation directory
– Something like: prog/mentor/modeltech-6.3a/modeltech/vhdl_src/ieee/stdlogic.vhd
b) Start simulation of a design with ModelSim, open either tab ”sim” or ”Files”, and double-click some package

A package used in
this design

Double-clicking opens the

source code for the
package

94
2f. Standard Packages

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
Arto Perttula 19.10.2015 95
Data Types of Standard VHDL
• integer:
– Minimal range: -(231-1) to 231-1
– Two subtypes: natural, positive
• boolean: (false, true)
• bit: (‘0’, ‘1’)
– Not capable enough, but we’ll return to that…
• bit_vector: a one-dimensional array of bit

Arto Perttula 19.10.2015 96

Operators in Standard VHDL

Arto Perttula 19.10.2015 97

Operators (2)

Arto Perttula 19.10.2015 98

Concatenation
• Concatenation operator (&)
• Attaches multiple signals together into array
y <= "00" & a(7 DOWNTO 2);
y <= a(7) & a(7) & a(7 DOWNTO 2);
y <= a(1 DOWNTO 0) & a(7 DOWNTO 2);
7 2 0 7 2 0 7 0

a a a

... ... ...

y ”00” y y
7 6 5 0 7 6 5 0 7 6 5 0
Array Aggregate
• Aggregate is a VHDL construct to assign a value to an array-typed object
• Different types supported, e.g.,
a <= "10100000"; --direct
a <= (7=>'1', 6=>'0', 0=>'0', 1=>'0',
5=>'1', 4=>'0', 3=>'0', 2=>'1');
a <= (7|5=>'1', 6|4|3|2|1|0=>'0');
a <= (7|5=>'1', others=>'0');
• E.g., setting all elements at the same time
a <= "00000000“ -- Size of a has to be known
a <= (others=>'0'); -- Size not needed, Flexible, Good
-- for reset. Superb!

Arto Perttula 19.10.2015 100

IEEE std_logic_1164 Package
• ’Bit’ is too limited having only 2 possible values
• Introduce extended data types
– std_logic
– std_logic_vector
• std_logic: 9 values: (’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’)
– ’0’, ’1’; forcing logic 0 and forcing logic 1
– ’Z’: high-impedance, as in tri-state buffer
– ’L’, ’H’: weak logic 0 and weak logic 1
• As in wired-OR and wired-AND logic (pull-down/pull-up resistors)
– ’X’, ’W’: ”unknown” and ”weak unknown”
– ’U’: for uninitialized
– ’-’: don’t care

Arto Perttula 19.10.2015 101

IEEE std_logic_1164 Package (2)
• std_logic_vector
– An array of elements with std_logic data type
– Implies a bus (=set of signals)
• Recommended form is descending range
signal a : std_logic_vector(7 downto 0);
• Another form (less desired, do not use)
signal b : std_logic_vector(0 to 7);
– Always be consistent within a design
– Assigning a<=b or b<=a will be confusing
• Need to invoke package to use the data type:
library ieee;
use ieee.std_logic_1164.all;
Arto Perttula 19.10.2015 102
Overloaded Operator
IEEE std_logic_1164 Package
• Which standard VHDL operators can be applied to std_logic and std_logic_vector?
• Overloading: same operator of different data types
• Overloaded operators in std_logic_1164 package

Note: that shift is not defined

for std_logic_vector. Use
slicing and concatenation. Arto Perttula 19.10.2015 103
Type Conversion
• Type conversion is crucial in strongly typed language, such as VHDL
• Type conversion function in std_logic_1164 package:

Arto Perttula 19.10.2015 104

Examples of Type Conversions
• E.g.,

Arto Perttula 19.10.2015 105

IEEE numeric_std Package
• How to infer arithmetic operators?
• In standard VHDL:
signal a, b, sum: integer;
. . .
sum <= a + b;
• What’s wrong with integer data type?
– Negative or positive representation of the number
– Integer is typically 32-bit
• Default range is also 32-bit, synthesis tools may not optimize
• Note the range -(231-1) to 231-1
• I.e., 0 to 232-1 not supported!
Arto Perttula 19.10.2015 106
IEEE numeric_std Package (2)
• IEEE numeric_std package: define integer as an array of elements of
std_logic
• Two new data types: unsigned, signed
• The array interpreted as an unsigned or signed binary number, respectively
– Unsigned are represented as standard binary
– Signed vectors are represented using two’s complement
• E.g.,
signal x, y: signed(15 downto 0);
• Need to invoke package to use the data type
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Arto Perttula 19.10.2015 107
Overloaded Operators in
IEEE numeric_std Package

Arto Perttula 19.10.2015 108

New Functions in IEEE
numeric_std Package

Note: that these

are functions, not
operators.

Arto Perttula 19.10.2015 109

Operator Overloading Example
-- this internal function computes the addition
• Operator overloading is a declaration of a function whose
-- of two UNSIGNED with input CARRY
designator is an operator symbol -- * the two arguments are of the same length
– Note the double quotes around the symbol
package body NUMERIC_STD is function ADD_UNSIGNED (L, R: UNSIGNED;
. . . C: STD_LOGIC) return UNSIGNED is
-- Result subtype: UNSIGNED(MAX(L'LENGTH, -- constant L_LEFT: INTEGER := L'LENGTH-1;
-- R'LENGTH)-1 downto 0). alias XL: UNSIGNED(L_LEFT downto 0) is L;
-- Result: Adds two UNSIGNED vectors that may be of alias XR: UNSIGNED(L_LEFT downto 0) is R;
-- different lengths. variable RESULT: UNSIGNED(L_LEFT downto 0);
function "+" (L, R: UNSIGNED) return UNSIGNED is variable CBIT: STD_LOGIC := C;
constant SIZE: NATURAL := MAX(L'LENGTH, R'LENGTH); begin
variable L01 : UNSIGNED(SIZE-1 downto 0); for I in 0 to L_LEFT loop
variable R01 : UNSIGNED(SIZE-1 downto 0); RESULT(I) := CBIT xor XL(I) xor XR(I);
begin CBIT := (CBIT and XL(I))
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then or (CBIT and XR(I))
return NAU; end if; or (XL(I) and XR(I));
end loop;
L01 := TO_01(RESIZE(L, SIZE), 'X'); return RESULT;
if (L01(L01'LEFT)='X') then return L01; end ADD_UNSIGNED;
end if;

R01 := TO_01(RESIZE(R, SIZE), 'X');

if (R01(R01'LEFT)='X') then return R01;
end if;

return ADD_UNSIGNED(L01, R01, '0');

end "+";
. . .

Arto Perttula 19.10.2015 110

Operators Over an Array Data Type
• Relational operators for array
– Operands must have same element type
– But their lengths may differ! Be careful!
• Two arrays are compared element by element, starting from the left
– If an array has less bits, it is considered smaller if compared bits are equal
(std_logic_vector)
• All the following return true
• “011“ = “011“
• “011“ > “010“
• “011“ > “00010“
• “0110“ > “011“

Arto Perttula 19.10.2015 111

Operators Over an Array Data Type
• a = 2 bits wide, b = 3 or 4 bits wide:
a b a > b, std_logic_vector a > b, unsigned
11 000 1 1
11 011 1 0
11 0111 1 0
11 110 0 0
00 001 0 0
00 000 0 0

• Problems: consider std_logic_vector ’if a = b then’

– If a and b have different length, the expression is always false!
– Syntactically correct so no warning/error
– => Use always unsigned/signed data type for values (that need to be compared)
– std_logic_vector only for ”general” control and ports

Arto Perttula 19.10.2015 112

Type Conversion
• std_logic_vector, unsigned and signed are defined as an array of
elements of std_logic
• They are considered as three different data types in VHDL
• Type conversion between data types:
a) Type conversion function
b) Type casting (for ”closely related” data types)
• Sometimes operands must be resized to same size, e.g., both to 16
bits

Arto Perttula 19.10.2015 113

Example
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
. . .
signal s1, s2, s3, s4, s5, s6:
std_logic_vector(3 downto 0);

signal u1, u2, u3, u4, u6, u7:

unsigned(3 downto 0);

signal sg: signed(3 downto 0);

Arto Perttula 19.10.2015 114

Example (continued)
-- Ok
u3 <= u2 + u1; -- ok, both operands unsigned

u4 <= u2 + 1; -- ok, unsigned and natural operands

-- Wrong
u5 <= sg; -- type mismatch
u6 <= 5; -- type mismatch, 5 is integer/natural

-- Fixed
u5 <= unsigned(sg); -- type casting
u6 <= to_unsigned(5,4); -- use conversion function,
-- use 4 bits to represent
-- the value 5
Arto Perttula 19.10.2015 115
Example (continued 2)
-- Wrong
u7 <= sg + u1; -- + undefined over these types

-- Fixed
u7 <= unsigned(sg) + u1; -- ok, but be careful

-- Wrong
s3 <= u3; -- type mismatch
s4 <= 5; -- type mismatch
-- Fixed
s3 <= std_logic_vector(u3); -- type casting
s4 <= std_logic_vector(to_unsigned(5,4));

Arto Perttula 19.10.2015 116

Example (continued 3)
-- Wrong
s5 <= s2 + s1; -- + undefined
-- over std_logic_vector

s6 <= s2 + 1; -- + undefined for

-- std_logic_vector

-- Fixed
s5 <= std_logic_vector(unsigned(s2)
+ unsigned(s1));

s6 <= std_logic_vector(unsigned(s2) + 1);

Arto Perttula 19.10.2015 117

Conversion Example HW
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
r=
entity addsub is r=
port (
a,b: in std_logic_vector(7 downto 0);
ctrl: in std_logic;
r: out std_logic_vector(7 downto 0)
);
end addsub;

architecture direct_arch of addsub is

signal src0, src1, res:
signed(7 downto 0);
begin • Only a single line implements all the HW!
src0 <= signed(a); • No logic from the conversions!
src1 <= signed(b); • Exact HW for ”+” and ”-” operations do not
res <= src0 + src1 when ctrl='0' else have to be specified, tool will select
src0 - src1;
appropriate
r <= std_logic_vector(res);
• It is possible to code own
end direct_arch;
implementation, also

Arto Perttula 19.10.2015 118

Resize() in numeric_std.vhdl
--===========================================================================
-- RESIZE Functions
--===========================================================================

-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.

-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.

Arto Perttula 19.10.2015 119

Resize in Action
• Original data width 4b (u_counter_r, sg_counter_r) is resized to 2b and 8b

Radix=
unsigned
hex signed
hex
Note: showing values in hex format is bit misleading with negative numbers 19.10.2015 120
Resize() in numeric_std.vhdl (2)
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias INVEC: SIGNED(ARG'LENGTH-1 downto 0) is ARG;
variable RESULT: SIGNED(NEW_SIZE-1 downto 0) := (others => '0');
constant BOUND: INTEGER := MIN(ARG'LENGTH, RESULT'LENGTH)-2;
begin
if (NEW_SIZE < 1) then return NAS;
end if;
if (ARG'LENGTH = 0) then return RESULT;
end if;
RESULT := (others => ARG(ARG'LEFT)); -- sign extension
if BOUND >= 0 then
RESULT(BOUND downto 0) := INVEC(BOUND downto 0);
end if;
return RESULT;
end RESIZE;

-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT: INTEGER := ARG'LENGTH-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others => '0');
begin
if (NEW_SIZE < 1) then return NAU;
end if;
if XARG'LENGTH =0 then return RESULT;
end if;
if (RESULT'LENGTH < ARG'LENGTH) then
RESULT(RESULT'LEFT downto 0) := XARG(RESULT'LEFT downto 0);
else
RESULT(RESULT'LEFT downto XARG'LEFT+1) := (others => '0');
RESULT(XARG'LEFT downto 0) := XARG;
end if;
return RESULT;
end RESIZE;

Arto Perttula 19.10.2015 121

Conversion And Resize Summary
From type To type Conversion function

std_logic_vector unsigned unsigned( arg )

std_logic_vector signed signed( arg )

unsigned std_logic_vector std_logic_vector( arg )

signed std_logic_vector std_logic_vector( arg )

integer unsigned to_unsigned( arg, size )

integer signed to_signed( arg, size )

unsigned integer to_integer( arg )

signed integer to_integer( arg )

integer std_logic_vector integer -> unsigned/signed -> std_logic_vector

std_logic_vector integer std_logic_vector -> unsigned/signed -> integer

unsigned + unsigned std_logic_vector std_logic_vector( arg1 + arg2 )

signed + signed std_logic_vector std_logic_vector( arg1 + arg2 )

Type Resize function

unsigned resize( arg, size )

signed resize( arg, size )

http://www.tkt.cs.tut.fi/kurssit/50200/S14/Harjoitukset/conversion.html

Arto Perttula 19.10.2015 122

Non-IEEE Package
• Several supported non-IEEE packages exists
• Packages by Synopsys
• std_logic_arith:
– Similarities with numeric_std
• Cannot be used at the same time
– New data types: unsigned, signed
– Details are different
• std_logic_unsigned / std_logic_signed
– Treat std_logic_vector as unsigned and signed numbers
– i.e., overload std_logic_vector with arith operations
• USE NUMERIC_STD
– It is the standard and implementation is known and portable

Arto Perttula 19.10.2015 123

2g. Attributes

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
Arto Perttula 19.10.2015 124
Attributes
• A special identifier used to return or specify information about a
named object
• Denote values, functions, types, signals, or ranges associated with
various kinds of elements
• Predefined (a part of the VHDL’87) and user defined
• Predefined attributes are always applied to a prefix
• Used instead of fixed values or constants (unless the value is known
and very unlikely to be modified)
 Code is easier to maintain and reuse

Arto Perttula 19.10.2015 125

Attributes (2)
• Predefined attributes
• Notation in the examples:
– t = scalar type or subtype, e.g., integer
– a = array type, e.g., std_logic_vector(3 downto 0)
– s = signal, e.g., std_logic

• There are 5 kinds of attributes

1. Value kind attributes, return a constant value
– Return an explicit value and are applied to a type or subtype
– t’high, t’low
– t’left, t’right
– a’length[(n)]
2. Type, return a type: (t’base)
3. Range, return a range: (a’range, a’reverse_range)
Arto Perttula 19.10.2015 126
Attributes (3)
4. Function, call a function that returns a value:
– Attributes that return information about a given type, signal, or array value
– s’event, s’active, s’last_event, s’last_active, s’last_value
– t’pos(x), t’val(x), t’succ(x), t’pred(x), t’leftof(x), t’rightof(x)
– a’left[(n)], a’right[(n)], a’high[(n)], a’low[(n)]
5. Signal, create a new implicit signal:
– s’delayed [(t)], s’stable[(t)], s’quiet[(t)], s’transaction
• User defined
– Only constants possible
• Only a few are commonly needed

Arto Perttula 19.10.2015 127

Attributes: event
• Returns value true if an event occured (signal has changed its value) during the current delta, and
otherwise returns value false
• General form:
S’EVENT
• Example:
PROCESS(clk)
BEGIN
IF clk’EVENT AND clk=’1’ THEN
q <= d;
END IF;
END PROCESS;
• NOTE:
Typical way to model flip-flop behavior
– Use only for clock signal
– Can be used in synthesis
– Cannot be nested!
Arto Perttula 19.10.2015 128
Attributes: low
• Returns the lower bound of array object or type
• General form:
T’LOW and A’LOW [(N)]
• Example:
...
VARIABLE c,b: BIT_VECTOR(5 DOWNTO 0);
...
FOR i IN c’LOW TO 5 LOOP
c(i) := b(i); -- i goes from 0 to 5
END LOOP;

• T’LOW is value kind of attribute and A’LOW is function kind of attribute

Arto Perttula 19.10.2015 129

Attributes: left
• Returns the left-most element index of a given type or subtype
• General form:
T’LEFT

• Example:
...
TYPE bit_array IS ARRAY (5 DOWNTO 1) OF BIT;
...
SIGNAL tmp_r : INTEGER;
...
tmp_r <= bit_array’LEFT;
-- tmp_r is assigned with a value of 5

Arto Perttula 19.10.2015 130

Array Attributes
TYPE v41 IS (’X’, ’0’, ’1’, ’Z’);
TYPE v4l_4by8 is ARRAY (3 downto 0, 0 to 7) of v41;
Signal s_4by8 : v41_4by8;

More info about

attributes in the
extra section

Source: Zainalabedin Navabi, VHDL: Modular Design and Synthesis of Cores and Systems
19.10.2015 131
VHDL Summary
Language Purpose Other notes C++ counterpart
constructs in VHDL

ENTITY Defines interface. Includes generics and ports ”Public interface”, the actual implementation is Class definition
(their names, widths, and directions). hidden into architecture.

GENERIC Instance-specific constant value Excellent idea in HDL! Constant parameters, templates

PORT I/O pin of an entity. Defines direction and type. See also signal. Method of a class, inter-process
message

ARCHITECTURE Contains functionality. One entity may have many architectures in the Class implementation
library

SIGNAL, Communication channel between They are not the same! Variables only inside Variable
(VARIABLE) components/processes. processes

COMPONENT For instantiating a sub-block Needed for hierarchy. Class instance, object

PROCESS These capture most of the functionality. Processes are executed in parallel. Both seq. Thread
and comb.

IF,FOR,CASE, Control statements Bounds must be known for loops at compile- The same
ASSIGNMENT time

PACKAGE Contains shared definitions. Constants, functions, procedures, types Header file (file.h)

LIBRARY Holds analyzed (’compiled’) codes Standard ieee library is practically always used Compiled object codes (file.o)

Arto Perttula 19.10.2015 132

Capabilities Verilog-95,
VHDL, SystemVerilog
• Verilog is another, but primitive HDL
– For some reason, more popular in US and Asia than Europe
• SystemVerilog is rather new language which adds many handy features for verification

SystemVerilog

( )
VHDL

Verilog-95

133
EXTRA SLIDES ON VHDL

Arto Perttula 19.10.2015 134

Recap: Register Transfer Level (RTL)

• Circuit is described in terms of how data moves through the system

• In the register-transfer level you describe how information flows between
registers in the system
• The combinational logic is described at a relatively high level, the placement
and operation of registers is specified quite precisely

• The behavior of the system over the is defined by registers

Arto Perttula 19.10.2015 135

 Variables: Example
• THIS IS WRONG! • THIS IS RIGHT (but variable is not very useful)
testi: process (clk, rst_n) testi: process (clk, rst_n)
<= temp_v or a_in(1); variable temp_v : std_logic;
variable temp_v : std_logic; begin -- process testi
begin -- process testi if rst_n = '0' then
if rst_n = '0' then c_out <= '0';
c_out <= '0'; temp_r <= '0';
temp_v := '0'; -- naughty habit
elsif clk'event and clk = '1' then
elsif clk'event and clk = '1' then temp_v := temp_r and a_in(0);
temp_v := temp_v and a_in(0); c_out <= temp_v or a_in(1);
c_out temp_r <= temp_v;
end if; end if;

end process testi; end process testi;

Variable is read before it is written inside the
elsif brach, and hence it must retain the old temp_v temp_r
value. It is not a good custom to infer registers a_in(0)
with variables (although possible)

Fig. The circuit we are trying to create: a_in(1) c_out

136
Signal Drivers
• Every signal has at least one driver, if it is not disconnected
• Signal assignment changes driver
• A conceptual circuit that is created for every signal driver
• Example of driver:
signal ex: positive;
...
ex <= 3 AFTER 5 ns, 2 AFTER 10 ns,
4 AFTER 15 ns, 0 AFTER 20 ns;

ex

Arto Perttula 19.10.2015 137

Signal Drivers
• Signal ”ex” as a function of time
ex

Arto Perttula 19.10.2015 138

Shift…
• For bit_vectors: operators: sla, sra, sll, srl…
• For (un)signed: functions shift_left() and shift_right()
• For std_logic_vector: no operators nor built-in functions, you should use slicing
• variable A: bit_vector :=”101101”;
– A sll 2 -- “110100”, filled with zeros
– A sla 2 -- “110111”, filled with LSB!
• sla is rather strange operator in VHDL

– A srl 2 -- “001011”, filled with zeros

– A sra 2 -- “111011”, filled with MSB

grey color denotes

– A rol 2 -- “110110”
– A ror 2 -- “011011”
inserted bits
Arto Perttula 19.10.2015 139
Configurations
• Links entity declaration and architecture body together
– Apply to structural description (one that instantiates components)
• Concept of default configuration is a bit messy in VHDL ’87
– Last architecture analyzed links to entity?
• Can be used to change simulation behaviour without re-analyzing the VHDL
source
• Complex configuration declaration are ignored in synthesis
• Some entities can have, e.g., gate level architecture and behavioral
architecture
• Are always optional

Arto Perttula 19.10.2015 140

Configuration Example
ARCHITECTURE configurable OF multiplexer IS
COMPONENT n2
PORT (
a: IN std_logic; CONFIGURATION
b: IN std_logic;
y: std_logic is in its own section
); in VHDL file, not
END COMPONENT;
SIGNAL sbar, asel, bsel : std_logic; within entities or
BEGIN architectures.
U1: n2 PORT MAP (a => s, b => s, y => sbar);
U2: n2 PORT MAP (a => x, b => sbar, y => asel);
END ARCHITECTURE configurable; Component
Mapping of ”n2” used
component n2
Use entity
nand2_t with
CONFIGURATION example_cfg OF multiplexer IS architecture
FOR configurable arch_2
FOR ALL : n2
USE ENTITY WORK.nand2_t (arch_2)
GENERIC MAP (cc_delay_g => 3);
END FOR;
END FOR;
END CONFIGURATION example_cfg; Generic for
the nand2_t
19.10.2015 141
Resolution Function
• Describes the resulting value when two or more different values are
driven onto a signal (more than one driver exists)
• Enables resolved data types
• Multi-value logic, implementation of three-state drivers

142
Type Conversion Between
Number-Related Data Types

Arto Perttula 19.10.2015 143

Attributes: high
• Returns the upper bound of array object or type
• General form:
T’HIGH and A’HIGH [(N)]
• Example:
...
VARIABLE c,b: BIT_VECTOR(5 DOWNTO 0);
...
FOR i IN c’HIGH DOWNTO C’LOW LOOP
c(i) := b(i); -- i goes from 5 to 0
END LOOP;
• T’HIGH is value kind of attribute and A’HIGH is function kind of attribute

Arto Perttula 19.10.2015 144

Attributes: right
• Returns the right-most bound of a given type or subtype
• General form:
T’RIGHT
• Example:
...
TYPE bit_array IS ARRAY (5 DOWNTO 1) OF BIT;
...
SIGNAL tmp_r : INTEGER;
...
tmp_r <= bit_array’RIGHT;
-- r is assigned with a value of 1

Arto Perttula 19.10.2015 145

Attributes: length
• Returns the length (number of elements) of an array
• General form:
A’LENGTH[(n)]
• Example:
...
TYPE bit_array IS ARRAY (31 TO 0) OF BIT;
...
SIGNAL len : INTEGER;
...
len <= bit_array’LENGTH;
-- LEN is assigned with a value of 32

Arto Perttula 19.10.2015 146

Attributes: range
• Returns the range of array object or array subtype
• General form:
A’RANGE and A’REVERSE_RANGE [(N)]
• Example:
...
SIGNAL c,b: std_logic_vector(5 DOWNTO 0);
...
FOR i IN c’RANGE LOOP
c(i) <= b(i); -- i goes from 5 to 0
END LOOP;
• NOTE:
– T’RANGE doesn’t exists

Arto Perttula 19.10.2015 147

Attribute Examples
• Signal d: std_logic_vector(7 downto 0)
– d’LOW = 0
– d’HIGH = 7
– d’LEFT = 7
– d’RIGHT = 0
– d’LENGTH = 8
– d’RANGE =(7 downto 0)
– d’REVERSE_RANGE=(0 to 7)
• Unfortunately, these cannot be applied to, e.g., a specific integer
– Only infromation type integer is obtainable, not about it’s instantiation
– integer’high, integer’low
– Not:
signal d : integer range 0 to 3;
d’high, d’low; -- does not work

Arto Perttula 19.10.2015 148

Attributes: active
• Returns value true if any transaction occured during the current delta, and otherwise
returns value false
• General form:
S’ACTIVE
• Example:
PROCESS(clk)
BEGIN
IF clk’ACTIVE AND clk=’1’ THEN
q <= d; AVOID
END IF;
END PROCESS; !
• NOTE:
Synthesis tools may not work correctly, use ’EVENT instead
Arto Perttula 19.10.2015 149
Attributes: stable
• Creates a boolean signal that is true whenever the reference signal has had no
events for the time specified by the optional time expression
• General form:
S’STABLE [(time)]
• Example:
PROCESS(clk)
BEGIN
IF NOT(clk’STABLE) AND clk= ’1’ THEN
q <= d;
END IF; AVOID
END PROCESS;
!
• NOTE:
Used to model flip-flop behaviour. Not so efficient as event.
Arto Perttula 19.10.2015 150
Type Attributes
TYPE v41 IS (‘X’, ’0’, ‘1' ,’Z' );
SUBTYPE v31 IS v41 RANGE ‘0' TO ‘Z’;
SUBTYPE v21 IS v41 RANGE ‘0‘ TO ‘1';
TYPE opcode IS (sta, lda, add, sub,
and, nop, jmp, jsr);

Source: Zainalabedin Navabi, VHDL: Modular

Design and Synthesis of Cores and Systems
Arto Perttula 19.10.2015 151
Block Statement
• Partitioning mechanism that allows design to group logically areas of design

ARCHITECTURE behav OF cpu IS

BEGIN
alu : BLOCK
BEGIN
statements
END BLOCK alu;

regs : BLOCK
BEGIN
statements
END BLOCK regs;
END behav;

Arto Perttula 19.10.2015 152

Guarded Block
• A block containing boolean expression which can enable and disable driver inside a block

ARCHITECTURE behav OF guarded_latch IS

BEGIN
latch : BLOCK(clk = ‘1’)
BEGIN
q <= GUARDED d AFTER 3ns;
qn <= GUARDED NOT(d) AFTER 5;
END BLOCK latch;
END guarded_latch Not
synthesizable
• Not synthesizable !

Arto Perttula 19.10.2015 153

Guarded Signal Assignment
• Like sequential signal assignment except guarded expression
• General form:
target <= [quarded] [transport] expr [after t_expr{,
expr after t_expr} ];
• Example, guarded signal assignment:
BLOCK (enable = ‘1’) AVOID
q <= GUARDED d AFTER 10 ns; !
END BLOCK
• When enable = ‘1’, d is asssigned to q after 10 ns, otherwise q and d
are disconnected
– I.e., changes in d are not reflected in q

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