Analog Integrated Circuits and Signal Processing, 14, 113–129 (1997)

°
c 1997 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

di/dt Noise in CMOS Integrated Circuits

PATRIK LARSSON
Bell Laboratories, Holmdel, NJ

Received October 22, 1996; Accepted November 18, 1996

Abstract. This is an overview paper presenting di/dt noise from a designer’s perspective. Analysis and circuit
design techniques are presented taking package parasitics into account. The main focus is on digital CMOS design,
but analysis and design suggestions can easily be extended to mixed-mode design.

Key Words: ground bounce, di/dt noise, simultaneous switching noise, low-noise design

I. Introduction in Fig. 1. The current paths in a CMOS circuit are il-

lustrated for an on-chip and an off-chip driver in Fig. 1
In the early 80s it was predicted that the transition from [2]. The definition of an on-chip driver is that it drives a
bipolar/NMOS to CMOS processing would lead to in- node A with capacitive loads connected to Vdd and Vss
creased di/dt noise levels in integrated circuits [46]. whereas an off-chip driver has loads to pwr and gnd as
However, it took a few processing generations before for node B. This is indicated by index i (internal) and
the impact of scaling caused significant problems. To- e (external) for the capacitors in Fig. 1. The MOS tran-
day, the improvements in packaging technology are sistors are modeled as switches with inherent resistors
barely sufficient to keep noise to tolerable levels. Even (not shown).
with exotic packages tailored for low noise, it is neces- Early research work [25, 42] was oriented towards
sary to estimate noise levels and design for low noise estimating L, using a simple model of di/dt or as-
before starting production of an IC. Circuit designers suming that di/dt was extracted from simulation. One
need to know the limits of the packages and how to simple model of di/dt is the triangle approximation
reduce noise levels. This paper covers the basics of [25, 46, 48]. It is assumed that the current has a trian-
di/dt noise including estimation, modeling, low-noise gular shape as in Fig. 2, with peak I p and duration t f ,
design and the impact of scaling. the fall time of the discharged node. [48] introduced
The paper starts by introducing circuit models and the variable T to denote the amount of time required
noise estimates. This theory is later used to derive for the current to reach its peak value. di/dt noise
noise reduction techniques and safe design. The future levels are smallest when T = t f /2, since this value
is predicted by scaling theory. minimizes the steepness of both the rising and falling

II. Modeling

A. Analytic First Order Model

The starting point when it comes to studying di/dt

noise and designing proper circuits is noise estimation.
The most important parameter to estimate is the peak
noise, which can be derived using the standard expres-
sion for the voltage across an inductor, expressed as:
di(t)
vn (t) = L · (1)
dt
where L is the effective inductance in the current path Fig. 1. Current paths in a CMOS chip for an on-chip and an off-chip
and vn (t) is the noise appearing on Vss relative to gnd driver [2].
114 P. Larsson

peak noise occurs for t = T , we get [50]

T · vnmax
Ip = = i out (T )
L
β
= · (vin (T ) − Vt − vnmax )2 (4)
2
Solving for vnmax yields
T
vnmax = vin (T ) − Vt +
Lβ
" r #
Fig. 2. Triangle approximation of current. Lβ
· 1− 1 + 2(vin (T ) − Vt ) · (5)
T
edges. The triangle approximation gives the maximum [58] set vin (T ) = Vdd and T = tr , the rise time of vin ,
di/dt as I p /T and which is justified for output buffers, since their input
rise times are commonly much smaller than their output
Ip fall times.
vnmax = L · (2)
T
This is the peak noise that would show up on Vss in
C. Current Waveform
Fig. 1 when the output node, B, is switched from high
to low. Due to symmetry, the same noise would show
One objection to the triangle approximation in Fig. 2 is
up on Vdd when the output buffer is switched from low
that when deriving vn (t), we end up with the waveform
to high.
in Fig. 3, which is never observed in measurements or
When internal circuits are switching, the current
simulations. To alleviate this, we use eqn. (3) to derive
paths in Fig. 1 show that Vss and Vdd will simulta-
di/dt and assume that the noise is a ramp [58, 68].
neously have symmetric noise (assuming equal induc-
From eqn. (3), we get
tance in the Vdd and Vss supply) such that Vddmin =
µ ¶
pwr − vnmax and Vssmax = gnd + vnmax . di out (t) dvin dvn
= β · (vin (t) − Vt − vn (t)) · −
dt dt dt
(6)
B. Bounce Causing Negative Feedback
There is no noise until vin reaches Vt , so assuming vn (t)
The formulation in eqn. (2) is not valid for large noise is a linear ramp leads to
levels since it predicts that the noise may in fact be
dvn vnmax
larger than the supply voltage, Vdd . The concept of = Vdd −Vt
(7)
negative feedback introduced in [48] gives an improved dt
Vdd
· tr
model by writing the current as a function of the noise
voltage. As Vss increases due to a falling transition
at the output, ground bounce tends to reduce the cur-
rent through the output N transistor. Assuming this N
transistor is saturated, we get

β
i out (t) = · (vin (t) − Vt − vn (t))2 (3)
2
where vin is the gate voltage of the output driver, Vt is
the threshold voltage of an MOS transistor and β is the
transconductance parameter. By combining eqn. (1)
with the triangle current approximation, it is possible
to express I p as a function of vnmax . Assuming that the Fig. 3. Unrealistic noise waveform due to triangle approximation.