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AIM: - Write A VHDL Code For 4 Bit Ripple Carry Adder Using Loop Statement. Code

The document describes a VHDL code for a 4-bit ripple carry adder. It includes the code for the adder entity using a loop statement to perform the addition. It also includes a test bench that applies various input patterns and checks the output. The RTL diagram and simulation waveform are shown. The synthesis summary shows the resource utilization is very low.

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Prashant Pathak
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586 views

AIM: - Write A VHDL Code For 4 Bit Ripple Carry Adder Using Loop Statement. Code

The document describes a VHDL code for a 4-bit ripple carry adder. It includes the code for the adder entity using a loop statement to perform the addition. It also includes a test bench that applies various input patterns and checks the output. The RTL diagram and simulation waveform are shown. The synthesis summary shows the resource utilization is very low.

Uploaded by

Prashant Pathak
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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PRACTICAL – 4

AIM: -Write a VHDL code for 4 bit ripple carry adder using loop statement.
CODE:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rippleadd4bit is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end rippleadd4bit;

architecture Behavioral of rippleadd4bit is

begin
process (a,b,cin)
variable c :STD_LOGIC_VECTOR (4 downto 0);
variable i: integer:=0;
begin
c(0):=cin;
for i in 0 to 3 loop
s(i)<=a(i) xor b(i) xor c(i);
c(i+1):= (a(i)and b(i))or(b(i)and c(i))or(c(i)and a(i));
end loop;
cout<= c(4);
end process;
end Behavioral;

TEST BENCH:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_ripplecarry is
end tb_ripplecarry;

architecture Behavioral of tb_ripplecarry is


COMPONENT rippleadd4bit is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);


b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
END COMPONENT rippleadd4bit;
signal a : std_logic_vector(3 downto 0);
signal b : std_logic_vector(3 downto 0);
signal cin : std_logic := '0';
signal S : std_logic_vector(3 downto 0);
signal cout : std_logic;

begin

u:rippleadd4bit PORT MAP (a,b,cin,s,cout);

process
begin

cin<= '0';
A <= "0110";
B <= "1100";

wait for 50 ns;


A <= "0110";
B <= "0111";

wait for 50 ns;


A <= "1111";
B <= "1100";

wait for 50 ns;


cin<='1';

A <= "0110";
B <= "1100";

wait for 50 ns;


A <= "0110";
B <= "0111";

wait for 50 ns;


A <= "1111";
B <= "1100";

wait for 50 ns;


A <= "1111";
B <= "1111";

wait for 50 ns;

end process;

end Behavioral;
RTL DIAGRAM:-

SIMULATION WAVEFORM :-
SYNTHESIS SUMMARY:-
+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 4 | 0 | 17600 | 0.02 |
| LUT as Logic | 4 | 0 | 17600 | 0.02 |
| Bonded IOB | 14 | 0 | 100 | 14.00 |
+-------------------------+------+-------+-----------+-------+

 Maximum Combinational path Delay : 5.968 ns

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