CMOS INTEGRATED CIRCUIT DESIGN TECHNIQUES

University of Ioannina
University of Ioannina

Boundary
Scan Testing
(JTAG –– ΙΕΕΕ 
(JTAG  ΙΕΕΕ 1149.1 std.)
1149.1 std.)

Dept. of Computer Science and Engineering

Y. Tsiatouhas

CMOS Integrated Circuit Design Techniques

Overview
1. Basic JTAG architecture

2. The Test Access Port (TAP)

3. JTAG registers

4. State diagram –
State diagram – Operating modes

5. Instruction set

6. External and internal testing operations
VLSI Systems
and Computer Architecture Lab

Boundary Scan (JTAG 1149.1) 2

1
 Typical PCB Testing

Probe Chip Under
Test

Probe

PCB Under Test

True
Response
Drivers

Expected
Response Tester

Test Patterns
Boundary Scan (JTAG 1149.1) 3

Basic JTAG
Basic JTAG Architecture (Ι)
Architecture (Ι)
(IEEE 1149.1 std)
The JTAG 1149.1 Boundary Scan std.
Boundary supports PCB testing procedures according
Register
to a commonly acceptable (standard) test
mechanism.
User or ID It consists of:
Logic

Register
• A Test Access Port ‐ TAP with 4 or 5
Bypass pins.
Register • A set of registers (an instruction
Instruction
register (IR), a bypass register (BR)
Register and data registers (DR).
(DR)
. . .
• A TAP Controller which is a finite state
Test Access Port
Controller
TDI TDO machine (FSM) with 16 states.
. . .
TCK
TMS TAP Controller TRST

Boundary Scan (JTAG 1149.1) 4

2
 Basic JTAG
Basic JTAG Architecture (Ι
Architecture (ΙII)

In the normal mode of operation the JTAG circuitry is

transparent to the chip under test and the PCB
system where this chip is embedded.
embedded


Logic

Two test modes of operation exist:

• Internal Testing where the internal logic of the
chip is tested.
• External Testing where the interconnections
. . .
among the chips are tested.
TDI TDO
. . .
TCK
TMS TAP Controller TRST

Boundary Scan (JTAG 1149.1) 5

Test Access Port 
Test Access Port –– TAP (I)
PCB
TDO TRST TDO TRST
TAP Cntrl

TAP Cntrl
. . .

. . .
. . .

. . .

Logic Logic
TDO
TDI TCK TMS TDI TCK TMS
TCK
TRST
TAP

TDO TRST TDO TRST

TMS
TDI
TAP Cntrl

TAP Cntrl
. . .

. . .
. . .

. . .

Logic Logic

TDI TCK TMS TDI TCK TMS

Boundary Scan (JTAG 1149.1) 6

3
 Test Access Port 
Test Access Port –– TAP (II)
• TCK (Test Clock): This is the test clock signal, which synchronizes the test
procedure independently of the system clock. Under the control of this
signal test data are shifted between the TAP registers.
• TDI (Test Data Input): Serial test data input. New data are scanned
scanned‐in
in at
each positive edge of the TCK clock signal. When not in use must remain at
logic High.
• TDO (Test Data Output): Serial test data output. Data are scanned‐out at the
negative edge of the TCK clock signal.
• TMS (Test Mode Select): The sequence of values at this input is translated
by the TAP Controller and is used to control the test procedure. When not in
use must remain at logic High.
• TRST (Test Reset): This is an optional signal, which is used for the
asynchronous initialization of the test logic independently of the clock
signal TCK.

Boundary Scan (JTAG 1149.1) 7

Registers
Chip The JTAG protocol
Scan Register
provides the ability to
Logic support a large number of
BSR

. . . . . .
BSR

PI PO user defined
d fi d registers.
it
However, the presence of
Decoders three registers is
mandatory :
MUX‐1

User Registers

Dev. ID Register • Bypass Register (BR) 
Shift_DR
Clock_DR Bypass (Καταχωρητής Παράκαμψης)
Update_DR • Instruction Register (IR) 
Run_Test MUX‐2
(Καταχωρητής Εντολών
Καταχωρητής Εντολών)
0 TDO
Decode Logic • Boundary Scan Register 
FF
TDI
IR Register
1 (BSR) (Καταχωρητής 
Shift_IR TCK
Περιφερειακής Σάρωσης)
TCK Clock_IR
TMS TAP Update_IR
Controller Reset Select
TRST Shift

Boundary Scan (JTAG 1149.1) 8

4
 Instruction Register 
Instruction Register –– IR
(Καταχωρητής Εντολών)
Εντολών)
• The Instruction Register – IR (Καταχωρητής Εντολών) is a serial / parallel input and
output register. Each stage of the register consists of a pair of a flip‐flop and a
latch. The flip‐flop feeds the corresponding latch. The latch holds the current
instruction when the IR is updated with new data (instructions).
(instructions) The size of
the register is at least two bits.
TDO or
Next Cell
IR Cell
MUX Parallel 
Data 0 Shift Reg. FF Latch FF Output
D Q D Q Parallel Outputs
1
CLK CLK
Latch  IR
Flip‐Flops
CLR CLR
. . .
TDI or TDI . . . TDO
Previous  ShiftIR ClockIR UpdateIR n n‐1 1 0
Shift Reg. 
(CaptureIR)
Cell Flip‐Flops

n1 Data
Boundary Scan (JTAG 1149.1) 9

Boundary Scan Register –– BSR
Boundary Scan Register 
(Καταχωρητής Περιφερειακής Σάρωσης)
Περιφερειακής Σάρωσης)
• The Boundary Scan Register – BSR (Καταχωρητής Περιφερειακής Σάρωσης) is placed
at the chip periphery, in‐between the input/output pads and the internal
logic. It consists of the Boundary Scan Cells – BSC (Κύτταρα Περιφερειακής Σάρωσης)
and supports both the testing of the internal logic of the chip as well as the
interconnects of the chip with other chips.

To next BSC
Data or TDO ShiftOut
Input Pin BSC MUX
Internal
0
Logic
Internal MUX
Logic 0 Shift Reg. FF Latch FF 1 Output Pin
D Q D Q

1 CAP UPD
CLK CLK

CLR CLR

From previous BSC (CaptureDR)
or TDI
ShiftIn ShiftDR ClockDR UpdateDR Mode (Test/Normal)

Boundary Scan (JTAG 1149.1) 10

5
 Bypass Register –
Bypass Register – BR
• The Bypass Register – BR (Καταχωρητής Παράκαμψης) is an one bit register
consisting of a single Flip‐Flop*. It permits the signal at the TDI input to
bypass the BSR register and directly feed the TDO output.

AND
Flip‐‐Flop
Flip
TDI TDOBR
D Q
CaptureDR To TDO output 
CLK through MUX‐1 and MUX‐2
CLR

BR

ClockDR
(CaptureDR)

* In practice the BR is implemented as a single boundary scan cell !

Boundary Scan (JTAG 1149.1) 11

TAP Controller  State Diagram

The ΤΑΡ controller is a Finite

State Machine (FSM) with 16
states. The state transition takes
1
place at the positive edge of the
TCK clock signal.

At the state diagram beside, the

arrows between the states are
marked with 0 or 1, which
correspond to the logic level that
the TMS signal must have before
the
h positive
i i edge
d off the
h clock
l k
signal TCK in order to activate
the corresponding state
transition.

Boundary Scan (JTAG 1149.1) 12

6
 Modes of Operation

Two basic modes of operation exist for the JTAG 1149.1 std. and each mode
supports specific instructions:
• Non‐Invasive Mode (Απρόσκοπτος Τρόπος): The ΤΑΡ controller and the
pertinent port operate asynchronously and independently with
respect to the system under test. In this mode, the ΤΑΡ port can be
exploited without disturbing the operation of the system.
• Pin Permission Mode (Τρόπος Επίτρεψης Ακροδέκτη): In this mode, the
internal logic of the circuit under test is disconnected from the
input/output pins. Consequently, only testing operations can be
performed.

Boundary Scan (JTAG 1149.1) 13

Instruction Set 
Instruction Set –– Ι
(Non‐‐Invasive)
(Non
• BYPASS: This instruction places the 1‐bit bypass register between the TDI and
TDO pins. The BYPASS instruction is mandatory for the protocol. The all ones
state in the instruction register
g must correspond
p to this instruction.

• IDCODE: This instruction places a 32‐bit register between the TDI and TDO
pins. The register is loaded in parallel by the hardware with the code ID of the
chip.

• USERCODE: Once again, this instruction places the previous 32‐bit register
between the TDI and TDO pins. This time the register is not loaded with the
code
d ID off the
th chip
hi but
b t with
ith a user defined
d fi d code.
d This
Thi instruction
i t ti is i related
l t d to
t
programmable devices (like FPGAs).

Boundary Scan (JTAG 1149.1) 14

7
 Instruction Set 
Instruction Set –– ΙI
(Non‐‐Invasive)
(Non

• SAMPLE/PRELOAD instruction: This instruction places the boundary scan

register (BSR) between the TDI and TDO pins. This instruction is mandatory
for the protocol.
protocol The Sample/Preload instruction does not disturb the normal
mode of operation since the Mode signal of the second multiplexer in the
boundary scan cells is at logic “0” (normal mode). The instruction activates
two operations:
– The SAMPLE operation is accomplished at the CAPTURE‐DR state of the TAP
controller where the CAP Flip‐Flops capture the data at their inputs. Thus, the BSR
register holds a snapshot of the activity at the chip’s I/Os. Then, the sampled data
can be scanned‐out for observation.
– The PRELOAD operation is accomplished during the scan scan‐out
out activity,
activity where in
parallel new data are scanned‐in. Thus, the data at the ShiftIn (SI) inputs are
captured by the CAP Flip‐Flops and subsequently feed the UPD Flip‐Flops when
the TAP controller is at the UPDATE‐DR state.

Boundary Scan (JTAG 1149.1) 15

Instruction Set 
Instruction Set –– ΙII
(Non‐‐Invasive)
(Non
. .
. SAMPLE phase – CaptureDR . Chip
Input . Output .
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR “0” DR DR DR “0”
“0” “0”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 16

8
 Instruction Set 
Instruction Set –– ΙV
(Non‐‐Invasive)
(Non
. .
. PRELOAD – SHIFT phase – ShiftDR . Chip
Input . Output .
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR “0” DR DR DR “0”
“1” “1”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 17

Instruction Set 
Instruction Set –– V
(Non‐‐Invasive)
(Non
. .
. End of PRELOAD – UpdateDR . Chip
Input . Secure/Don’t Care Output .
Values
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR “0” DR DR DR “0”
“0” “0”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 18

9
 Instruction Set 
Instruction Set –– VΙ
(Pin‐‐Permission)
(Pin
• The EXTEST instruction: This instruction places the boundary scan register
between the TDI and TDO pins. The instruction is mandatory and the all zero
state at the instruction register must correspond to it.

At the CAPTURE‐DR state, the logic values at the input pads of the chip are
captured in the CAP Flip‐Flops of the BSC cells. In addition, the output pads
are driven by the UPD Flip‐Flops since the Mode signal is “1”. With this
instruction the input pads are sampled and the output pads are driven.
Consequently, at the shift operations on the BSR register, the state of the
input pads is read while new values are set at the output pads of the chip.

Boundary Scan (JTAG 1149.1) 19

Instruction Set 
Instruction Set –– VI
VIΙΙ
(Pin‐‐Permission)
(Pin
. Test Application
.
. 1st phase of EXTEST . Chip
Input . Secure/Don’t Care Output .
Values
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR “1” DR DR DR “1”

. .
. .
. .
Boundary Scan (JTAG 1149.1) 20

10
 Instruction Set 
Instruction Set –– VΙII
(Pin‐‐Permission)
(Pin
. Test Response Capture
.
. 2nd phase of EXTEST – CaptureDR . Chip
Input . Don’t Care Output .
Values
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR DR DR DR
“0” “0”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 21

Instruction Set 
Instruction Set –– ΙX
(Pin‐‐Permission)
(Pin
. Test Data Shift
.
. 3rd phase of EXTEST– ShiftDR . Chip
Input . Output .
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR DR DR DR
“1” “1”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 22

11
 Instruction Set 
Instruction Set –– X
(Non‐‐Invasive)
(Non
. Update BSR with Test Data .
. End of EXTEST – UpdateDR . Chip
Input . Secure/Don’t Care Output .
Values
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR DR DR DR
“0” “0”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 23

Instruction Set 
Instruction Set –– XI
(Pin‐‐Permission)
(Pin
• The RUNBIST instruction: This instruction activates a user defined register
which may be one of the existing registers in the protocol. The target is to
permit the use of embedded BIST techniques. The BIST procedures start when
the ΤΑΡ controller is at the RUN‐TEST‐IDLE state.

• The INTEST instruction: This instruction places the boundary scan register
between the TDI and TDO pins. It sets the inputs of the internal logic under
the control of the corresponding UPD Flip‐Flops of the BSR. In addition, the
BSR cells at the outputs of the internal logic sample the corresponding
responses at the CAPTURE‐DR state. Consequently, at the UPDATE‐DR state a
test pattern is applied while at the CAPTURE
CAPTURE‐DR
DR state the response of the
logic to this pattern is sampled. Next, the response is scanned‐out and
concurrently a new test pattern is scanned‐in.

Boundary Scan (JTAG 1149.1) 24

12
 Instruction Set 
Instruction Set –– XΙI
(Pin‐‐Permission)
(Pin
. Test Application
.
. 1st phase of INTEST . Chip
Input . Output . Secure/Don’t Care
BSC BSC Values
l
SO SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR “1” DR DR DR “1”

. .
. .
. .
Boundary Scan (JTAG 1149.1) 25

Instruction Set 
Instruction Set –– XI
XIΙΙI
(Pin‐‐Permission)
(Pin
. Test Response Capture
.
. 2nd phase of INTEST . Chip
Input . Don’t Care Output .
Values
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR DR DR DR
“0” “0”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 26

13
 Instruction Set 
Instruction Set –– XIV
(Pin‐‐Permission)
(Pin
. Test Data Shift .
. 3rd phase of INTEST – ShiftDR . Chip
Input . Output .
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR DR DR DR
“1” “1”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 27

Instruction Set 
Instruction Set –– XV
(Non‐‐Invasive)
(Non
. Update BSR with Test Data .
. End of INTEST – UpdateDR . Chip
Input . Output . Secure/Don’t Care
Values
BSC SO BSC SO
PI
0 0 PO

0 1 0 1

1
D Q
CAP
D Q
UPD
Logic 1
D
CAP
Q D Q
UPD
CLK CLK CLK CLK

SI Shift Clock Update Mode SI Shift Clock Update Mode

DR DR DR DR DR DR
“0” “0”
. .
. .
. .
Boundary Scan (JTAG 1149.1) 28

14
 Instruction Set 
Instruction Set –– XVI
(Pin‐‐Permission)
(Pin
• The HIGHZ instruction: This instruction places the bypass register between
the TDI and TDO pins. In addition, sets the output pads in the “high Z”
condition
co d t o at tthee U
UPDATE‐IR state
state. Itt iss eexploited
p o ted for
o tthee test
testingg o
of cchips
ps tthat
at
are not compliant with the JTAG protocol.

• The CLΑMP instruction: This instruction places the bypass register between
the TDI and TDO pins. In addition, sets the output pads under the control of
the BSR register, which has been earlier fed with proper values by exploiting a
sequence of SAMPLE/PRELOAD instructions. Consequently, the output pads of
the chip retain specific values during the testing procedures that are applied
to other
h chips
hi where
h these
h outputs do
d not participate.
i i

Boundary Scan (JTAG 1149.1) 29

Instruction Register Update 
Instruction Register Update –– Ι

Initialization at the TEST‐LOGIC‐

RESET state by exploiting the
TRST signal.
1
Proper use of the TMS and TCK
signals in order to activate the
CAPTURE‐IR state and
subsequently the SHIFT‐IR state.

At the CAPTURE‐IR state the IR

register is placed between the
TDI andd TDO pins.
i

At the SHIFT‐IR state the TDO pin

is activated.

Boundary Scan (JTAG 1149.1) 30

15
 Instruction Register Update 
Instruction Register Update –– ΙI 

Boundary Scan (JTAG 1149.1) 31

Instruction Register Update 
Instruction Register Update –– ΙII 
PCB
TDO TRST TDO TRST

ΙR ΙR
TAP Cntrl

TAP Cntrl
. . .

. . .
. . .

. . .

Logic Logic
TDO
TDI TCK TMS TDI TCK TMS
TCK
TRST
TAP

TDO TRST TDO TRST

TMS
TDI
ΙR ΙR
TAP Cntrl

TAP Cntrl
. . .

. . .
. . .

. . .

Logic Logic

TDI TCK TMS TDI TCK TMS

Boundary Scan (JTAG 1149.1) 32

16
Data Register Activation

The update of the IR register, at

the UPDATE‐IR state, will result
to the connection of the proper
1
data register between the TDI
and TDO pins when the ΤΑΡ
controller will be at the
CAPTURE‐DR state.

Boundary Scan (JTAG 1149.1) 33

Data Register Update –– I
Data Register Update 

At SHIFT‐DR state the TDO is

activated and new test data are
1
scanned‐in/out to the selected
register.

Boundary Scan (JTAG 1149.1) 34

17
 Data Register Update –– II
Data Register Update 

Boundary Scan (JTAG 1149.1) 35

Data Register Update –– III
Data Register Update 
(& Bypass Operation)
& Bypass Operation)
PCB
TDO TRST TDO TRST

BR
TAP Cntrl

TAP Cntrl
. . .

. . .
. . .

. . .

CUT
Logic Logic
TDO
TDI TCK TMS TDI TCK TMS
TCK
TRST
TAP

BSR
TDO TRST TDO TRST
TMS
TDI
BR BR
TAP Cntrl

TAP Cntrl
. . .

. . .
. . .

. . .

Logic Logic

TDI TCK TMS TDI TCK TMS

Boundary Scan (JTAG 1149.1) 36

18
 Data Register Activation

At the UPDATE‐DR state the data

register is updated.

1
Possibly another data shift phase
will be initiated next.

Boundary Scan (JTAG 1149.1) 37

Basic Testing Procedure 
Basic Testing Procedure –– Ι
(External or Internal Testing)
1 TEST‐LOGIG‐RESET

‐ Invasive Mode
Invasive Mode ‐
Load IR with the instruction
2 The selected DR 
SAMPLE/PRELOAD is placed between TDI‐TDO

Shift data to the selected  PRELOAD phase
3
DR (e.g. BSR)

‐ Pin‐Permission Mode ‐
Load IR with the instruction
Load IR with the instruction The selected DR
The selected DR 
4 is placed between TDI‐TDO.
EXTEST ή INTEST
Test data application.

5 Test response Capture

Boundary Scan (JTAG 1149.1) 38

19
Basic Testing Procedure 
Basic Testing Procedure –– ΙI
(External or Internal Testing)

Scan‐out the test response
6
Scan‐in new test data

7 New Test data application

8 YES
More test data? 5

NO

9 Test response capture

Boundary Scan (JTAG 1149.1) 39

Basic Testing Procedure 
Basic Testing Procedure –– ΙII
(External or Internal Testing)

Scan‐out the test response
10
Scan‐in secure data

11 Secure data application 

12 TEST‐LOGIG‐RESET

Boundary Scan (JTAG 1149.1) 40

20
 IEEE P1687 –– Internal 
IEEE P1687  Internal JTAG
JTAG (IJTAG)
IJTAG)

IEEE P1687 std.

Also referred to as IJTAG (Internal JTAG), the IEEE P1687 working group intends to develop a methodology for access
to embedded test and debug features (but not the features themselves) via the IEEE 1149.1 Test Access Port (TAP)
and additional signals that may be required.
required The IEEE 1149.1
1149 1 standard specifies circuits to be embedded within a
Integrated Circuit to support board test, namely the Test Access Port (TAP), TAP Controller, and a number of internal
registers. In practice, the TAP and TAP controller are being used for other functions well beyond boundary scan in an
ad‐hoc manner across the industry to access a wide variety of internal chip test and debug features. The purpose of
the IJTAG initiative is to provide an extension to the IEEE 1149.1 standard specifically aimed at using the TAP to
manage the configuration, operation and collection of data from embedded test and debug circuitry. There exists the
widespread use of embedded instrumentation (such as BIST Engines, Complex I/O Characterization and Calibration,
Embedded Timing Instrumentation, etc.) each of which is accessed and managed by a variety of external
instrumentation using a variety of mechanisms and protocols. Therefore, there exists a need for a standardization of
these protocols in order to ensure an efficient and orderly methodology for the preparation of tests and the access
and control of these embedded instruments. The elements of the methodology include a description language for
the characteristics of the features and for communication with the features, and requirements for interfacing to the
features.

Source: ΙΕΕΕ

Boundary Scan (JTAG 1149.1) 41

References
• “The Boundary‐Scan Handbook,” K. Parker, Kluwer Academic Publishers, 1992.
• “Principles of Testing Electronics Systems”, S. Mourad and Y. Zorian, John Wiley & Sons,
2000.
• “Essentials of Electronic Testing: for Digital, Memory and Mixed‐Signal VLSI Circuits”, M.
Bushnell and V. Agrawal, Kluwer Academic Publishers, 2000.
• “System‐on‐Chip Test Architectures”, L‐T Wang, C. Stroud and N. Touba, Morgan‐
Kaufmann, 2008.

Boundary Scan (JTAG 1149.1) 42

21