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11-Memory management-TLB PDF

The document discusses memory management and TLB (translation lookaside buffer) caching in operating systems. It provides 3 key points: 1. TLB caches virtual to physical address translations to speed up the memory management process. 2. On x86 architectures, the entire TLB must be flushed on every context switch because entries do not identify the process context. 3. Using page tags allows TLB entries to be associated with processes, reducing the performance penalty of context switches.

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138 views

11-Memory management-TLB PDF

The document discusses memory management and TLB (translation lookaside buffer) caching in operating systems. It provides 3 key points: 1. TLB caches virtual to physical address translations to speed up the memory management process. 2. On x86 architectures, the entire TLB must be flushed on every context switch because entries do not identify the process context. 3. Using page tags allows TLB entries to be associated with processes, reducing the performance penalty of context switches.

Uploaded by

anotherstupidregistr
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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CS 550 Operating Systems

Spring 2019

Memory Management: TLB

1
Translation look-aside Buffer
• TLB caches virtual-to-physical address translation
• TLB is a small cache that speeds up the translation
of virtual addresses to the physical addresses
• It is not a Data Cache or Instruction Cache. Those
are separate
• TLB simply caches translations from virtual page
number to physical page number so the MMU
don’t have to access page-table in the memory too
often.

2
TLBs – Translation Lookaside Buffers

⬥TLB is a small cache that speeds up the translation of virtual addresses to


physical addresses.
⬥TLB is part of the MMU hardware (comes with CPU)
⬥It is not a Data Cache or Instruction Cache. Those are separate.
⬥TLB simply caches translations from virtual page number to physical page
number so that the MMU don’t have to access page-table in memory too
often.
⬥On x86 architecture, TLB has to be “flushed” upon every context switch 3
because there is no field in TLB to identify the process context.
Cold Start Penalty
• Cost of repopulating the TLB (and other caches) upon a
context switch.

• Immediately after a context switch, all (or many) of TLB


entries are invalidated.
• On some x86 processors, TLB has to be “flushed” upon every
context switch because there is no field in TLB to identify the
process context.
• Every memory access by the newly scheduled process may
results in a TLB miss.

• MMU must then walk the page-table in main memory to


repopulate the missing TLB entry, which takes longer than a
cache hit.
4
Tagged TLB
• A“tag” in each TLB entry identifies the process/thread
context to which the TLB entry belongs

• Thus TLB entries for more than one execution context


can be stored simultaneously in the TLB.
• TLB lookup hardware matches the tag in addition to
the virtual page number.

• With tags, context switch no longer requires a


complete TLB flush.
• Reduces cold-start penalty.
5
Impact of Page Size on Page tables
Small page size
• Advantages
• less internal fragmentation
• page-in/page-out less expensive

• Disadvantages
• process that needs more pages has larger page
table

6
TLB Coverage
• Max amount of memory mapped by TLB
• Max mount of memory that can be accessed without TLB misses

• TLB Coverage = N x P bytes


• N = Number of entries in TLB
• P = Page size in bytes
• N is fixed by hardware constraints
• So, to increase TLB Coverage, we must increase P.

• Consider these extreme examples


• Suppose P = 1 byte
• TLB Coverage = N bytes only
• Suppose P = 2^64 bytes (on a 64-bit ISA)
• TLB Coverage = N x2^64bytes
• TLB can perform translations for N processes without any TLB misses!

• Of course, both examples above are impractical and meant to illustrate the tradeoffs.

• But what if P is something reasonable, but greater than than the standard 4KB?

• This brings us next to superpages.

7
Superpages
⬥Memory pages of larger sizes than standard pages
⬥supported by most modern CPUs

⬥Superpage size = power of 2 x the base page size

⬥Only one TLB entry per superpage


⬥But multiple (identical) page-table entries, one per base page

⬥Constraints:
⬥contiguous (physically and virtually)
⬥aligned (physically and virtually)
⬥uniform protection attributes
⬥one reference bit, one dirty bit
A superpage TLB
virtual memory

base page entry (size=1)

virtual superpage entry (size=4) physical


address address

TLB

physical memory

9
References
• Chapter 3: Modern Operating Systems, Andrew S. Tanenbaum

• X86 architecture
• http://en.wikipedia.org/wiki/X86

• Memory segment
• http://en.wikipedia.org/wiki/Memory_segment

• Memory model
• http://en.wikipedia.org/wiki/Memory_model

• IA-32 Intel Architecture Software Developer’s Manual, Volume 1: Basic


Architecture

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