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4 Bit Ring Counter Program

This document contains code for a 4-bit ring counter, a test bench to test the ring counter, code for a BCD (binary coded decimal) counter, and a brief description of an SR flip flop. The 4-bit ring counter code uses a always block and blocking assignments to shift the bits left on each clock cycle and feedback the last bit, resetting the counter to 0001 on reset. The test bench generates a clock signal, applies a reset, and monitors the output over time. The BCD counter code counts from 0 to 9 in decimal before resetting to 0.

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Ramanathan
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158 views5 pages

4 Bit Ring Counter Program

This document contains code for a 4-bit ring counter, a test bench to test the ring counter, code for a BCD (binary coded decimal) counter, and a brief description of an SR flip flop. The 4-bit ring counter code uses a always block and blocking assignments to shift the bits left on each clock cycle and feedback the last bit, resetting the counter to 0001 on reset. The test bench generates a clock signal, applies a reset, and monitors the output over time. The BCD counter code counts from 0 to 9 in decimal before resetting to 0.

Uploaded by

Ramanathan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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4 bit ring counter

Program:
module four_bit_ring_counter (

input clock,

input reset,

output [3:0] q

);

reg[3:0] a;

always @(posedge clock)

if (reset)

a = 4'b0001;

else

begin

a <= a<<1; // Notice the blocking assignment

a[0]<=a[3];

end

assign q = a;

endmodule

Test bench:
`timescale 1ns / 1ps

module stimulus;

reg clock;

reg reset;

wire[3:0] q;

four_bit_ring_counter r1 (
.clock(clock),

.reset(reset),

.q(q)

);

always #10 clock = ~clock;

initial begin

clock = 0;

reset = 0;

#5 reset = 1;

#20 reset = 0;

#500 $finish;

end

initial begin

$monitor($time, " clock=%1b,reset=%1b,q=%4b",clock,reset,q);

end

endmodule
BCD counter

Program:
Program:
module BCD_Counter ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input clk ;

wire clk ;

input reset ;

wire reset ;

initial dout = 0 ;

always @ (posedge (clk)) begin

if (reset)

dout <= 0;
else if (dout<=9) begin

dout <= dout + 1;

end else if (dout==9) begin

dout <= 0;

end

end

endmodule

SR flip flop:

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