EX.

NO:1 Design and Simulation of Combinational Circuits

[Link](a) Design and Simulation of Full Adder

AIM:
To design and verify the Full Adder using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A full adder is a logical circuit that performs an addition operation on three one-bit
binary numbers. The full adder produces a sum of the three inputs and carry value.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:
module fa(s,co,a,b,ci);
output s,co;
input a,b,ci;
xor1 u1(s,a,b,ci);
and1 u2(n1,a,b);
and1 u3(n2,b,ci);
and1 u4(n3,a,ci);
or1 u5(co,n1,n2,n3);
endmodule

SIMULATION RESULTS:

1
 [Link](b) Design and Simulation of Full Subtractor

AIM:
To design and verify the Full Subtractor using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module fs(a, b, c, borrow, difference);

input a;
input b;
input c;
output borrow;
output different;
wire d,e,f;
xor(difference,a,b,c);
and(d,~a,b);
and(e,b,c);
and(f,~a,c);
or(borrow,d,e,f);
endmodule

SIMULATION RESULTS:

2
 [Link](c) Design and Simulation of Multiplexer

AIM:
To design and verify the Multiplexer using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A multiplexer or MUX is a device that allows digital information from several different
sources on different input lines to be routed onto a single line. A basic MUX has several input
lines, several data select lines or control signals and one output signal. The input that gets
selected to pass to the output is determined by the control signals.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module mux1(a,b,c,d,s1,s2,z);
input a,b,c,d,sel;
output z;
assign<=((~s1)&(~s2)&a)|((~s1)&(s2)&b)|((s1)&(~s2)&c)| ((s1)&(s2)&d);
endmodule

SIMULATION RESULTS:

3
 [Link](d) Design and Simulation of Demultiplexer

AIM:
To design and verify the Demultiplexer using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of
several digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to
select which output line to send the input. Ademultiplexer is also called a data distributor.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module Demultiplexer(in,s0,s1,s2,d0,d1,d2,d3,d4);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4;
assign d0=(in & ~s1 & ~s2 ),
d1=(in & ~s1 & s2 ),
d2=(in & s1 & ~s2),
d3=(in & s1 & s2 );
endmodule

SIMULATION RESULTS:

4
 [Link](e) Design and Simulation of Encoder

AIM:
To design and verify the Encoder using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another, for the purposes of standardization, speed or
compression.
PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module encoder83(o,i);
output [2:0]o;
input [7:0]i;
wire x,y,k,l,m;
or1 u1(x,i[5],i[4]);
or1 u2(y,i[7],i[6]);
or1 u3(o[2],x,y);
or1 u4(k,i[3],i[2]);
or1 u5(o[1],y,k);
or1 u6(l,i[7],i[5]);
or1 u7(m,i[3],i[1]);
or1 u8(o[0],l,m);
endmodule

5
SIMULATION RESULTS:

RESULT:

The basic combinational circuits was designed and simulated using Modelsim Software.

6
 [Link] Design and Simulation of Sequential Circuits

[Link](a) Design and Simulation of Flip Flop

AIM:
To design and verify the FlipFlop using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level “1”.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

SR FLIPFLOP:

module srff(q,q1,r,s,clk);
output q,q1;
input r,s,clk;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk)
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end

7
Endcase
end
endmodule

SIMULATION RESULTS:

JK FLIPFLOP:

module jk(q,q1,j,k,c);
output q,q1;
input j,k,c;
reg q,q1;
initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
begin
case({j,k})
{1'b0,1'b0}:begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=~q; q1=~q1; end
endcase
end
endmodule

SIMULATION RESULTS:

8
 [Link](b) Design and Simulation of Counter

AIM:
To design and verify the JK Synchronous and Asynchronous using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types.

 Asynchronous or ripple counters.

 Synchronous counters.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

SYNCHRONOUS UP/DOWN COUNTER:

module updown_counter(
input up_down, // if up_down is ‘1’ then it counts up , else if ‘0’ it counts down
input clk,
input clear,
output [7:0]count_out
);
reg [7:0]count;
assign count_out = count;
always@(posedge clk) begin
if(!clear)
count<=’b0;
else begin
if(up_down) // counting up
count<=count+1′b1;
else
count<=count-1′b1;
9
end
end
endmodule

SIMULATION RESULTS:

ASYNCHRONOUS UP/DOWN COUNTER:

module ripple_count(j,k,clock,reset,q,qb);
input j,k,clock,reset;
output wire [3:0]q,qb;

jkff JK1(j,k,clock,reset,q[0],qb[0]);
jkff JK2(j,k,q[0],reset,q[1],qb[1]);
jkff JK3(j,k,q[1],reset,q[2],qb[2]);
jkff JK4(j,k,q[2],reset,q[3],qb[3]);
endmodule

module jkff(j,k,clock,reset,q,qb);
input j,k,clock,reset;
output reg q,qb;

10
always@(negedge clock)
begin
case({reset,j,k})
3'b100 :q=q;
3'b101 :q=0;
3'b110 :q=1;
3'b111 :q=~q;
default :q=0;
endcase
qb<=~q;
end
endmodule

SIMULATION RESULTS:

11
 [Link](c) Design and Simulation of Shift Registers

AIM:
To design and verify the Shift Registers using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the
output of each flip-flop is connected to the 'data' input of the next flip-flop in the chain, resulting
in a circuit that shifts by one position the 'bit array' stored in it, 'shifting in' the data present at its
input and 'shifting out' the last bit in the array, at each transition of the clock input.
Asynchronous or ripple counters.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

SISO:

module sisomod(clk,in,T);
input clk,in;
output T;
reg T;
reg [3:0] tmp;
always @(posedge clk )
begin
if (clear)
tmp <= 4’b0000;
else
tmp <= tmp << 1;
tmp[0] <= in;
T = tmp[3];
end
endmodule
12
SIMULATION RESULTS:

SIPO:

module SIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;
endmodule

13
SIMULATION RESULTS:

RESULT:

The basic sequential circuits was designed and simulated using Modelsim Software.

14
 [Link] Design and Simulation of 4 bit serial adder
AIM:
To design and verify the 4bit serial adder using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by
bit. Theserial full adder has three single-bit inputs for the numbers to be added and the carry in.
There are two single-bit outputs for the sum and carry out.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module serial(sum,cout,a,b,clk);
input [3:0] a,b;
input clk;
wire [3:0] x,z;
output [3:0] sum;
output cout;
wire s,cin;

15
fa k(s,cout,x[0],z[0],cin);
dff q(cin,cout,clk);
sipo m(sum,s,clk);
shift g(x,a,clk);
shift h(z,b,clk);
endmodule

module shift(y,d,clk);
input [3:0] d;
input clk;
output [3:0] y;
reg [3:0] y;
initial begin
assign y=d;
end
always @(posedge clk)
begin
assign y=y>>1;
end
endmodule

module sipo(y,s,clk);
input s;
input clk;
output [3:0] y;
reg [3:0] y;
always @(posedge clk)
begin
assign y={s,y[3:1]};
end
endmodule

module fa(s,cout,a,b,cin);
input a,b,cin;
output s,cout;
assign {cout,s}=a+b+cin;
endmodule

module dff(q,d,clk);
input d,clk;
output q;
reg q;
initial begin
q=1'b0;
end

16
always @(posedge clk)
begin
q=d;
end
endmodule

SIMULATION RESULTS:

RESULT:

The 4bit serial adder was designed and simulated using Modelsim Software

17
 [Link] Design and Simulation of 4 bit parallel adder/subtractor

AIM:
To design and verify the 4bit 4 bit parallel adder/subtractor

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
Parallel Adder :A single full adder performs the addition of two one bit numbers and an input
carry. But a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary
numbers that is greater than one bit in length by operating on corresponding pairs of bits in
parallel. It consists of full adders connected in a chain where the output carry from each full
adder is connected to the carry input of the next higher order full adder in the chain. A n bit
parallel adder requires n full adders to perform the operation. So for the two-bit number,
two adders are needed while for four bit number, four adders are needed and so on. Parallel
adders normally incorporate carry lookahead logic to ensure that carry propagation between
subsequent stages of addition does not limit addition speed.A Parallel Subtractor is a digital
circuit capable of finding the arithmetic difference of two binary numbers that is greater than one
bit in length by operating on corresponding pairs of bits in parallel. The parallel subtractor can be
designed in several ways including combination of half and full subtractors, all full subtractors or
all full adders with subtrahend complement input.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module ripple_carry_adder_subtractor(S, C, V, A, B, Op);

output [3:0] S;
output C;
output V;
input [3:0] A;
input [3:0] B;
input Op;
wire C0;
wire C1;
wire C2;
wire C3;

18
 wire B0;
wire B1;
wire B2;
wire B3;
xor(B0, B[0], Op);
xor(B1, B[1], Op);
xor(B2, B[2], Op);
xor(B3, B[3], Op);
xor(C, C3, Op);
xor(V, C3, C2);
full_adder fa0(S[0], C0, A[0], B0, Op
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2);

module full_adder(S, Cout, A, B, Cin);

output S;
output Cout;
input A;
input B;
input Cin;
wire w1;
wire w2;
wire w3;
wire w4;
xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule

SIMULATION RESULTS:

RESULT:

The 4bit adder/subtractor was designed and simulated using Modelsim Software.

19
 [Link] Design and Simulation of 4 bit multiplier

AIM:
To design and verify the 4bit 4 bit multiplier

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A binary multiplier is a combinational logic circuit used in digital systems to perform the
multiplication of two binary numbers. These are most commonly used in various applications
especially in the field of digital signal processing to perform the various algorithms.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module array4x4(a,b,p);
input [3:0]a,b;
output [7:0]p;
wire [39:0]w;
and a1(w[0],a[0],b[0]);
and a2(w[1],a[1],b[0]);
and a3(w[2],a[2],b[0]);

20
and a4(w[3],a[3],b[0]);

and a5(w[4],a[0],b[1]);
and a6(w[5],a[1],b[1]);
and a7(w[6],a[2],b[1]);
and a8(w[7],a[3],b[1]);
and a9(w[8],a[0],b[2]);
and a10(w[9],a[1],b[2]);
and a11(w[10],a[2],b[2]);
and a12(w[11],a[3],b[2]);
and a13(w[12],a[0],b[3]);
and a14(w[13],a[1],b[3]);
and a15(w[14],a[2],b[3]);
and a16(w[15],a[3],b[3]);
assign p[0]=w[0];
fulladder a17(1'b0,w[1],w[4],w[16],w[17]);
fulladder a18(1'b0,w[2],w[5],w[18],w[19]);
fulladder a19(1'b0,w[3],w[6],w[20],w[21]);
fulladder a20(w[8],w[17],w[18],w[22],w[23]);
fulladder a21(w[9],w[19],w[20],w[24],w[25]);
fulladder a22(w[10],w[7],w[21],w[26],w[27]);
fulladder a23(w[12],w[23],w[24],w[28],w[29]);
fulladder a24(w[13],w[25],w[26],w[30],w[31]);
fulladder a25(w[14],w[11],w[27],w[32],w[33]);
fulladder a26(1'b0,w[29],w[30],w[34],w[35]);
fulladder a27(w[31],w[32],w[35],w[36],w[37]);
fulladder a28(w[15],w[33],w[37],w[38],w[39]);
assign p[1]=w[16];
assign p[2]=w[22];
assign p[3]=w[28];
assign p[4]=w[34];
assign p[5]=w[36];
assign p[6]=w[38];
assign p[7]=w[39];

endmodule

FULL ADDER
module fulladder(a,b,c,s,ca);
input a,b,c;
output s,ca;
assign s=(a^b^c);
assign ca=((a&b)|(b&c)|(c&a));
endmodule

21
SIMULATION RESULTS:

RESULT:

The 4bit multiplier was designed and simulated using Modelsim Software.

22
 [Link] Design and testing of 8 bit ALU on FPGA board

AIM:
To design and verify the 8 bit ALU on FPGA board

SOFTWARE REQUIRED:
Xilinx ISE
Spartan 3E FPGA Kit

THEORY:
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit (CPU) of a
computer. Modern CPUs contain very powerful and complex ALUs.

PROCEDURE:

1. Open new Verilog source editor in Xilinx ISE tool

2. Type the Verilog coding for 8-Bit ALU in the new file
3. Save the file.
4. Assign the I/O Signal to the FPGA package pins
5. Synthesis the Verilog Code.
6. Place and Route the Design by click on Implement Design
7. Generate the bit file
8. Configure the bit file on Spartan 3E FPGA and verify the result

VERILOG CODING:
module alu(
input [7:0] A,B,
input [3:0] ALU_Sel

23
 output [7:0] ALU_Out,
output CarryOut );
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result;
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8];
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor

24
 ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule

SIMULATION RESULTS:

RESULT:

The 4bit ALU was designed and simulated using Xilinx Software and implemented in Spartan
3E kit.

25
 [Link] Design a real time clock and demonstrate its working on the FPGA board

AIM:
To design a real time clock and demonstrate its working on the FPGA board.

SOFTWARE REQUIRED:
Xilinx ISE
Spartan 3E FPGA Kit

THEORY:
A clock that keeps track of the time even when the computer is turned off. Real-time
clocks run on a special battery that is not connected to the normal power supply. In contrast,
clocks that are not real-time do not function when the computer is off. Although using a RTC we
have the following benefits: Low power consumption, Frees the main system for time-critical
tasks, sometimes more accurate than other methods.

PROCEDURE:

1. Open new Verilog source editor in Xilinx ISE tool

2. Type the Verilog coding for 8-Bit ALU in the new file
3. Save the file.
4. Assign the I/O Signal to the FPGA package pins
5. Synthesis the Verilog Code.
6. Place and Route the Design by click on Implement Design
7. Generate the bit file
8. Configure the bit file on Spartan 3E FPGA and verify the result

VERILOG CODING:

module new_code(clk,y,sel);
input clk;
output [7:0]y;
output [3:0]sel;
reg [7:0]y;
reg [3:0]sel;
integer w,i,f,j,k,n;
reg [1:0]state,stat;
parameter state0=2’b00;
parameter state1=2’b01;
parameter state2=2’b10;
parameter state3=2’b11;

26
initial begin
w=0; i=0; f=0; j=0; k=0; n=0;
state=state0; stat=state0;
end
always @( posedge clk) begin
if (i 500000) begin
if (w == 100) begin
f = f+1; //—-increment of each data for each device
w= 0;
end
else if (w < 100) begin
i = 0;
w = w + 1;
state = stat; //—-moving to each device for each count
end
if (state == state0) begin //—unit state
if (f == 0) begin
y = 8'b11000000 ;
sel = 4'b1000 ; //—-selecting first device
stat = state1;
end
if (f == 1) begin
y = 8'b11111001; //-/–data to be display
sel = 4'b1000 ;
stat = state1;
end
if (f == 2) begin
y = 8'b10100100; // —-code for selecting the segments in each display
sel = 4'b1000 ;
stat = state1;
end
if (f == 3) begin
y = 8'b10110000;
sel = 4'b1000 ;
stat = state1;
end
if (f == 4) begin
y = 8'b10011001;
sel = 4'b1000 ;
stat = state1;

27
end
if (f == 5) begin
y = 8'b10010010;
sel = 4'b1000 ;
stat = state1;
end
if (f == 6) begin
y = 8'b10000010;
sel = 4'b1000 ;
stat = state1;
end
if (f == 7) begin
y = 8'b11111000;
sel = 4'b1000 ;
stat = state1;
end
if (f == 8) begin
y = 8'b10000000;
sel = 4'b1000 ;
stat = state1;
end
if (f == 9) begin
y = 8'b10010000 ;
sel = 4'b1000 ;
stat = state1;
end
if(f==10) begin
y = 8'b10011000 ;
sel = 4'b1000 ;
stat = state1;
j = j + 1;
f = 0;
end
end
else if (state == state1) begin
if (j == 0) begin
y = 8'b11000000 ;
sel = 4'b0100 ;
stat = state2;
end

28
if (j == 1) begin
y = 8'b11111001;
sel = 4'b0100 ;
stat = state2;
end
if (j == 2) begin
y = 8'b10100100;
sel = 4'b0100 ;
stat = state2;
end
if (j == 3) begin
y = 8'b10110000;
sel = 4'b0100 ;
stat = state2;
end
if (j == 4) begin
y = 8'b10011001;
sel = 4'b0100 ;
stat = state2;
end
if (j == 5) begin
y = 8'b10010010;
sel = 4'b0100 ;
stat = state2;
end
if (j == 6) begin
y = 8'b10000010;
sel = 4'b0100 ;
stat = state2;
j = 0;
k = k + 1;
end
end
else if (state == state2) begin
if (k == 0) begin
y = 8'b01000000 ;
sel = 4'b0010 ;
stat = state3;
end
if (k == 1) begin

29
y = 8'b01111001;
sel = 4'b0010 ;
stat = state3;
end
if (k == 2) begin
y = 8'b00100100;
sel = 4'b0010 ;
stat = state3;
end
if (k == 3) begin
y = 8'b00110000;
sel = 4'b0010 ;
stat = state3;
end
if (k == 4) begin
y = 8'b00011001;
sel = 4'b0010 ;
stat = state3;
end
if (k == 5) begin
y = 8'b00010010;
sel = 4'b0010 ;
stat = state3;
end
if (k == 6) begin
y = 8'b00000010;
sel = 4'b0010 ;
stat = state3;
end
if (k == 7) begin
y = 8'b01111000;
sel = 4'b0010 ;
stat = state3;
end
if (k == 8) begin
y = 8'b00000000;
sel = 4'b0010 ;
stat = state3;
end
if (k == 9) begin

30
y = 8'b00011000 ;
sel = 4'b0010 ;
stat = state3;end
if (k == 10) begin
y = 8'b00010000 ;
sel = 4'b0010 ;
stat = state3;
k=0;
n=n+1;
end
end
if (state == state3) begin
if (n == 0) begin
y = 8'b11000000 ;
sel = 4'b0001 ;
stat = state0;
end
if (n == 1) begin
y = 8'b11111001;
sel = 4'b0001 ;
stat = state0;
end
if (n == 2) begin
y = 8'b10100100;
sel = 4'b0001 ;
stat = state0;
end
if (n == 3) begin
y = 8'b10110000;
sel = 4'b0001 ;
stat = state0;
end
if (n == 4) begin
y = 8'b10011001;
sel = 4'b0001 ;
stat = state0;
end
if (n == 5) begin
y = 8'b10010010;
sel = 4'b0001 ;

31
stat = state0;
end
if (n == 6) begin
y = 8'b10000010;
sel = 4'b0001 ;
stat = state0;
n = 0;
end
end
end
end
endmodule

SIMULATION RESULTS:

RESULT:

Thus the Real Time Clock was designed and implemented using FPGA.

32
 [Link] Basic gates using SPICE tool

AIM:
To design and verify the Basic gates using SPICE

SOFTWARE REQUIRED:
Tanner SPICE

PROCEDURE:
1. Open a new schematic cell in S-Edit
2. Add all the libraries
3. Design CMOS inverter circuit and specify the input and output
4. Save the file and include the TSMC 250nm model library
5. Open T-Spice and specify the transient analysis values
6. Save and run the netlist
7. Verify the input and output graphs
8. Check the Delay and Power results

CMOS INVERTER

DIAGRAM:

33
SIMULATION SETTINGS:
MNMOS_1 Out In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out In Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
.tran 10n 100n
vs vdd GND 5
v1 in GND BIT ({1010110})
.print tran v(in) v(out)
.power vs 10n 100n
.print tran p(vs)
.end

SIMULATION RESULTS:

34
 NAND GATE

DIAGRAM:

SIMULATION SETTINGS:
MNMOS_1 Out a N_1 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 N_1 b Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out a Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out b Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
.tran 10n 100n
vs vdd GND 5
v1 a GND BIT ({10101011})
v2 b GND BIT ({11001101})
.print tran v(a) v(b) v(out)
.print tran p(vs)
.power vs 10n 100n
.end

35
SIMULATION RESULTS:

NOR GATE

DIAGRAM:

36
SIMULATION SETTINGS:
MNMOS_1 Out a Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Out b Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_1 a Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Out b N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
.tran 10n 100n
vs vdd GND 5
v1 a GND BIT ({10101011})
v2 b GND BIT ({11001101})
.print tran v(a) v(b) v(out)
.power vs 10n 100n
.print tran p(vs)
.end

SIMULATION RESULTS:

RESULT:

Thus the CMOS basic gate was designed and verified using SPICE.

37
CONTENT BEYOND SYLLABUS

38
 [Link] Design and Simulation of Carry Save Adder

AIM:
To design and verify the Carry Save Adder using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A carry-save adder is a type of digital adder, used in computer microarchitecture to
compute the sum of three or more n-bit numbers in binary. It differs from other digital adders in
that it outputs two numbers of the same dimensions as the inputs, one which is a sequence of
partial sum bits and another which is a sequence of carry bits.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values

VERILOG CODING:

module carrysave(s,c,a,b);
output [3:0]s;
output c;
input [3:0]a,b;
wire [2:0]c2,c0;
fa u1(s[0],c0[0],a[0],b[0],1'b0);
dff1 u2(c2[0],c0[0],clk);
fa u3(s[1],c0[1],a[1],b[1],c2[0]);
dff1 u4(c2[1],c0[1],clk);
fa u5(s[2],c0[2],a[2],b[2],c2[1]);
dff1 u6(c2[2],c0[2],clk);
fa u7(s[3],c,a[3],b[3],c2[2]);
endmodule

module fa(s,co,a,b,ci);
output s,co;
input a,b,ci;
xor1 u1(s,a,b,ci);
and1 u2(n1,a,b);
and1 u3(n2,b,ci);

39
and1 u4(n3,a,ci);
or1 u5(co,n1,n2,n3);
endmodule

module dff1(D,clk,Q);
input D;
input clk;
output Q;
always @(posedge clk)
begin
Q <= D;
end
endmodule

SIMULATION RESULTS:

RESULT:

The Carry Save Adder was designed and simulated using Modelsim Software.

40
 [Link] Design and Simulation of Phase Locked Loop(PLL)

AIM:
To design and verify PLL using Verilog.

SOFTWARE REQUIRED:
ModelSim 6.2c

THEORY:
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal
whose phase is related to the phase of an input signal. There are several different types; the
simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector
in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares
the phase of that signal with the phase of the input periodic signal, adjusting the oscillator to
keep the phases matched.
Keeping the input and output phase in lock step also implies keeping the input and output
frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop
can track an input frequency, or it can generate a frequency that is a multiple of the input
frequency. These properties are used for computer clock synchronization, demodulation, and
frequency synthesis.

PROCEDURE:
1. Open new file in Verilog source editor
2. Type the Verilog coding for the circuit in the new file.
3. Save the file .
4. Compile and Simulate the Program.
5. Add the selected signal to the wave form window.
6. Force the input signals values and verify the output signal values.

41
VERILOG CODING:

module pll_test;
reg ref_clock=0;
always #(`CYCLE) ref_clock=~ref_clock;
pll_module #(.File_Name("loop_filter.txt")) PLLl_1MHz (ref_clock);
pll_module #(.File_Name("loop_filter1MHz_much_phase.txt")) PLLl_1M_Much(ref_clock);
pll_module #(.File_Name("loop_filter1MHz_less_phase.txt")) PLLl_1M_Less(ref_clock);
endmodule

module pll_module #(parameter File_Name="loop_filter.txt") (input ref_clock);

wire v_clock,d_clock;
wire [1:0] iout;
pfd pll1(.ref_clock(ref_clock),
.d_clock(d_clock),
.iout(iout));
loop_filter_and_vco #(.File_Name(File_Name)) lvco(.iout(iout),.v_clock(v_clock));
divider #(.DRatio(16)) div(.v_clock(v_clock),.d_clock(d_clock));
endmodule

module divider #(parameter integer DRatio=32)

( input v_clock,
output reg d_clock=0);

integer counter=0;
always @(posedge v_clock) begin
if (counter==DRatio-1) counter <=0;
else counter <=counter+1;
end
always @(posedge v_clock) begin
if (counter ==DRatio-1) d_clock<=~d_clock;
end
endmodule

module loop_filter_and_vco #(parameter File_Name="loop_filter.txt")

( input signed [1:0] iout,
output v_clock);

localparam real Igain=-(-260e-6);//A

localparam real Igminus=260e-6;
localparam integer cycle=100;//ps
localparam real Vco_Gain=200*1e6;//Hz/V
localparam real Center_Frequency=200e6;//433.92e6;//Hz

real I;
real read_array[0:10];// Input vector for rungekutta

42
 real write_array[0:10];//Output vector from rugekutta
real vco_in;
real omega,delta_theta;
real theta,delta_theta;
real vco_waveform;
always @(*) I=Igain*iout;
always #(cycle) begin
read_array[0]=I;//
$runge_kutta(File_Name,1);//Loop Filter V/I
vco_in=write_array[0];//Get Loop Filter voltage
omega=2.0*(Center_Frequency+vco_in*Vco_Gain)*$M_PI;
delta_theta=cycle*1e-12*omega;//
theta=theta+delta_theta;
vco_waveform=$sin(theta);//
end
assign v_clock=vco_waveform>=0 ? 1:0;
initial begin

$runge_kutta(File_Name,0,read_array,write_array);//rugekutta Initialization
#(8200*1000) $finish;
end
endmodule

module pfd( input ref_clock,

input d_clock,
output reg signed [1:0] iout);
integer state=0;
always @(posedge ref_clock) state=state+1;
always @(posedge d_clock) state=state-1;

always @(*) begin

if (state>0) state=1;
else if (state<0) state=-1;

if (state>0) iout=1;
else if (state<0) iout=-1;
else iout=0
end
endmodule

43
SIMULATION RESULTS:

RESULT:

The PLL was designed and simulated using Modelsim Software.

44