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8086 Bus Cycle - System Configuration

The document describes the minimum mode read bus cycle of the 8086 microprocessor. It has 4 states - T1 where the microprocessor outputs the 20-bit address on the address/data bus and asserts control signals, T2 where it removes the address and prepares for reading data, T3 where it samples the data bus for valid data, and T4 where it deactivates control signals to end the bus cycle.

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446 views

8086 Bus Cycle - System Configuration

The document describes the minimum mode read bus cycle of the 8086 microprocessor. It has 4 states - T1 where the microprocessor outputs the 20-bit address on the address/data bus and asserts control signals, T2 where it removes the address and prepares for reading data, T3 where it samples the data bus for valid data, and T4 where it deactivates control signals to end the bus cycle.

Uploaded by

Warrior Prince
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Draw and explain the minimum mode Read Bus Cycle of 8086 microprocessor.

ANS:
In this bus cycle 8086 microprocessor read data from Memory or I/O device.
T1 State:
During T1 state microprocessor outputs the 20-bit address computed from a segment register and offset on
the multiplexed address/data/status bus.
During this T-state control signals ALE=1, DT/R’=0, M/IO’=1 (for memory Read) or 0 (for I/O read).
T2 state:
In this T-state microprocessor remove the
address from multiplexed bus and tri-state
the AD0-AD15 line in preparation for
reading data via AD0-AD15 in T3-state.
During T2 state microprocessor generate
RD’=0, to active memory or Input port
for reading data and DEN’=0, to enable
data bus buffer. So microprocessor can
accept the data from memory or I/O
device.
T3 state:
READY signal is sampled at the
beginning of T3-State, if it is low then
Wait state is inserted between T3 and T4
state else T4 state is executed.
Microprocessors sampled the data bus in
this state for valid data and store it in the
internal register.
T4 State:
In this T-state microprocessor deactivates all the control signal to terminate Read bus cycle and prepare for
the next bus cycle.
Draw and explain 8086 minimum mode write bus cycle.

In this bus cycle 8086 microprocessor write data in


Memory or I/O device.
T1 State:
In this T-state microprocessor outputs the 20-bit
address computed from a segment register and offset
on the multiplexed address/data/status bus.
During this T-state control signals ALE=1, DT/R’=1,
M/IO’=1 (for memory write) or 0 (for I/O write).
T2 state:
In this T-state microprocessor remove the address
from multiplexed bus and load data in AD0-AD15
During T2 state microprocessor issue
WR’=0 , to enable memory or output port for write
operation and DEN’=0, enable data bus buffer. So
microprocessor can transmit the data to load in memory
or output port.
T3 state:
Memory or output device loaded by the data from data
bus in this T-state.
READY signal is sampled at the beginning of T3-State,
if it is low then Wait state is inserted between T3 and
T4 state else T4 state is executed.
T4 State:
In this T-state microprocessor deactivates all the control
signal to terminate Write bus cycle and prepare for the
next bus cycle.
Draw and explain the Maximum mode Read Bus Cycle of 8086 microprocessor.

MAXIMUM MODE READ BUSCYCLE:

In this bus cycle microprocessor read data from


the memory or Input device. This bus cycle will
be executed by the 8086 processor in 4 T-states.

T1: In this T-states microprocessor generate


20-bit physical address of memory in
external address bus and latch it externally
using ALE =1. At the beginning of this
state DT/R’ = 0, for selecting the receiving
mode of data bus buffer connected with
the data bus of 8086.

T2: In this T-state rising edge memory Read or


I/O read control signal will be generated
by the bus controller to enable memory or
Input device or for Read operation and
Data enable (DEN) signal will be activate
to enable the data bus buffer.

T3: In this T-state valid data will be placed in


the data bus by the memory or input
device and to be read by the processor.
S0’-S2’ status signals are inactive in this T-state.

T4: Read control signal and DEN signal will be deactivate around in the rising edge of this state
to terminate the read bus cycle.
Status signals (S0’ to S2’) are activate in this T-states to indicate the type of next bus cycle to
be execute.
Draw and explain the Maximum mode Write Bus Cycle of 8086 microprocessor.

ANS:

MAXIMUM MODE WRITE BUSCYCLE:

In this bus cycle microprocessor write data in the memory or output device. This bus cycle will be
executed by the 8086 processor in 4 T-states.

T1: In this T-states microprocessor generate


20-bit physical address of memory in
external address bus and latch it
externally using ALE =1. At the
beginning of this state DT/R’ = 1, for
selecting the transmitting mode of data
bus buffer connected with the data bus of
8086.

T2: At the beginning of this state valid data


will be placed in the data bus by the
processor.
In this T-state rising edge advanced
memory write (AMWC’=0) control
signal will be generated by the bus
controller to enable write operation and
Data enable (DEN) signal will be activate
to enable the data bus buffer.

T3: Standard write control signal (MWTC’=0)


will be activated in this T-state for enable
memory or output device for write operation by the processor. Valid data will be load in the
output device or memory in this T-state. S0- S2 status signals are inactive in this T-state.

T4: Write control signal and DEN signal will be deactivate around in the rising edge of this state
to terminate the write bus cycle.
Status signals (S0’ to S2’) are activate in this T-states to indicate the type of next bus cycle to
be execute.

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