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Chap 6

This document discusses pipelining in CPUs to improve performance. It describes a 5-stage MIPS pipeline with fetch, decode, execute, memory, and writeback stages. Pipelining allows overlapping execution of instructions to increase throughput. Hazards like structure, data, and control hazards can prevent back-to-back instruction completion and need to be addressed. Various techniques like forwarding, stalling, code scheduling, and branch prediction are used to mitigate hazards in pipelined CPUs.

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45 views

Chap 6

This document discusses pipelining in CPUs to improve performance. It describes a 5-stage MIPS pipeline with fetch, decode, execute, memory, and writeback stages. Pipelining allows overlapping execution of instructions to increase throughput. Hazards like structure, data, and control hazards can prevent back-to-back instruction completion and need to be addressed. Various techniques like forwarding, stalling, code scheduling, and branch prediction are used to mitigate hazards in pipelined CPUs.

Uploaded by

uchihard
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 6

Enhancing Performance with Pipelining

1
Pipelining analogy
 Pipelining:
overlapping
execution
 Parallelism
improves
performance

2
MIPS pipeline
 Five stages:
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register read
3. EX: Execute operation or calculate address
4. MEM: Access memory operand
5. WB: Write result back to register

3
MIPS pipeline
Time

1 2 3 4 5 6 7 8 9 10

Instruction 1 IF ID EX MEM WB

Instruction 2 IF ID EX MEM WB

Instruction 3 IF ID EX MEM WB

Instruction 4 IF ID EX MEM WB

Instruction 5 IF ID EX MEM WB

Instruction 6 IF ID EX MEM WB

4
Pipeline performance
 Assume time for stages is
▪ 100ps for register read or write
▪ 200ps for other stages

5
Pipeline performance

6
Hazards
 Situations that prevent starting the next instruction in
the next cycle
 Structure hazards
▪ Two or more instructions that are already in the pipeline
need the same resource
 Data hazard
▪ Need to wait for previous instruction to complete its data
read/write
 Control hazard
▪ Deciding on control action depends on previous
instruction
7
Structure hazards
 Conflict for use of a resource
 In MIPS pipeline with a single memory
▪ Load/store requires data access
▪ Instruction fetch would have to stall for that cycle
− Would cause a pipeline “bubble”

 Hence, pipelined datapaths require separate


instruction/data memories
▪ Or separate instruction/data caches

8
Data hazards
 An instruction depends on completion of data access
by a previous instruction
add $s0, $t0, $t1
sub $t2, $s0, $t3

9
Forwarding
 Use result when it is computed
▪ Don’t wait for it to be stored in a register
▪ Requires extra connections in the datapath

10
Load-use data hazards
 Can’t always avoid stalls by forwarding
▪ If value not computed when needed
▪ Can’t forward backward in time

“Stall one stage”

11
Code scheduling to avoid stalls
 Reorder code to avoid use of load result in the next
instruction
 C code for A = B + E; C = B + F;

12
Control hazards
 Also known as a branch hazard
 Occurs when the pipeline makes the wrong decision on a
branch prediction
 Brings instructions into the pipeline that must subsequently
be discarded
beq $t0, $t1, Loop
addi $s0, $s1, 3
…
Loop: sub $s2, $s0, $s3

13
Stall on branch
 Wait until branch outcome determined before fetching
next instruction

14
Branch prediction
 Longer pipelines can’t readily determine branch
outcome early
▪ Stall penalty becomes unacceptable
 Predict outcome of branch
▪ Only stall if prediction is wrong
 In MIPS pipeline
▪ Can predict branches not taken
▪ Fetch instruction after branch, with no delay

15
Branch prediction
 Longer pipelines can’t readily determine branch
outcome early
▪ Stall penalty becomes unacceptable
 Predict outcome of branch
▪ Only stall if prediction is wrong
 In MIPS pipeline
▪ Can predict branches not taken
▪ Fetch instruction after branch, with no delay

16
MIPS pipelined datapath

17
Pipeline registers
 Need registers between stages to hold information
produced in previous cycle

18
Pipeline summary
 Pipelining improves performance by increasing
instruction throughput
▪ Executes multiple instructions in parallel
▪ Each instruction has the same latency
 Subject to hazards
▪ Structure, data, control
 Instruction set design affects complexity of pipeline
implementation

19
Exercises
 6.1, 6.2, 6.3, 6.4, 6.39
 Chapter 6, David A. Patterson & John L. Hennessy,
Computer Organization and Design – The
Hardware/Software Interface, 3rd Edition, Morgan
Kaufmann

20

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