Multicycle Datapath

PC 0 0
M Instruction Read
[25– 21] register 1 M
u Address u
x Read x
Instruction Read A
1 Memory Zero
[20– 16] register 2 data 1 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write result
Read
[15– 0] Instruction u register data 2 B 0
Write [15– 11] x
Instruction Write 4 1 M
data 1 u
register data 2 x
Instruction 0 3
[15– 0] M
u
x
Memory 1
data 16 32
Sign Shift
register
extend left 2

Basic multicycle MIPS datapath handles R-type instructions and load/stores:

new internal register in red ovals, new multiplexors in blue ovals
Breaking instructions into steps
 We break instructions into the following potential execution steps
– not all instructions require all the steps – each step takes one
clock cycle
1. Instruction fetch and PC increment (IF)
2. Instruction decode and register fetch (ID)
3. Execution, memory address computation, or branch completion (EX)
4. Memory access or R-type instruction completion (MEM)
5. Memory read completion (WB)

 Each MIPS instruction takes from 3 – 5 cycles (steps)

 Step 1: Instruction Fetch &
PC Increment (IF)
 Use PC to get instruction and put it in the instruction register.
Increment the PC by 4 and put the result back in the PC.

 Can be described succinctly using RTL (Register-Transfer Language):

IR = Memory[PC];
PC = PC + 4;
 Multicycle Execution Step (1):
Instruction Fetch
IR = Memory[PC];
PC = PC + 4;

PC + 4
4
Step 2: Instruction Decode and
Register Fetch (ID)
 Read registers rs and rt in case we need them.
Compute the branch address in case the instruction is a branch.

 RTL:
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
Multicycle Execution Step (2):
Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])
B = Reg[IR[20-15]]; (B = Reg[rt])
ALUOut = (PC + sign-extend(IR[15-0]) << 2)

Branch
Reg[rs]
Target
Address

PC + 4

Reg[rt]
Step 3: Execution, Address
Computation or Branch Completion
(EX)
 ALU performs one of four functions depending on instruction
type
 memory reference:
ALUOut = A + sign-extend(IR[15-0]);
 R-type:
ALUOut = A op B;
 branch (instruction completes):
if (A==B) PC = ALUOut;
 jump (instruction completes):
PC = PC[31-28] || (IR(25-0) << 2)
 Multicycle Execution Step (3):
Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);

Reg[rs] Mem.
Address

PC + 4

Reg[rt]
 Multicycle Execution Step (3):
ALU Instruction (R-Type)
ALUOut = A op B

Reg[rs]
R-Type
Result

PC + 4

Reg[rt]
 Multicycle Execution Step (3):
Branch Instructions
if (A == B) PC = ALUOut;

Branch
Reg[rs]
Target
Address

Branch
Target
Address
Reg[rt]
 Multicycle Execution Step (3):
Jump Instruction
PC = PC[31-28] concat (IR[25-0] << 2)

Branch
Reg[rs]
Target
Address

Jump
Address
Reg[rt]
Step 4: Memory access or R-type
Instruction Completion (MEM)
 Again depending on instruction type:
 Loads and stores access memory
 load
MDR = Memory[ALUOut];
 store (instruction completes)
Memory[ALUOut] = B;

 R-type (instructions completes)

Reg[IR[15-11]] = ALUOut;
 Multicycle Execution Step (4):
Memory Access - Read (lw)
MDR = Memory[ALUOut];

Reg[rs] Mem.
Address

PC + 4

Mem. Reg[rt]
Data
 Multicycle Execution Step (4):
Memory Access - Write (sw)
Memory[ALUOut] = B;

Reg[rs]

PC + 4

Reg[rt]
 Multicycle Execution Step (4):
ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOUT

Reg[rs]
R-Type
Result

PC + 4

Reg[rt]
Step 5: Memory Read
Completion (WB)
 Load writes back (instruction completes)
Reg[IR[20-16]]= MDR;

Important: There is no reason from a datapath (or control) point

of view that Step 5 cannot be eliminated by performing
Reg[IR[20-16]]= Memory[ALUOut];
for loads in Step 4. This would eliminate the MDR as well.

The reason this is not done is that, to keep steps balanced in

length, the design restriction is to allow each step to contain
at most one ALU operation, or one register access, or one
memory access.
 Multicycle Execution Step (5):
Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;

Reg[rs]
Mem.
Address

PC + 4

Mem. Reg[rt]
Data
 Summary of Instruction Execution

Step Action for R-type Action for memory-reference Action for Action for
Step name instructions instructions branches jumps
1: IF Instruction fetch IR = Memory[PC]
PC = PC + 4
Instruction A = Reg [IR[25-21]]
2: ID decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] II
3: EX computation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)
jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]
4: MEM completion ALUOut or
Store: Memory [ALUOut] = B
5: WB Memory read completion Load: Reg[IR[20-16]] = MDR
 Multicycle Datapath with Control I
IorD MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA

PC 0 0
M Instruction Read
[25– 21] register 1 M
u Address u
x Read x
Instruction Read A Zero
1 Memory data 1
[20– 16] register 2 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write Read result
[15– 0] register data 2 B
Instruction u 0
Write x
Instruction [15– 11]
Write 4 1 M
data 1 u
register data 2 x
Instruction 0 3
[15– 0] M
u
x
Memory 1
data 16 32 ALU
Sign Shift
register control
extend left 2

Instruction [5– 0]

MemtoReg ALUSrcB ALUOp

… with control lines and the ALU control block added – not all control lines are shown
Multicycle Datapath with Control II
New gates New multiplexor
For the jump address

PCWriteCond PCSource
PCWrite ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
MemtoReg RegWrite
Op RegDst
IRWrite [5– 0]
0
M
Jump 1 u
Instruction [25– 0] 26 28 address [31-0] x
Shift
left 2 2
Instruction
[31-26]
PC 0 PC [31-28]
0
M Instruction Read
[25– 21] register 1 M
u Address u
x Read x
Instruction Read A Zero
1 Memory
[20– 16] register 2 data 1 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write result
Read B
[15– 0] Instruction u register data 2 0
Write Instruction [15– 11] x 1 M
Write 4
data register 1 u
data 2 x
Instruction 0 3
[15– 0] M
u
x
Memory 1
data 16 32 ALU
Sign Shift
register control
extend left 2

Instruction [5– 0]

Complete multicycle MIPS datapath (with branch and jump capability)

and showing the main control block and all control lines
 Multicycle Control Step (1): Fetch
IR = Memory[PC];
PC = PC + 4;

1
IRWrite

I Instruction I jmpaddr 28 32
1 R 5 I[25:0] <<2 CONCAT
PCWr* rs rt rd
2
0 0 32 5 5
0
MUX
1 RegDst
0 M
IorD 1U
PC
5 X ALUSrcA 010
Operation 0
X

MemWrite RN1 RN2 WN 3

0M 0M
U ADDR M U PCSource
1X 1M Registers 1X Zero
Memory D RD1 A 0
RD R U WD ALU
0X ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
2X
X RegWrite
3
1 0 E
X ALUSrcB
immediate 16 32
T <<2 1
N
D
Multicycle Control Step (2):
Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])
B = Reg[IR[20-15]]; (B = Reg[rt])
ALUOut = (PC + sign-extend(IR[15-0]) << 2);

0IRWrite

I Instruction I jmpaddr 28 32
0 R 5 I[25:0] <<2 CONCAT
PCWr* rs rt rd
X 0 1 RegDst 0 2
IorD 0 32 5 5 MUX
5 X ALUSrcA 010 1U
M

X
PC Operation 0
MemWrite RN1 RN2 WN 3
0M 0M
U ADDR M U PCSource
1X 1M Registers 1X Zero
Memory D RD1 A X
RD R U WD ALU
0X ALU
OUT
WD RD2 B 0
MemRead MemtoReg 4 1M
U
X 2X
3
RegWrite
0 0 E
X ALUSrcB
immediate 16 32
T <<2 3
N
D
Multicycle Datapath with Control II
New gates New multiplexor
For the jump address

PCWriteCond PCSource
PCWrite ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
MemWrite Control
MemtoReg RegWrite
Op RegDst
IRWrite [5– 0]
0
M
Jump 1 u
Instruction [25– 0] 26 28 address [31-0] x
Shift
left 2 2
Instruction
[31-26]
PC 0 PC [31-28]
0
M Instruction Read
[25– 21] register 1 M
u Address u
x Read x
Instruction Read A Zero
1 Memory
[20– 16] register 2 data 1 1
0 ALU ALU ALUOut
MemData Registers
Instruction M Write result
Read B
[15– 0] Instruction u register data 2 0
Write Instruction [15– 11] x 1 M
Write 4
data register 1 u
data 2 x
Instruction 0 3
[15– 0] M
u
x
Memory 1
data 16 32 ALU
Sign Shift
register control
extend left 2

Instruction [5– 0]

Complete multicycle MIPS datapath (with branch and jump capability)

and showing the main control block and all control lines