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4 Bit Full Adder

The document describes designing and implementing a 4-bit ripple carry adder using VHDL. It involves cloning a 1-bit full adder component four times and connecting the carry outputs to form a ripple carry adder. Test vectors are applied and the output waveform is observed to verify the adder design works as intended.

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Vinay Yadav
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322 views5 pages

4 Bit Full Adder

The document describes designing and implementing a 4-bit ripple carry adder using VHDL. It involves cloning a 1-bit full adder component four times and connecting the carry outputs to form a ripple carry adder. Test vectors are applied and the output waveform is observed to verify the adder design works as intended.

Uploaded by

Vinay Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment No:

Aim: To design and implement a 4-bit ripple carry adder using VHDL.

Software: Xilinx - vivado

Theory: In the ripple carry adder, the output is known after the carry generated by the previous
stage is produced. Thus, the sum of the most significant bit is only available after the carry signal
has rippled through the adder from the least significant stage to the most significant stage. As a
result, the final sum and carry bits will be valid after a considerable delay.
Program

-- program for 1 bit full adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is

port (A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

S : out STD_LOGIC;

Cout : out STD_LOGIC

);

end full_adder;

architecture Behavioral of full_adder is

begin

S <= A xor B xor Cin;

Cout <= (A and B) or (B and Cin) or (Cin and A);

end Behavioral;

-- program for 4 bit full adder by cloning it in 1 bit full adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Ripple_Adder is

Port ( A : in STD_LOGIC_VECTOR (3 downto 0);

B : in STD_LOGIC_VECTOR (3 downto 0);

Cin : in STD_LOGIC;

S : out STD_LOGIC_VECTOR (3 downto 0);

Cout : out STD_LOGIC);

end Ripple_Adder;

architecture Behavioral of Ripple_Adder is

-- Full Adder VHDL Code Component Decalaration

component full_adder

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

S : out STD_LOGIC;

Cout : out STD_LOGIC);

end component;

-- Intermediate Carry declaration

signal c1,c2,c3: STD_LOGIC;

begin
-- Port Mapping Full Adder 4 times

FA1: full_adder port map( A(0), B(0), Cin, S(0), c1);

FA2: full_adder port map( A(1), B(1), c1, S(1), c2);

FA3: full_adder port map( A(2), B(2), c2, S(2), c3);

FA4: full_adder port map( A(3), B(3), c3, S(3), Cout);

end Behavioral;

Schematic Diagram:
Waveform:

Conclusion:

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