Exercises Solution Chapter 1 (111CNET-3)
Exercises Solution Chapter 1 (111CNET-3)
CHAPTER 1
1.1 Base 10 : 10 11 12 13 14 15 16 17 18 19 20 21 22
Octal : 12 13 14 15 16 17 20 21 22 23 24 25 26
Hex :A B C D E F 10 11 12 13 14 15 16
Base 12 :A B 10 11 12 13 14 15 16 17 18 19 1A
Base 10 : 23 24 25 26 27 28 29 30 31 32
Octal : 27 30 31 32 33 34 35 36 37 40
Hex : 17 18 19 1A 1B 1C 1D 1E 1F 20
Base 12 : 1B 20 21 22 23 24 25 26 27 28
(b) 33,554,432
(c) 3,435,973,837
(c) (475)8 = 4 × 82 + 7 × 81 + 5 × 80
= 256 + 56 + 5
= (317)10
(d) (2345)6 = 2 × 63 + 3 × 62 + 4 × 61 + 5 × 60
= 432 + 108 + 24 + 5
= (569)10
(a) 12 × 4 = 52 → (b + 2) 4 = 5b + 2
4b + 8 = 5b + 2
b=6
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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(c) (2 × b + 4) + (b + 7) = 4b, so b = 11
1.6 x2 – 13x + 32 = 0
(x – 5)(x – 4) = 0
x2 – (5 + 4)x + 5 × 4 = x2 – 13x + 32
So, 5 + 4 = b + 3 5 × 4 = 3b + 2
b=6 OR b=6
2 128 – 0 ⇒ (1000000000)2
2 64 –0
2 32 –0
2 16 –0
2 8 –0
2 4 –0
2 2 –0
1 –0
16 32 –0 ⇒ (200)16
To binary
(200)16 = (10 0000 0000)2
2nd method is faster.
2 4
(c) (276.24)8 = 2 × 82 + 7 × 8 + 6 + +
8 64
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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4
11
(d) (BABA.B)16 = 11 × 163 + 10 × 162 + 11 × 161 + 10 +
16
= 45056 + 2560 + 176 + 10 + 0.6875
= (47802.6875)10
9
1.10 (a) 1.100102 = 0001.10012 = 1.916 = 1 + = 1.56310
16
1.11 1010.1
110 | 111111
110
111 ⇒ (1010.1)2
110
110
110
0
(b) (AB)16 AB × 1C
+(1C)16 804
(C7)16 AB+
(12B4)16
2 35
2 17 – 1 0.125 × 2 = 0.25
2 8 –1 0.25 × 2 = 0.5
2 4 –0 0.5 × 2 = 1.0
2 2 –0
1 –0
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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5
1
(b) = 0.33333333
3
= (0.01010101)2 ⇒ (0.33203125)10
1.14 (a) 1111 0000 (b) 0000 0000 (c) 1101 1000
1’s comp:0000 1111 1’s comp: 1111 1111 1’s comp: 0010 0111
2’s comp: 0001 0000 2’s comp: 0000 0000 2’s comp: 0010 1000
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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6
1.18
(a) 10010 10101
1’s comp : 01101 +01110
2’s comp : 01110 1 00011 Ans: 00011
drop
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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7
= 008127
drop 1
= 991873 ⇒ –8127
= 989965 ⇒ –10035
1
drop
+0 100011
1 011011 (overflow)
1011011 → 91
+1 011101
0010101 ⇒ +21
drop
+0 100011
1 101011 ⇒ –21
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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8
+ 000641
010183
1 +999359
008901
drop
+000641
991099 ⇒ −8901
989817 ⇒ −10183
drop
1.22 (7654)10
BCD: 0111 0110 0101 0100
ASCII: 0 0110111 0110110 0110101 0110100
7 6 5 4
1.23
694 0110 1001 0100
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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9
1.25 (6514)10
(a) BCD : 0110 0101 0001 0100
(b) Excess 3 : 1001 1000 0100 0111
(c) 2421 : 1100 1011 0001 0100
(d) 6311 : 1000 0111 0001 0101
1.26 6514
9’s comp : 3485
2421 : 0011 0100 1110 1011 → ①
1.27 For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb's select the suit (e.g.,
diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits
select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack,
queen, king). This a jack of spades might be coded as 11 1010. (Note: only 52 out of 64 patterns are
used.)
1.28 G e o r g e
(space) 1100 0111 1110 0101 1110 1111 1111 0010 0110 0111
1110 0101 0010 0000 B
1100 0010 1010 1110
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
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(a) BCD 5 6 4
(b) Excess-3 2 3 1
(c) 84-2-1 3 2 4
0 → 1 011 0000
1 → 0 011 0001
2 → 0 011 0010
3 → 1 011 0011
4 → 0 011 0100
5 → 1 011 0101
6 → 1 011 0110
7 → 0 011 0111
1.35 (a)
a b c
a
f
b
c
g
f
1.36
a b
a
f
b
g
f
Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012,
All rights reserved.