Model Test Paper
Model Test Paper
1. Find the region of operation for each transistor in Fig.1. Calculate the drain current in each of the [10]
cases.
Fig.1
2. Derive the drain current equation of NMOS transistor at various regions of operations. Discuss any [10]
three non-ideal effects.
3. a) Determine the value of Out in Fig. 2 if A, B and C is HIGH and LOW. [6]
Fig. 2
b) Compare the merits and demerits of FinFET with CMOS devices. [4]
4. i. Derive the expression for output voltage of CMOS inverter at region C. Determine the transistor [10]
size ratio so that VM = 1.5V
ii. If you desire to design an inverter such that NMH> NML, then how do you size the NMOS and
PMOS transistors of the inverter? Explain your answer.
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5. Calculate the path delay from in to out. In order to minimize the delay, what should the size of the [10]
gates in Fig. 3 from In to Out.
Fig. 3
6. i) What is the logic function implemented by the CMOS transistor network in Fig. 4? Size the [10]
NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an
NMOS W/L = 4 and PMOS W/L = 8.
ii) What are the input patterns that give the worst case tpHL and tpLH.
Fig. 4
7.(a) Identify the logic function of the stick diagram in Fig.5 [10]
i) sketch a transistor-level schematic
ii) estimate the area from the stick diagram for λ = 65 nm.
Fig. 5
OR
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7.(b) For the CMOS compounded OAI21 logic [10]
i. sketch a transistor-level schematic
ii. draw the optimized stick diagram using Euler’s path.
iii. estimate the area from the stick diagram for λ = 90 nm.
Fig. 6
9. Design Pulsed Latches and Enabled Latches. Explain the operation of latches using waveforms. [10]
10.(a) Design a 16-bit adder using 4-bit Carry Look ahead Adder. Discuss the limitation in direct realization [10]
16-bit Carry Look ahead Adder.
OR
10.(b) Discuss in detail about the design and working of 4-bit Barrel shifter. [10]
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