LAB 4 BASIC COMPUTER ORGANIZATION

1. Objectives
In this laboratory, students will analyse the structure of a basic computer, will devise and design its
control unit, and will use opcodes to write simple programs in machine code. The design must
function in simulation, and also on the DE2-115 Altera development board.
2. Equipment and Supplies:
* Quartus II (student edition or web edition)
* Altera DE2-115 board with
- USB-blaster cable
- Power supply 12 VDC, 2A

3. References
 You are provided with all the .bdf files, except one that describes the combinational circuits
which generates the output and transition functions of the Control Unit and which you are
expected to conceive and develop. Their logic diagrams are annexed to this document.
 Chapters 5 and 6 of the textbook: Computer Systems Structures, Morris Mano, 3rd edition,
1993, ISBN 0-13-175563-3.
 The course notes
 The user guide of the Altera DE2-115 development kit is provided in the Laboratories >
Documentation section of your CEG2136 Virtual Campus.

4. The Structure of the Basic Computer

4.1 General View
This laboratory implements a computer having a structure that is very close to the one presented in
figure 5.4 on page 130 of your textbook. However, there are two major differences:
1. The designed computer’s memory (storing both programs and data) has a capacity of 256 words of
8 bits (256 x 8). In the textbook, the BASIC computer has a memory with words of 16 bits, each
word being capable of storing one memory-reference instruction (which consists there of a 4-bit
opcode and a 12-bit memory address). In this lab, a memory-reference instruction is 2 byte long as
well, but the msb byte carries the opcode, while the lsb byte contains the operand address (8 bits
are enough to address a memory space of 28 = 256 memory locations); as such, a 2-byte memory-
reference instruction is stored in 2 consecutive memory locations (two 1-byte words).
Consequently, two successive READ cycles are needed to fetch a memory-reference instruction:
first to get the opcode, and the second to get the address of the data that the opcode will use.
2. The second major difference consists in the additional circuits which will allow a user to visualize
the contents of the memory independently of having a program running or not on the DE2-115
board.
User can preset the DIP switches on the board with the memory address to be visualized. Before
the fetch phase of each instruction, the BASIC computer reads the contents of the memory location
pointed at by the DIP switches on the board, and shows it in hexadecimal format on the 7 segment
display of the board.

The block diagram of your computer is presented in Figure 1. The .bdf files of all the component blocks,
except the Instruction Decoder (lab_controller of CU), will be provided. The Control Unit functions
in accord with a time sequence which is generated by the sequence counter (SC) that plays the role of
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FSM state register. The SC initial state is 0; it restarts counting from 0 at the beginning of each
instruction of a program and it is reset to 0 once that instruction is finished. A decoder converts the 4-
bit output of the SC into time-signals, distinct for each possible output (for example, when the SC
output is 0010, then the T2 output of the decoder will go high, if not, it will remain low for any other
combination); this combination of the SC and its decoder implement a One-hot encoded state register.
The control commands for the Datapath are synthesized by the Instruction Decoder as (FSM output)
functions in terms of the contents of the IR, DR and other signals from the Datapath; a set of gates
(AND, OR, and NOT) forms the Instruction Decoder. As some CU outputs are of Mealy type, a bank
of buffer registers (Control Register) is used to insure a duration of one clock period for the control
commands that are generated by the CU, and to synchronize them with the system clock.

Data[7..0]
256 x 8 Memory
Data[7..0]
Address [7..0] CPU
Datapath Control Unit
Address register (AR)  8
Sequence counter
(SC) State Register
4
Program counter (PC)  8
State Decoder (T)
Stop register
IR [7..0] 16
Instruction register (IR)  8
8
Instruction Decoder
DR [7..0 ] (lab_controller)
8
Data register (DR) 
Control Register
(Register bank)
8

ALU Accumulator (AC)  λ(Sn,Xn)

8 Control commands to 
counters , registers , bus
multiplexer and ALU
Bus 
INPUT Address REGISTER 8
select
(OUTA ) DIP switches
Data[7..0] 8
(addr. to display)

I/O
OUTPUT Data REGISTER 7‐segment 
7‐segment 
(OUTD ) display  displays

Figure 1: Computer block diagram

The following sequence of steps (grouped in 3 sets – Display, Fetch and Execution) is repeated for
each instruction cycle, as long as Stop Register = 0:
Display
1. The address of the memory location to being displayed (specified by the DIP switches) is loaded
from register OUTA to register AR.
2. The content of memory location at this address is loaded into OUTD whose output is connected
to the 7-segment display. Steps 1 and 2 are always executed, even if the system is in halt.

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Fetch
3. The content of the Program Counter PC (containing at this point the address of the current
instruction) is loaded into AR (address register). PC determines the address of the memory
location from where the instruction is fetched (read) into the IR of the CPU. Since PC is reset to
0 whenever the UP2 board is programmed, your program’s first instruction has to be stored in
the first memory location (address 00).
4. PC is incremented to be prepared for getting the next instruction byte.
5. The first byte of the instruction (opcode) is fetched from memory and is stored in IR (instruction
register).
6. The IR content (instruction opcode) is decoded by the Instruction Decoder (in Control Unit).
7. If the instruction refers to a register, then skip to step 10.
8. If the instruction refers to memory, the PC content is transferred to AR, to get the second byte of
the instruction. This second byte of the instruction may contain
 either the address of the operand - if direct addressing mode; the instruction’s second byte (the
operand address) is read and directly loaded into AR;
 or the pointer to the operand address (i.e., address of the operand address) if indirect addressing;
This pointer is read from the memory location pointed by instruction’s 2nd byte and is loaded to
AR; then a newer read is performed to get the operand address and move it to AR.
The FETCH cycles conclude with AR carrying the operand address.
Execution
9. The data (operand) is read from the memory, and the PC is incremented to pointing to the next
instruction and being prepared for the next FETCH.
10. The EXECUTION cycles of the instruction are implemented, which requires typically several
more steps.
11. In the last cycle of the execution the SC is reset to 0, and the procedure begins again at step 1.
NOTE:
 Setting Stop Register = 1=> blocks incrementing PC and stops running further instructions.
These steps will be discussed in detail below.
 You will use a new type of file for memory initialization (.mif), to specify the contents of
memory; just go to “File” and open a “New” file which will display the list of file formats from
where you should select “Memory Initialisation File.” For this lab, the file .mif has to be named
memorycontents8.mif. To use hex numbers, you have to right-click on the Addr region and then
choose Hexadecimal for both Address and Memory (content) Radix. Save Every time you
change the contents of this file, you have to save and recompile your project.
 Every time you want to run the program that you loaded in the memory, you have to reprogram
your device.

4.3 Syntax of the computer instructions

The instructions that can be executed by the computer are shown in Table 1. The second most
significant bit (IR6) specifies if the instruction is a memory-reference instruction (IR6=0) or a register-
reference instruction (IR6=1). The msb (I = IR7) specifies the instruction addressing mode (direct or
indirect), while the other 6 bits form the opcode. For memory-reference instructions with direct
addressing mode another memory access is needed to read the operand, while two more memory read
cycles are needed to get the operand in case of indirect addressing. In conclusion,
 register-reference instructions are encoded with one byte: {opcode},
 memory-reference instructions employ a two byte format as follows:
o memory-reference instructions with direct addressing: {opcode, operand address}
o memory-reference instructions in indirect addressing: {opcode, address of the operand address}.
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Table 1: Computer Instructions List

Type of Binary opcodes = hex opcodes
Instruction Symbol Direct Addressing Indirect Addressing Description
I = IR7 = 0 I = IR7 = 1
AND 00 000001=01 10 000001=81 AND AC to memory word
ADD 00 000010=02 10 000010=82 Add a memory word to AC

Memory SUB 00 000011=03 10 000011=83 Subtract a memory word from AC

Reference LDA 00 000100=04 10 000100=84 Load AC from a memory location

(IR6 = 0) STA 00 001000=08 10 001000=88 Store AC to a memory location
BUN 00 010000=10 10 010000=90 Branch unconditionally
Increment content of memory location and skip the
ISZ 00 100000=20 10 100000=A0 following instruction if the incremented number is 0
CLA 01 000001=41 Clear AC
CMA 01 000010=42 Complement AC
Register ASL 01 000100=44 Arithmetic left shift AC
Reference ASR 01 001000=48 Arithmetic right shift AC
(IR6 = 1) INC 01 010000=50 Increment AC
Halt. A Stop bit is set to 1, which prevents PC
HLT 01 100000=60 from being incremented.
Now let us consider the following example file which presents a simple program in the memory
(in machine code and commented with assembly language):
% THE PROGRAM IS IN THE ADDRESS ZONE 00 - 7F %
00: 04; % LDA (direct) %
01: 80; % from address 80H; AC contains now the number 1AH %
02: 44; % ASL (direct); AC contains 34H now %
03: 02; % ADD (direct) %
04: 81; % add number of address 81H to AC; AC contains now 5FH%
05: 08; % STA (direct) %
06: a0; % AC sent to the address memory A0H %
07: 83; % SUB (indirect) %
08: 90; % @ address 90H is data pointer (82H); AC =5FH-65H =FAH %
09: 08; % STA (direct) %
0a: a1; % store AC to the address memory A1H %
0b: 60; % HLT %
% DATA ARE IN THE ADDRESS ZONE 80 to FF %
80: 1a;
81: 2b;
82: 65;
90: 82;
% address A0H is reserved for the addition result %
% address A1H is reserved for the subtraction result %
The hex number of the first column indicates the address in the memory, while the second hex
number indicates the instruction (opcode or operand’s address) represented in machine code. The
symbol % delimits the comments; these comments will contain the assembly language mnemonics of
opcode of the instructions at hand (assembly language representation).
From operating point of view, the memory space of our computer is divided in two: the first half
(00-7F) carries the code of your program, while the second half (80-FF) is dedicated to storing data
(initial operands and results).
(#00) The program starts at address 00, with memory –reference instruction LDA that loads the register
AC with a number which is stored at address 80H; this number is 1AH.
(#02) The second program line contains a register-reference instruction, ASL, which is executed in
only one reading cycle of memory. The AC contents are shifted to the left and become 34H.
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(#03) This instruction adds the number stored at address 81H to the AC, i.e., performs 34H+2BH= 5FH
(#05) Next instruction stores the sum obtained in AC at address A0H.
(#07) An indirect subtraction is performed here. Address 90H contains a pointer to the address 82H,
where the number to being subtracted (65H) is stored. The operation is then 5FH– 65H = 0FH;
(#9) The resulted difference 0FH (of AC) is stored at memory address A1H, and the program stops.
Choosing addresses A0H and A1H by DIP, the numbers 5FH and FAH, respectively, can be seen on
the 7-segment displays.

The .mif file which represents this program in machine code (bold characters of the above example) is
shown in fig. 2 as it is stored in the memory.

Figure 2: .mif file which represents the program in machine code

4.4 Detailed Description of the Control Functions (to be generated by the Control Unit)
Starting from Table 1, one can observe that there are three types of distinct instructions that are encoded
by the two most significant bits of the instruction register (IR):
1. X 0  IR 7 IR 6 indicates a direct memory-reference instruction;
2. X 1  IR 7 IR6 indicates a register-reference instruction
3. X 2  IR7 IR 6 indicates an indirect memory-reference instruction.
The seven memory-reference instructions can be discriminated by the following control signals (note
that X 0  X 2  IR 6 ), employing the one-hot encoding (LDA; STA; BUN; and ISZ) and partially binary
encoding (AND, ADD and SUB).
1. Y0  IR 6 IR1IR0 : AND;
2. Y1  IR 6 IR1 IR 0 : ADD;
3. Y2  IR 6 IR1IR0 : SUB;
4. Y3  IR 6 IR2 : LDA;
5. Y4  IR 6 IR3 : STA;
6. Y5  IR 6 IR4 : BUN; and
7. Y6  IR 6 IR5 : ISZ.
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These “designations” for Xi and Yj will be used in the following sections.

The following three tables detail the instruction cycles; you have to read and analyse these
tables attentively and make sure that you understand each step. These tables represent the specifications
for the design of the CPU Control Unit. The ALU functions are described in TABLE 5. Please note
that
 register-reference instructions require one memory read cycle (to get the opcode in T3),
 memory-reference instructions in direct addressing mode need three memory read cycles:
o 2 read cycles to fetch the instruction (one for the opcode in T3 and another one for the
operand address in T6), and
o a third cycle to get the operand in T8 to execute the instruction,
 memory-reference instructions in indirect addressing mode need four memory read cycles (3 read
cycles to fetch the instruction – the 1st cycle to read the opcode in T3, the 2nd cycle to read the
address of the operand address in T6, the 3rd to get the operand address in T7, and the 4th cycle to
get the operand in T8).
Table 2: Instruction Fetch Cycle (Initialisation) - common to all types of instruction
State Description Notation RTL
T0 Load the address register AR with the contents of OUTA T0: AR ← OUTA
T1 Read memory location pointed to by AR to the data output register OUTD T1: OUTD ← M [AR]
T2  Load AR register with the ADDRESS of the opcode of the current instruction (PC) T2: AR ← PC
 Increment PC (if the program is running, i.e., if Stop FF S = 0) to point to the address T2S’: PC ← PC + 1
of the next byte to be read, which can be:
o the next instruction, if the current instruction is a register-reference instruction
o the 2nd byte of the current instruction, if it is a memory-reference instruction.
T3 Read the instruction’s first byte (opcode) from memory location specified by AR to IR T3 : IR ← M [AR]
T4 This state is a delay that allows the opcode to be decoded in the Control Unit. (nothing)
T5 If X 1 , the byte in IR is a register - reference instruction and will be executed now T5X1: execute instruction from
Table 3
T5X1 :SC ← 0
If X 0 or X 2 ( memory - reference instruction),
 PC is copied to AR, i.e, the address of the instruction’s 2nd byte goes from PC to AR T5IR’6 : AR ← PC
=> now AR contains the ADDRESS of
o the operand address if direct addressing, or
o the address of the operand address if indirect addressing
 Increment PC if the program is running (Stop FF S=0). Note that  X 0  X 2   IR 6 . TsIR’6 S’: PC ← PC + 1

T6 Read from memory location pointed to by AR to AR; the read byte is T6IR’6 : AR ← M [AR]
 the operand address, if direct addressing, or
 the address of the operand address, if indirect addressing
T7 If indirect addressing, read the operand address from memory location pointed to by AR T7 X 2 : AR  M AR

If direct addressing, don’t do anything, as the operand’s address is already in AR since T7 X 0 : (nothing)
T6
T8 & after Execute the memory - reference instruction as described in Table 4. (see Table 4)

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Table 3: Instruction Execution Cycle - Control of the register - reference instructions

Symbol RTL Notation
CLA T5 X1IR0 : AC  0

CMA T5 X 1IR1 : AC  AC

ASL T5 X1IR2 : AC  ashl AC

ASR T5 X1IR3 : AC  ashr AC

INC T5 X1IR4 : AC  AC  1

HLT T5 X1IR5 : S  1

Table 4: Instruction Execution Cycle - Control of the memory - reference instructions

Symbol RTL Notation
T8Y0 : DR  M AR 
AND
T9Y0 : AC  AC  DR , SC  0
T8Y1 : DR  M AR 
ADD
T9Y1 : AC  AC  DR , SC  0
T8Y2 : DR  M AR 
SUB
T9Y2 : AC  AC  DR , SC  0
T8Y3 : DR  M AR 
LDA
T9Y3 : AC  DR , SC  0
T8 : (cycle not allocated to allow the address bus to stabilize)
STA
T9Y4 : M AR  AC , SC  0
BUN T8Y5 : PC  AR, SC  0
T8Y6 : DR  M AR 
ISZ (assuming that the next
T9Y6 : DR  DR  1
instruction is a memory-
reference instruction, stored at T10Y6 : M AR   DR
2 memory location further T11Y6 : si DR  0  alors S : PC  PC  1
down)
T12Y6 : si ( DR  0) alors S : PC  PC  1, SC  0

Table 5: ALU operations table

S2 S1 S0 Operation Description
0 0 0 AC + DR Addition
0 0 1 AC + DR’ + 1 Subtraction: AC - DR
0 1 0 ashl AC AC arithmetic left shift
0 1 1 ashr AC AC arithmetic right shift
1 0 0 AC  DR logic AND
1 0 1 AC  DR logic OR
1 1 0 DR DR transfer to AC
1 1 1 AC’ Complement AC

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To illustrate the computer’s operation, let’s track the registers contents as the following memory –
reference instruction is run:

00: ADD 80H

02: …

This translates into the machine code stored in the computer’s memory as follows

Addr Content
00: 02
01: 80
02: …

State PC AR IR DR AC SC+ RTL

T0 00 0 0 1
T1 00 0 0 2
T2
(PC) = 00 = ADDRESS of the opcode T2 : AR  PC
0 0 3
01 PC++ T2S : PC  PC  1
M[AR=0]
T3 01 00 = ADDRESS of the opcode = 02 0 0 4 T3 : IR  M AR 
=opcode
T4 01 0 0 5
nd
(PC) = 01 = ADDRESS of the 2 byte of the opcode= T5 IR 6 : AR  PC
T5 0 0 6
memory-reference instruction (operand address) 02 T5 IR6 S : PC  PC  1
02 PC++
M[AR=01] = 80 operand address as direct addressing opcode T6 IR6 : AR  M AR
T6 02 (not the address of the operand address 0 0 7
= 02
since it is not indirect addressing)
T7
02 * M[AR] = operand address if indirect addressing (not here) opcode 0 0 8
* still the operand address as direct addressing (read in T6) = 02 (nothing)
opcode M[AR=80] DR <- M[AR]
T8 02 operand address 0 9
= 02 = operand
0+ 0 AC <- AC+DR
T9 02 operand address operand SC <- 0

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5. Prelab - Hardware

5.1 Files Analysis

You will start up by analyzing the files .bdf which you are provided with. You can do it either by using
Quartus II, or by “deciphering” the diagrams at the end of this document (Fig. 3 - 11). You don’t have
to understand in detail the RAM operation (ram256x8), nor the controller of the 7-segment display.
The diagram of the 4 bit SC counter is not included in the figures below, because the counter has the
same architecture like the 8 bit counter, but truncated to 4 bits. Finally, the VHDL code of the bus
multiplexer is presented in Table 7. Although you did not learn VHDL yet, you will see that the code
is easy to understand, and much simpler to implement than would be a .bdf.

Examining the logic diagrams, answer the following questions and write your answers in your report:

1. Draw a diagram which shows the hierarchy of the files, with lab3top at the top. For the files
lab3controller, ram256x8, and sevensegcontroller, you do not have to identify the subfiles.
2. How can you check by analysing these files that only one register will place its output on the
data bus at a time?
3. Are the register reset (clear) signals synchronous or asynchronous? Explain your answer. Note
that all the command signals are active at high (i.e. a “1” will reset a register to 0).
4. What happens if a load and a reset are simultaneously sent to a register? Why?
5. Why the address register is connected directly to the memory?
6. Why the Program Counter, the Data Register, and the Accumulator are implemented as
counters?
7. Of all the three commands of the counters (reset, increment, and load), which one has the
highest priority? Which one has the lowest priority? Explain your answer.
8. Is it possible to read a value from memory directly to the accumulator? Explain your answer.
9. Analyze the ALU and determine a truth table which describes the 8 operations which can be
selected by the three control lines. Are the shift operations logical or arithmetic?

5.2 Design of the Control Unit

Your main objective is to derive the equations of all the control signals which have to be generated
by the Control Unit in order to control the CPU datapath (registers and ALU), the bus and the memory.
To this effect, analyze the RTL expressions of Table 2, Table 3, Table 4, and write the logic expression
for each of the following control signal ( and  functions of the Control Unit):
Memory (M(In, T)) 11. OUTD_Load
1. memwrite CPU ALU (ALU(In, T))
CPU registers (R(In, T)) 12. ALU_Sel2
2. AR_Load 13. ALU_Sel1
3. PC_Load 14. ALU_Sel0
4. PC_Inc Bus (data mux (Bus(In, T))
5. DR_Load 15. BusSel2
6. DR_Inc 16. BusSel1
7. IR_Load 17. BusSel0
8. AC_Clear Control Unit ((In, T))
9. AC_Load 18. SC_Clear
10. AC_Inc 19. Halt

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The inputs (In) of the Control Unit are: the Instruction Register IR [7..0], the Data Register DR [7..0],
the State Register (SC) T[12..0], and the stop command (Stop) of the Stop register. The Xi and Yj
functions (as described in section 4.3) are the core of the Instruction Decoder and have to be
implemented first, to allow for deriving all the control signal (CU’s  and  functions) from them.
To this effect, examine the tables and determine which signals must be activated to execute each
RTL line. For each control signal, derive a list of the conditions under which that signal is activate.
After making up the list for a particular signal, you can simply do an OR of each condition/term to
obtain the final expression of that control signal. For example, let consider the bus (multiplexer) for
which three select lines (BusSel [2..0]) have to be derived (Bus(In, T)). Let synthesize in a table all the
conditions under which each register places its output onto the bus:
Circuit which writes on Control Conditions Bus select = Bus(In, T)
the bus (In, T) BusSel2 BusSel1 BusSel1
T1
T3
Memory T6 IR 6 0 0 0
T7 X 2
T8 Y0  Y1  Y2  Y3  Y6 
AR T8Y5 0 0 1
T2
PC T5
0 1 0
DR T10Y6 0 1 1
IR (never happens here) 1 0 0
AC T9Y4 1 0 1
OUTA T0 1 1 0
(not used) (indifferent) 1 1 1
From this table, one can see that BusSel 2  T0  T9Y4 . Actually you have to design an encoder that
generates BusSel [2..0] in terms of the Control Conditions. Similar Boolean expressions have to be
derived for all the other control signals. To eliminate the dependence of the duration of the output
functions (In, T) and transition functions (In, T) to the input signals, every function is sampled and
stored in a buffer synchronously with the system clock.
It is worth to pay great attention when you derive your lists!

6. Procedure - Hardware

6.1 Build and test the Control Unit

6.1.1 Automatic run
1. Create a new Quartus II Project and name it appropriately with File -> New Project Wizard or
File->New->New Quartus II Project
Add support files (both .bdf and .vhd) to project: Project->Add/Remove Files from Project
Set lab3top.bdf as the top-level entity.
2. Open the file lab3controller.bdf (which gives the list of the pins of the inputs and outputs in the
order required for generating by default the same symbol as shown in the file lab3top.bdf). Use
AND, OR and NOT gates to implement the Boolean expressions that you derived in the prelab
for the control signals (section 5.3). It is a good idea to make virtual connections by giving
names to wires (simply click on a wire and enter the name; the wires which have the same

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names are automatically connected by the compiler). If you do not use virtual connections, your
file will quickly become an incomprehensible set of spaghetti. Try to reduce the number of
logic gates that a signal must go through. The clock period of the DE2-115 board is only 20 ns,
and errors can occur if signals are delayed over this period.
3. Create your Memory Initialization File (memorycontents8.mif): File->New->Memory
Initialization File; Select your radix etc... Hexadecimal. You can either put your test program
into the *.mif (like the one in Fig. 2) now or later. Save the file.
4. Set lab3controller.bdf as Top-Level Entity and make sure that it compiles without errors.
5. Assign lab3top.bdf to the project (set as Top-Level Entity), and choose the device
EP4CE115F29C7. Assign the pins as shown in Table 6. (right-click on pin -> Locate -> Locate
in Assignment Editor and then switch in the Category panel from All to Locations-Pins to select
the pin in the Edit panel, in the Location tab, etc…
Table 6: Pins Assignment
Pin Name Pin Number Component Pin Name Pin Number Component
clk PIN_Y2 50MHz clock A1 PIN_G18 HEX0[0]
Auto PIN_Y23 SW[17] B1 PIN_F22 HEX0[1]
DIP7 PIN_AB26 SW[7] C1 PIN_E17 HEX0[2]
DIP6 PIN_AD26 SW[6] D1 PIN_L26 HEX0[3]
DIP5 PIN_AC26 SW[5] E1 PIN_L25 HEX0[4]
DIP4 PIN_AB27 SW[4] F1 PIN_J22 HEX0[5]
DIP3 PIN_AD27 SW[3] G1 PIN_H22 HEX0[6]
DIP2 PIN_AC27 SW[2] A2 PIN_M24 HEX1[0]
DIP1 PIN_AC28 SW[1] B2 PIN_Y22 HEX1[1]
DIP0 PIN_AB28 SW[0] C2 PIN_W21 HEX1[2]
1_instruction PIN_M23 KEY[0] D2 PIN_W22 HEX1[3]
AR[0] PIN_G19 LEDR[0] E2 PIN_W25 HEX1[4]
AR[1] PIN_F19 LEDR[1] F2 PIN_U23 HEX1[5]
AR[2] PIN_E19 LEDR[2] G2 PIN_U24 HEX1[6]
AR[3] PIN_F21 LEDR[3] AC[0] PIN_E21 LEDG[0]
AR[4] PIN_F18 LEDR[4] AC[1] PIN_E22 LEDG[1]
AR[5] PIN_E18 LEDR[5] AC[2] PIN_E25 LEDG[2]
AR[6] PIN_J19 LEDR[6] AC[3] PIN_E24 LEDG[3]
AR[7] PIN_H19 LEDR[7] AC[4] PIN_H21 LEDG[4]
DR[0] PIN_J15 LEDR[10] AC[5] PIN_G20 LEDG[5]
DR[1] PIN_H16 LEDR[11] AC[6] PIN_G22 LEDG[6]
DR[2] PIN_J16 LEDR[12] AC[7] PIN_G21 LEDG[7]
DR[3] PIN_H17 LEDR[13] Stop PIN_F17 LEDG[8]
DR[4] PIN_F15 LEDR[14]
DR[5] PIN_G15 LEDR[15]
DR[6] PIN_G16 LEDR[16]
DR[7] PIN_H15 LEDR[17]
Compile your project.

6. To test and visualise the simulation of your project, create a new .vwf file called lab3top.vwf.
Choose a grid size of 20 ns and an end of simulation of 5μs. Make a right click and select
“Insert” then “Insert Node or Bus…” and then click on “node finder” and on “List” selecting
Pins: all for Filter, and Named “*”. In the panel Nodes Found select clk, DIP [7..0], etc.
7. Set the DIP switches to point to the A0 address. Also make sure the Auto signal is set to 1. Start
simulation. If your Control Unit functions correctly, the register OUTD would have at the end

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CEG 2136 Lab 4

the value 5F, and the Stop bit should be activated after approximately 2.7 μs. If you start again
your simulation with DIP [7..0] set to A1, the register OUTD should finally contain FA. Show
this simulation to your TA.

6.1.2 Manual run

8. If your simulation does not function, you have to find the source of the problem. Run short test
programs (a couple of instructions) to verify the correct generation of the control signals. To
help debug the issue, set the Auto signal to 0. Setting the Auto signal to 0 enables you to step-
through the instructions (a push-button press 1_instruction, permits the user to execute the next
instruction) and see where the issue is. In addition, the outputs to the following registers are
displayed as well: AR, DR and the Accumulator.
Check the sequence of the control signals to see whether they correspond to the order described
in tables 2 - 4. Keep in mind that the signals arrive one clock cycle after the sequence counter,
as they are stored first in the control registers. Another good technique of checking is to observe
what is stored in the memory. Examine the signals on the data and address buses each time the
signal memwrite is requested; this should help you to find out where your program causes an
error.
9. Program the DE2-115 board by opening the programmer and choose “Program”. Use the DIP
switches to choose the addresses for the data.
10. Enter the program of Section 4.3 in memorycontents8.mif. Program the device and use the DIP
switches to read the memory content. Was your analysis of the program correct? Demonstrate
to your TA.

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CEG 2136 Lab 4

7. Prelab - Software

7.1 Program Analysis

1. Analyze the following program. Examine the instructions one by one, inspecting the values
from the AC and the memory to understand what the program does.
2. Write a simple pseudo code to describe the program. Give the following names to the variables
stored at the memory addresses A0 - A3 (hex):
Address Name of variable
A0 Counter
A1 X
A2 Y Note that X, Y and Z are pointers.
A3 Z
3. What does calculate this program?
4. Why is practical to use in this program memory - reference instructions with indirect addressing
(in other words, instructions which use pointers)?
% PROGRAM IS IN the RANGE Of ADDRESSES 00 TO 7F %
00: 04; % LDA (direct) %
01: a0; % from address a0 %
02: 42; % CMA %
03: 08; % STA (direct) %
04: a0; % AC to address a0 %
05: 20; % ISZ (direct) %
06: a0; % counter stored at a0 %
07: 10; % BUN (direct) %
08: 20; % to address 20 %
09: 60; % HLT %
20: 84; % LDA (indirect) %
21: a1; % the number pointed to by the memory location a1 %
22: 82; % ADD (indirect) %
23: a2; % the number pointed to by the memory location a2 %
24: 88; % STA (indirect) %
25: a3; % to the memory location pointed to by a3 %
26: 04; % LDA (direct) %
27: a1; % from the address a1 %
28: 50; % Inc %
29: 08; % STA (direct) %
2a: a1; % AC to the memory address a1 %
2b: 50; % Inc %
2c: 08; % STA (direct) %
2d: a2; % store AC to the memory address a2 %
2e: 50; % Inc %
2f: 08; % STA (direct) %
30: a3; % send AC to the memory address a3 %
31: 10; % BUN (direct) %
32: 05; % to the memory address 05 %
80: 01; % DATA ARE FOUND AT ADDRESSES 80 TO FF %
81: 01;
a0: 0a; % loop counter, which will be done 10 times %
a1: 80; % pointer to the first number to be added %
a2: 81; % pointer to the second number to be added %
a3: 82; % pointer to memory location where result will be stored %

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CEG 2136 Lab 4

7.2 Program Design

1. Write a program which adds consecutively each number of the following sequence of hexadecimal
numbers: 21, B5, 37, 08, 5C, 84, A1, 1D, 72, FF, F6, 43, 03, A9, D4, 19, 31, D9, 47, 82, 14, 52, 07,
CA, 04. When your current sum becomes equal to zero, your program should store into the memory
the last number added, display this number, and eventually stop. Write the program in machine
code in .mif file format, as shown in section 4.2.3.
2. (bonus *) Write a program which can multiply any unsigned number of 4 bits.
It is important to understand how instruction ISZ operates. Let us assume that you want to skip the
following instruction if the number of address B0 is equal to FF (hex). Note that FF corresponds to
11111111 (in binary), which is also the complement with 2 of - 1 (in decimal). In this case, instruction
ISZ B0 will read the number FF, to put it in the data register, and increment to 00. Since the data
register is now equal to 0, the next instruction will be skipped. If any other value that FF is at the
address B0, then the next instruction will be executed.
Note that if you want to skip the following instruction when the number stored at the address B0
is equal to 00, you need to initially complement it to FF so that condition ISZ is met. This can be done
without losing the data of B0 by using the sequence of instructions LDA B0; CMA; STA B1; ISZ B1.
It is assumed that B1 is an address which is available for a temporary variable.

8. Procedure - Software
6.2 Test your programs
Enter the programs which you wrote at section 7 in memorycontents8.mif (one by one,
obviously). Use the simulator to debug your program; it is possible that you need simulations
which extend up to 50 - 100 μs. Once you are sure that your programs function, configure the
DE2-115 with those programs. Use the DIP switches and the 7-segment displays, and make
sure that the programs operate as expected. Show your simulations, and show a
demonstration to your TA.

9. Report
Besides the answers to your prelab section, you must include the following in your report:
1. a block diagram of the Control Unit that you conceived; and
2. copies of the .scf simulation files, for:
a. the addition and subtraction program of section 4.3, and
b. the sums (and multiplication if done) of section 5.4.
A TA will check that your design and your programs function both in simulation and on the UP2
board before you leave the lab. Be prepared to answer questions about the lab when you demo it.

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CEG 2136 Lab 4

Figure 3: lab3top.bdf

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CEG 2136 Lab 4
DFF DFF DFF
memw rite_in PRN memw rite DR_Inc_in PRN DR_Inc BusSel0_in PRN BusSel0
D Q D Q D Q

CLRN CLRN CLRN

1 102 128

DFF DFF DFF

AR_Load_in PRN AR_Load AC_Inc_in PRN AC_Inc SC_Clear_in PRN SC_Clear
D Q D Q D Q

CLRN CLRN CLRN

2 99 133

DFF DFF DFF

PC_Load_in PRN PC_Load OUTD_Load_in PRN OUTD_Load Halt_in PRN Halt
D Q D Q D Q

CLRN CLRN CLRN

3 96 134

DFF DFF
PC_Inc_in PRN PC_Inc ALU_Sel2_in PRN ALU_Sel2
D Q D Q

CLRN CLRN
4 93
INPUT memw rite_in memw rite OUTPUT
17 memw rite_in GND 9 memw rite
INPUT AR_Load_in AR_Load OUTPUT
18 AR_Load_in GND 10 AR_Load
INPUT PC_Load_in PC_Load OUTPUT
19 PC_Load_in GND DFF DFF 11 PC_Load
INPUT PC_Inc_in PC_Inc OUTPUT
20 PC_Inc_in GND DR_Load_in PRN DR_Load ALU_Sel1_in PRN ALU_Sel1 12 PC_Inc
INPUT DR_Load_in D Q D Q DR_Load OUTPUT
21 DR_Load_in GND 13 DR_Load
INPUT DR_Inc_in DR_Inc OUTPUT
22 DR_Inc_in GND 14 DR_Inc
INPUT IR_Load_in IR_Load OUTPUT
23 IR_Load_in GND
CLRN CLRN
15 IR_Load
INPUT AC_Clear_in 5 91 AC_Clear OUTPUT
24 AC_Clear_in GND 16 AC_Clear
INPUT AC_Load_in AC_Load OUTPUT
103AC_Load_in GND 104 AC_Load
INPUT AC_Inc_in AC_Inc OUTPUT
100 AC_Inc_in GND 101 AC_Inc
INPUT OUTD_Load_in DFF DFF OUTD_Load OUTPUT
OUTD_Load_in
97 GND 98 OUTD_Load
INPUT ALU_Sel2_in IR_Load_in PRN IR_Load ALU_Sel0_in PRN ALU_Sel0 ALU_Sel2 OUTPUT
94ALU_Sel2_in GND D Q D Q 95 ALU_Sel2
INPUT ALU_Sel1_in ALU_Sel1 OUTPUT
90ALU_Sel1_in GND 92 ALU_Sel1
INPUT ALU_Sel0_in ALU_Sel0 OUTPUT
87ALU_Sel0_in GND 89 ALU_Sel0
BusSel2_in CLRN CLRN BusSel2
INPUT OUTPUT
85 BusSel2_in GND 6 88 86 BusSel2
INPUT BusSel1_in BusSel1 OUTPUT
82 BusSel1_in GND 83 BusSel1
INPUT BusSel0_in BusSel0 OUTPUT
129 BusSel0_in GND 130 BusSel0
INPUT SC_Clear_in SC_Clear OUTPUT
131SC_Clear_in GND DFF DFF 135 SC_Clear
INPUT Halt_in Halt OUTPUT
132 Halt_in GND AC_Clear_in PRN AC_Clear BusSel2_in PRN BusSel2 136 Halt
D Q D Q

CLRN CLRN
7 84

DFF DFF
AC_Load_in PRN AC_Load BusSel1_in PRN BusSel1
D Q D Q

CLRN CLRN
8 81

INPUT
25 clk GND

INPUT
26 CLRN VCC

Figure 4: controlregister.bdf
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CEG 2136 Lab 4

INPUT
8 Clear VCC
NOT AND2 counter1bit counter1bit
Clear Clear
INPUT 14 q0 q4
9 Load VCC 16 Increment_In Out Increment_In Out
AND3 Load Increment_Out Load Increment_Out
NOT
d0 d4
In In
15 17
clk clk
INPUT
10 Increment VCC
49 50

counter1bit counter1bit
Clear Clear
q1 q5
Increment_In Out Increment_In Out

Load Increment_Out Load Increment_Out

d1 d5
In In

clk clk

48 51

counter1bit counter1bit
Clear Clear
q2 q6
Increment_In Out Increment_In Out

Load Increment_Out Load Increment_Out

d2 d6
In In

clk clk

47 52

q[7..0] OUTPUT
18 q[7..0]

INPUT d[7..0]
11 d[7..0] VCC counter1bit counter1bit
Clear Clear
q3 q7
Increment_In Out Increment_In Out

Load Increment_Out Load Increment_Out

d3 d7
In In

clk clk

46 53

INPUT
12 clk VCC

Figure 5: counter8bits.bdf

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CEG 2136 Lab 4 Page 18of 21

register1bit
Clear
q7
Load Q
d7
D

clk

30

register1bit
Clear
q6
Load Q
d6
D

clk

29

register1bit
Clear
q5
Load Q
d5
D

clk

28

register1bit
Clear
q4
Load Q
d4
D

clk

27

INPUT d[7..0] q[7..0] OUTPUT

14 d[7..0] VCC 13 q[7..0]
register1bit
Clear
q3
Load Q
d3
D

clk

26

register1bit
Clear
q2
Load Q
d2
D

clk

25

register1bit
Clear
q1
Load Q
d1
D

clk

24

register1bit
Clear
q0
Load Q
d0
D

clk

23

INPUT
9 Clear VCC
INPUT
10 Load VCC
INPUT
11 clk VCC

Figure 6: register8bits.bdf
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 CEG 2136 Lab 4 Page 19of 21

INPUT
4 Sel2 VCC
INPUT
5 Sel1 VCC Sum[7..0] OUTPUT
INPUT 17 Sum[7..0]
6 Sel0 VCC

INPUT AC[7..0]
7 AC[7..0] VCC alu1bit alu1bit
INPUT DR[7..0]
8 DR[7..0] VCC
Sel2 Sel2

Sel1 Sel1
Sum0 Sum4
Sel0 Sum Sel0 Sum
AC0 CP0N AC4 CP4N
X CarryProp_N X CarryProp_N
DR0 CG0N DR4 CG4N
Y CarryGen_N Y CarryGen_N
C4
Carry_in Carry_in
AC3
Xleftshift Xleftshift
AC1 AC5
Xrightshift Xrightshift

9 16
GND
20

alu1bit alu1bit
Sel2 Sel2

Sel1 Sel1
Sum1 Sum5
Sel0 Sum Sel0 Sum
AC1 CP1N AC5 CP5N
X CarryProp_N X CarryProp_N
DR1 CG1N DR5 CG5N
Y CarryGen_N Y CarryGen_N
C1 C5
Carry_in Carry_in
AC0 AC4
Xleftshift Xleftshift
AC2 AC6
Xrightshift Xrightshift

10 15

alu1bit alu1bit
Sel2 Sel2

Sel1 Sel1
Sum2 Sum6
Sel0 Sum Sel0 Sum
AC2 CP2N AC6 CP6N
X CarryProp_N X CarryProp_N
DR2 CG2N DR6 CG6N
Y CarryGen_N Y CarryGen_N
C2 C6
Carry_in Carry_in
AC1 AC5
Xleftshift Xleftshift
AC3 AC7
Xrightshift Xrightshift

11 14

alu1bit alu1bit
Sel2 Sel2

Sel1 Sel1
Sum3 Sum7
Sel0 Sum Sel0 Sum
AC3 CP3N AC7 CP7N
X CarryProp_N X CarryProp_N
DR3 CG3N DR7 CG7N
Y CarryGen_N Y CarryGen_N
C3 C7
Carry_in Carry_in
AC2 AC6
Xleftshift Xleftshift
AC4
Xrightshift Xrightshift

12 13

2 21
CARRY GEN. CARRY GEN.
C4
CI CI
CG0N CG4N
GN0 GN0
CG1N C1 CG5N C5
GN1 CX GN1 CX
CG2N C2 CG6N C6
GN2 CY GN2 CY
CG3N C3 CG7N C7
GN3 CZ AND2 GN3 CZ
CP0N CP4N
PN0 GN NOT PN0 GN
CP1N CP5N
PN1 PN 22 OR2 PN1 PN
CP2N 24 CP6N
PN2 NOT C4 PN2
CP3N CP7N
PN3 23 PN3
25
74182 74182

Figure 7: alu8bits.bdf

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 CEG 2136 Lab 4 Page 20of 21

AND3
NOT
INPUT
12 Clear VCC VCC
17 16 4
NOT OR2 DFF
PRN OUTPUT
18 D Q 3 Q
INPUT 14
9 Load VCC AND3

CLRN
INPUT
8 D VCC 13 1
11
INPUT VCC
2 clk VCC

Figure 8: register1bit.bdf
INPUT
4 Clear VCC
INPUT
6 Increment_In VCC
INPUT
5 Load VCC
VCC
2
OR2 JKFF
AND2
PRN OUTPUT
J Q 20 Out
INPUT 11
7 In VCC 14 OR3
AND2 K
CLRN
NOT
10 1 AND2
12 17
13 VCC OUTPUT
16 Increment_Out
15

INPUT
8 clk VCC

Figure 9: counter1bit.bdf
INPUT
2 Sel2 VCC
INPUT
3 Sel1 VCC
INPUT
4 Sel0 VCC

INPUT
7 X VCC

INPUT 81mux
8 Y VCC XOR partialadder1bit
A
X_in Sum_out
B
18 Y_in P_outN
INPUT C
9 Carry_in VCC
Carry_in G_outN
D0
21
D1
INPUT OUTPUT
10 Xleftshift VCC D2 Y 6 Sum
INPUT
11 Xrightshift VCC D3 WN
D4
AND2 D5
D6
13 D7
OR2 GN
1 MULTIPLEXER
14
GND
5

NOT
OUTPUT
12 CarryProp_N
16 OUTPUT
20 CarryGen_N

Figure 10: alu1bit.bdf

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 CEG 2136 Lab 4 Page 21of 21

XOR
INPUT XOR
4 X_in VCC
INPUT OUTPUT
8 Y_in VCC 1 5 Sum_out
6

INPUT
9 Carry_in VCC NOT
OUTPUT
12 P_outN
NAND2 14

OUTPUT
11 G_outN
13

Figure 11: partialadder1bit.bdf

Table 6: VHDL Code for the bus multiplexer

LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Title "Bus multiplexer";
-- File: busmux.vhd
ENTITY busmultiplexer IS
PORT ( Sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
D0 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D1 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D3 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D4 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D5 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D6 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
D7 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END busmultiplexer;

ARCHITECTURE busmuxarch OF busmultiplexer IS

BEGIN
Y <= D0 WHEN Sel = "000" ELSE
D1 WHEN Sel = "001" ELSE
D2 WHEN Sel = "010" ELSE
D3 WHEN Sel = "011" ELSE
D4 WHEN Sel = "100" ELSE
D5 WHEN Sel = "101" ELSE
D6 WHEN Sel = "110" ELSE
D7;
END busmuxarch;

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University of Ottawa CEG2136: Computer Architecture I