AN1330

Application note

Designing with the L5970D 1A high efficiency DC-DC converter

Introduction
The L5970D is a step-down monolithic power switching regulator capable of delivering up to
1 A at output voltages from 1.235 V to 35 V. The operating input voltage ranges from 4.4 V to
36 V. It has been designed using BCDV technology and the power switching element is
implemented through a P-channel DMOS transistor. It does not require a bootstrap
capacitor, and the duty cycle can range up to 100%. An internal oscillator fixes the switching
frequency at 250 kHz. This minimizes the LC output filter.
A synchronization pin is available for cases where a higher frequency (up to 500 kHz) is
required. Pulse-by-pulse and frequency foldback overcurrent protection offer effective short
circuit protection. Other features are voltage feed-forward, protection against feedback
disconnection, inhibit and thermal shutdown.

Figure 1. Demonstration board

L5970D (SO-8) board dimensions: 23 x 20 mm

Figure 2. Package Figure 3. Pin connection

OUT 1 8 VCC
SYNC 2 7 GND
INH 3 6 VREF
COMP 4 5 FB
SO-8
AM00004v1

May 2008 Rev 3 1/31

www.st.com
Contents AN1330

Contents

1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Oscillator and synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 PWM comparator and power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.7 Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/31
AN1330 Contents

6.1 Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.2 Buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 Compensation network with MLCC (multiple layer ceramic capacitor) at

the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 External SOFT_START network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31
List of figures AN1330

List of figures

Figure 1. Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 3. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 4. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Internal regulator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Current limitation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Driving circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Error amplifier equivalent circuit and compensation network . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Module plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Phase plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Short-circuit current (VIN = 25 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Short-circuit current (VIN = 30 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. PCB layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. PCB layout (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. PCB layout (front side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. Junction temperature vs. output current (VCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 21. Junction temperature vs. output current (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22. Junction temperature vs. output current (VCC = 24 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 23. Efficiency vs. output current (VCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24. Junction temperature vs. output current (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26. Buck-boost regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. Dual output voltage with auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 28. Synchronization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 29. MLCC compensation network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 30. Soft start network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/31
AN1330 Pin functions

1 Pin functions

1.1 Pin description

Table 1. Pin description
N. Name Description

1 OUT Regulator output

Master/slave synchronization. When open, a signal synchronous with the turn-OFF of
the internal power is present. When connected to an external signal at a frequency
2 SYNC higher than the internal one, then the device is synchronized by the external signal.
Connecting the SYNC pins of two devices, the one with the higher frequency works as
master and the other one works as slave.
A logical signal (active high) disables the device. With an IHN higher than 2.2 V the
device is OFF and with an INH lower than 0.8 V, the device is ON.
3 INH
If INH is not used the pin must be grounded. When it is open, an internal pull-up
disables the device.
4 COMP E/A output to be used for frequency compensation
Step-down feedback input. Connecting the output voltage directly to this pin results in
an output voltage of 1.235 V. An external resistor divider is required for higher output
5 FB
voltages (the typical value for the resistor connected between this pin and ground is
4.7 k).
6 VREF Reference voltage of 3.3 V. No filter capacitor is needed for stability
7 GND Ground
8 VCC Unregulated DC input voltage.

1.2 Block diagram

Figure 4. Block diagram
VCC

VOLTAGES
TRIMMING
MONITOR
VREF
SUPPLY VREF
BUFFER
THERMAL
SHUTDOWN 1.235V 3.5V
INH INHIBIT
PEAK TO PEAK
COMP CURRENT LIMIT

E/A
FB - PWM
+ D Q
+
1.235V - Ck DRIVER
LPDMOS
POWER
FREQUENCY
SYNC OSCILLATOR
SHIFTER

GND OUT AM00003v1

5/31
Functional description AN1330

2 Functional description

The main internal blocks are shown in the device block diagram in Figure 4. They are:
● A voltage regulator supplying the internal circuitry. From this regulator, a 3.3 V
reference voltage is externally available.
● A voltage monitor circuit which checks the input and internal voltages.
● A fully integrated sawtooth oscillator with a frequency of 250 kHz ±15%, including also
the voltage feed forward function and an input/output synchronization pin.
● Two embedded current limitation circuits which control the current that flows through
the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle
by cycle if the current reaches an internal threshold, while the frequency shifter reduces
the switching frequency in order to significantly reduce the duty cycle.
● A transconductance error amplifier.
● A pulse width modulation (PWM) comparator and the relative logic circuitry necessary
to drive the internal power.
● A high side driver for the internal P-MOS switch.
● An inhibit block for standby operation.
● A circuit to implement the thermal protection function.

2.1 Power supply and voltage reference

The internal regulator circuit (shown in Figure 5) consists of a start-up circuit, an internal
voltage Preregulator, the Bandgap voltage reference and the Bias block that provides
current to all the blocks. The Starter gives the start-up currents to the entire device when the
input voltage goes high and the device is enabled (inhibit pin connected to ground). The
Preregulator block supplies the Bandgap cell with a preregulated voltage VREG that has a
very low supply voltage noise sensitivity.

2.2 Voltages monitor

An internal block continuously senses the VCC, VREF and VBG. If the voltages go higher than
their thresholds, the regulator begins operating. There is also a hysteresis on the VCC
(UVLO).

6/31
AN1330 Functional description

Figure 5. Internal regulator circuit

VCC

STARTER PREREGULATOR

VREG

BANDGAP

IC BIAS

VREF
AM00006v1

2.3 Oscillator and synchronizer

Figure 6 shows the block diagram of the oscillator circuit.
The Clock Generator provides the switching frequency of the device, which is internally fixed
at 250 kHz. The Frequency Shifter block acts to reduce the switching frequency in case of
strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry
and is the input of the Ramp Generator and synchronizer blocks.
The Ramp Generator circuit provides the sawtooth signal, used for PWM control and the
internal voltage feed-forward, while the synchronization circuit generates the
synchronization signal. The device also has a synchronization pin which can works both as
Master and Slave.
As Master, it serves to synchronize external devices to the internal switching frequency, and
as Slave to synchronize itself using an external signal up to 500 kHz.
In particular, when connecting together two devices the one with the lower switching
frequency works as Slave and the other as Master.
To synchronize the device, the SYNC pin must pass from a low level to a level higher than
the synchronization threshold with a duty cycle that can vary from approximately 10% to
90%, depending also on the signal frequency and amplitude.
The frequency of the synchronization signal must be, at a minimum, higher than the internal
switching frequency of the device (250 kHz).

7/31
Functional description AN1330

Figure 6. Oscillator circuit block diagram

FREQUENCY
FREQUENCY
SHIFTER
SHIFTER CLOCK
t

Ibias_osc

CLOCK
CLOCK RAMP
RAMP
GENERATOR
GENERATOR GENERATOR
GENERATOR RAMP

SYNCHRONIZATOR
SYNCHRONIZER
SYNC
AM00007v1

2.4 Current protection

The L5970D has two types of current limit protection: pulse-by-pulse and frequency
foldback.
The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in
Figure 7. The output power PDMOS transistor is split into two parallel PDMOS transistors.
The smallest one includes a resistor in series, RSENSE. The current is sensed through
RSENSE and if reaches the threshold, the mirror becomes unbalanced and the PDMOS is
switched off until the next falling edge of the internal clock pulse. Due to this reduction of the
ON time, the output voltage decreases. Since the minimum switch ON time (necessary to
avoid a false overcurrent signal) is too short to obtain a sufficiently low duty cycle at 250
kHz, the output current, in strong overcurrent or short circuit conditions, could increase
again. For this reason the switching frequency is also reduced, thus keeping the inductor
current under its maximum threshold. The Frequency Shifter (Figure 6) functions based on
the feedback voltage. As the feedback voltage decreases (due to the reduced duty cycle),
the switching frequency decreases also.

Figure 7. Current limitation circuitry

VCC

RSENSE RTH
IOFF

DRIVER
A1 A2 IL

OUT
A1/A2=95
I I NOT

PWM

AM00008v1

2.5 Error amplifier

The voltage error amplifier is the core of the loop regulation. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage

8/31
AN1330 Functional description

reference (1.235 V), while the inverting input (FB) is connected to the external divider or
directly to the output voltage. The output (COMP) is connected to the external compensation
network. The uncompensated error amplifier has the following characteristics:

Table 2. Uncompensated error amplifier characteristics

Description Values

Transconductance 2300 µS
Low frequency gain 65 dB
Minimum sink/source voltage 1500 µA/300 µA
Output voltage swing 0.4 V/3.65 V
Input bias current 2.5 µA

The error amplifier output is compared with the oscillator sawtooth to perform PWM control.

2.6 PWM comparator and power stage

This block compares the oscillator sawtooth and the error amplifier output signals
generating the PWM signal for the driving stage.
The power stage is a highly critical block, as it functions to guarantee a correct turn ON and
turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise
time of the current at turn ON, is a very critical parameter. At a first approach, it appears that
the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by
the recovery time of the recirculation diode.
In fact, when the current of the power element is equal to the inductor current, the diode
turns OFF and the drain of the power is able to go high. But during its recovery time, the
diode can be considered a high value capacitor and this produces a very high peak current,
responsible of many problems:
● Spikes on the device supply voltage that cause oscillations (and thus noise) due to the
board parasitics
● Turn ON overcurrent leads to a decrease in the efficiency and system reliability
● Major EMI problems
● Shorter freewheeling diode life
The fall time of the current during the turn OFF is also critical, as it produces voltage spikes
(due to the parasitic elements of the board) that increase the voltage drop across the
PDMOS.
In order to minimize these problems, a new driving circuit topology has been used and the
block diagram is shown in Figure 8. The basic idea is to change the current levels used to
turn the power switch ON and OFF, based on the PDMOS and the gate clamp status.
This circuitry allows the power switch to be turned OFF and ON quickly and addresses the
freewheeling diode recovery time problem. The gate clamp is necessary to avoid that VGS of
the internal switch goes higher than VGSmax. The ON/OFF Control block protects against
any cross conduction between the supply line and ground.

9/31
Functional description AN1330

Figure 8. Driving circuitry

VCC

Vgsmax

IOFF

CLAMP GATE
PDMOS
VOUT
DRAIN
L
STOP
ON/OFF OFF
ILOAD
DRIVE CONTROL ESR

ON
DRAIN
C
ION

AM00009v1

2.7 Inhibit function

The inhibit feature is used to put the device in standby mode. With the INH pin higher than
2.2 V the device is disabled and the power consumption is reduced to less than 100 µA.
With the INH pin lower than 0.8 V, the device is enabled. If the INH pin is left floating, an
internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also VCC compatible.

2.8 Thermal shutdown

The shutdown block generates a signal that turns OFF the power stage if the temperature of
the chip goes higher than a fixed internal threshold (150 °C). The sensing element of the
chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A
hysteresis of approximately 20 °C avoids that the devices turns ON and OFF continuously.

10/31
AN1330 Additional features and protection

3 Additional features and protection

3.1 Feedback disconnection

If the feedback is disconnected, the duty cycle increases towards the maximum allowed
value, bringing the output voltage close to the input supply. This condition could destroy the
load.
To avoid this hazardous condition, the device is turned OFF if the feedback pin is left
floating.

3.2 Output overvoltage protection

Overvoltage protection, or OVP, is achieved by using an internal comparator connected to
the feedback, which turns OFF the power stage when the OVP threshold is reached. This
threshold is typically 30% higher than the feedback voltage.
When a voltage divider is required to adjust the output voltage (Figure 14), the OVP
intervention will be set at:

Equation 1
R1 + R2
V OVP = 1.3 • ---------------------- • V FB
R2

Where R1 is the resistor connected between the output voltage and the feedback pin, and
R2 is between the feedback pin and ground.

3.3 Zero load

Due to the fact that the internal power is a PDMOS, no bootstrap capacitor is required and
so the device works properly even with no load at the output. In this condition it works in
burst mode, with random burst repetition rate.

11/31
Closing the loop AN1330

4 Closing the loop

Figure 9. Block diagram of the loop

4.1 Error amplifier and compensation network

The output L-C filter of a step-down converter contributes with 180 degrees phase shift in
the control loop. For this reason a compensation network between the COMP pin and
GROUND is added. The simplest compensation network together with the equivalent circuit
of the error amplifier are shown in Figure 10. RC and CC introduce a pole and a zero in the
open loop gain. CP does not significantly affect system stability but it is useful to reduce the
noise of the COMP pin.
The transfer function of the error amplifier and its compensation network is:

Equation 2
A V0 • ( 1 + s • R c • C c )
A 0 ( s ) = ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2
s • R0 • ( C0 + Cp ) • Rc • Cc + s • ( R0 • Cc + R0 • ( C0 + Cp ) + Rc • Cc ) + 1

Where Avo = Gm · Ro

12/31
AN1330 Closing the loop

Figure 10. Error amplifier equivalent circuit and compensation network

The poles of this transfer function are (if Cc >> C0+CP):

Equation 3
1
F P1 = -------------------------------------
2 • π • R0 • Cc

Equation 4
1
F P2 = --------------------------------------------------------
2 • π • Rc • ( C0 + Cp )

where the zero is defined as:

Equation 5
1
F Z1 = -------------------------------------
2 • π • Rc • Cc

FP1 is the low frequency which sets the bandwidth, while the zero FZ1 is usually put near to
the frequency of the double pole of the L-C filter (see below). FP2 is usually at a very high
frequency.

4.2 LC filter
The transfer function of the L-C filter is given by:

Equation 6
R LOAD • ( 1 + ESR • C OUT • s )
A LC ( s ) = ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2
s • L • C OUT • ( ESR + R LOAD ) + s • ( ESR • C OUT • R LOAD + L ) + R LOAD

where RLOAD is defined as the ratio between VOUT and IOUT.

If RLOAD>>ESR, the previous expression of ALC can be simplified and becomes:

13/31
Closing the loop AN1330

Equation 7
1 + ESR • C OUT • s
A LC ( s ) = ---------------------------------------------------------------------------------------------
-
2
L • C OUT • s + ESR • C OUT • s + 1

The zero of this transfer function is given by:

Equation 8
1
F O = ---------------------------------------------------
-
2 • π • ESR • C OUT

F0 is the zero introduced by the ESR of the output capacitor and it is very important to
increase the phase margin of the loop.
The poles of the transfer function can be calculated through the following expression:

Equation 9
2
– ESR • C OUT ± ( ESR • C OUT ) – 4 • L • C OUT
F PLC1, 2 = ------------------------------------------------------------------------------------------------------------------------------------------
2 • L • C OUT

In the denominator of ALC the typical second order system equation can be recognized:

Equation 10
2 2
s + 2 • δ • ωn • s + ω n

If the damping coefficient δ is very close to zero, the roots of the equation become a double
root whose value is ω n.
Similarly, for ALC the poles can usually be defined as a double pole whose value is:

Equation 11
1
F PLC = ---------------------------------------------
-
2 • π • L • C OUT

4.3 PWM comparator

The PWM gain is given by the following formula:

Equation 12
V cc
G PWM ( s ) = -------------------------------------------------------------
( V OSCMAX – V OSCMIN )

where VOSCMAX is the maximum value of a sawtooth waveform and VOSCMIN is the
minimum value. A voltage feed forward is implemented to ensure a constant GPWM. This is
obtained by generating a sawtooth waveform directly proportional to the input voltage VCC.

Equation 13
V OSCMAX – V OSCMIN = K • V CC

Where K is equal to 0.076. Therefore the PWM gain is also equal to:

Equation 14
1
G PWM ( s ) = ---- = const
K

14/31
AN1330 Closing the loop

This means that even if the input voltage changes, the error amplifier does not change its
value to keep the loop in regulation, thus ensuring a better line regulation and line transient
response.
To sum up the Open Loop Gain can be written as:

Equation 15
R2
G ( s ) = G PWM ( s ) • -------------------- • A O ( s ) • A LC ( s )
R1 + R2

Example:
Considering RC = 2.7 kΩ, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are:
FP1 = 9 Hz
FP2 = 256 kHz
FZ1 = 2.68 kHz
If L = 22 µH, COUT = 100 µF and ESR = 80 mΩ, the poles and zeroes of ALC become:
FPLC = 3.39 kHz
F0 = 19.89 kHz
Finally R1 = 5.6 kΩ and R2 = 3.3 kΩ.
The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12.

Figure 11. Module plot

15/31
Closing the loop AN1330

Figure 12. Phase plot

The cut-off frequency and the phase margin are:

Equation 16
F C = 22.8kHz Phase margin = 39.8°

16/31
AN1330 Application information

5 Application information

5.1 Component selection

● Input capacitor
The input capacitor must be able to withstand the maximum input operating voltage and the
maximum RMS input current.
Since step-down converters draw current from the input in pulses, the input current is
squared and the height of each pulse is equal to the output current. The input capacitor has
to absorb all this switching current, which can be up to the load current divided by two (worst
case, with duty cycle of 50%). For this reason, the quality of these capacitors has to be very
high to minimize the power dissipation generated by the internal ESR, thereby improving
system reliability and efficiency. The critical parameter is usually the RMS current rating,
which must be higher than the RMS input current.
The maximum RMS input current (flowing through the input capacitor) is:

Equation 17
2 2
2•D
I RMS = I O -+D
• D – ----------------- -------
η η
Where η is the expected system efficiency, D is the duty cycle and IO the output DC current.
This function reaches its maximum value at D = 0.5 and the equivalent RMS current is equal
to IO divided by 2 (considering η = 1). The maximum and minimum duty cycles are:

Equation 18
V OUT + V F V OUT + V F
D MAX = ---------------------------------------- and D MIN = -----------------------------------------
V INMIN – V SW V INMAX – V SW

Where VF is the freewheeling diode forward voltage and VSW the voltage drop across the
internal PDMOS. Considering the range DMIN to DMAX, it is possible to determine the max
IRMS going through the input capacitor. Capacitors that can be considered are:
– Electrolytic capacitors: These are widely used due to their low price and their
availability in a wide range of RMS current ratings. The only drawback is that,
considering ripple current rating requirements, they are physically larger than
other capacitors.
– Ceramic capacitors: If available for the required value and voltage rating, these
capacitors usually have a higher RMS current rating for a given physical dimension
(due to very low ESR). The drawback is the considerably high cost.
– Tantalum capacitors: Good, small tantalum capacitors with very low ESR are
becoming more available. However, they can occasionally burn if subjected to very
high current during charge. Therefore, it is better to avoid this type of capacitor for
the input filter of the device. They can, however, be subjected to high surge current
when connected to the power supply.
● Output capacitor
The output capacitor is very important to meet the output voltage ripple requirement.
Using a small inductor value is useful to reduce the size of the choke but it increases the
current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required.

17/31
Application information AN1330

Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain,
which helps to increase the phase margin of the system. If the zero goes to a very high
frequency, its effect is negligible. For this reason, ceramic capacitors and very low ESR
capacitors in general should be avoided.
Tantalum and electrolytic capacitors are usually a good choice for this purpose.
Table 3 below provides a list of some tantalum capacitor manufacturers.

Table 3. Output capacitor selection

Manufacturer Series Cap value (µF) Rated voltage (V) ESR (mΩ)

AVX TPS 100 to 470 4 to 35 50 to 200

KEMET T494/5 100 to 470 4 to 20 30 to 200
Sanyo POSCAP (1)
TPA/B/C 100 to 470 4 to 16 40 to 80
Sprague 595D 220 to 390 4 to 20 160 to 650
1. POSCAP capacitors have characteristic very similar to tantalum capacitors.

● Inductor
The inductor value is very important because it fixes the ripple current flowing through
output capacitor.
The ripple current is usually fixed at 20-40% of IOmax, which is 0.2 - 0.4 A with IOmax = 1 A.
The approximate inductor value is obtained using the following formula:

Equation 19
( V IN – V OUT )
L = --------------------------------------- • T ON
∆I
where TON is the ON time of the internal switch, given by D · T.
For example, with VOUT = 3.3 V, VIN = 12 V and ∆IO = 0.3 A, the inductor value is about
35 µH.
The peak current through the inductor is given by:

Equation 20
I PK = I O + ∆
-----I
2
and it can be observed that if the inductor value decreases, the peak current (which must be
lower than the current limit of the device) increases. So, when the peak current is fixed, a
higher inductor value allows a higher value for the output current.
In Table 4: Inductor selection, some inductor manufacturers are listed.

Table 4. Inductor selection

Manufacturer Series Inductor value (µH) Saturation current (A)

DO1813HC 22 to 33 1 to 1.2
Coilcraft
DO3316 33 to 47 1.6 to 2

18/31
AN1330 Application information

Table 4. Inductor selection (continued)

Manufacturer Series Inductor value (µH) Saturation current (A)

UP1B 22 to 33 1 to 1.2
Coiltronics
UP2B 33 to 47 1.7 to 2
HM76-2 22 to 33 1 to 1.2
BI
HM76-3 33 to 47 2 to 2.5
Murata LQN6C 22 to 33 0.9 to 1.2
Panasonic ELLATV 22 to 47 1.4 to 2.05
Sumida CR75 22 to 33 1.2 to 1.5
Epcos B82476 33 to 47 1.6 to 2
Wurth Elektronik 744561 33 to 47 1.6 to 2

5.2 Layout considerations

The layout of switching DC-DC converters is very important to minimize noise and
interference. Power-generating portions of the layout are the main cause of noise and so
high switching current loop areas should be kept as small as possible and lead lengths as
short as possible.
High impedance paths (in particular the feedback connections) are susceptible to
interference, so they should be as far as possible from the high current paths. A layout
example is provided in Figure 13 below.
The input and output loops are minimized to avoid radiation and high frequency resonance
problems. The feedback pin connections to the external divider are very close to the device
to avoid pick-up noise. Moreover the GND pin of the device is connected to the ground plane
directly with VIA on the bottom side of the PCB.

Figure 13. Layout example

COMPENSATION NETWORK FAR
FROM HIGH CURRENT PATHS

to output voltage
MINIMUN SIZE OF FEEDBACK Inhibit signal
PIN CONNECTIONS TO AVOID
PICKUP
R2
5 4
R1 L
L5970

8 1
CONNECTION TO
GROUNDPLANE Vin Vout
THROUGH VIA

Cin D Cout
Gnd
VERY SMALL HIGH CURRENT OUTPUT CAPACITOR
CIRCULATING PATH TO MINIMIZE DIRECTLY CONNECTED
RADIATION AND HIGH FREQUENCY TO HEAVY GROUND
RESONANCE PROBLEMS AM00012v1

19/31
Application information AN1330

5.3 Thermal considerations

The dissipated power of the device is tied to three different sources:
● switching losses due to the not negligible RDSON. These are equal to:

Equation 21
2
P ON = R DS ( on ) • ( I OUT ) • D

Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by
the ratio between VOUT and VIN, but in practice it is substantially higher than this value to
compensate for the losses of the overall application. For this reason, the switching losses
related to the RDSON increase compared to an ideal case.
● Switching losses due to turning ON and OFF. These are derived using the following
equation:

Equation 22
( T ON + T OFF )
P SW = V IN • I OUT • ----------------------------------------- • F SW = V IN • I OUT • T SW • F SW
2

where TON and TOFF are the overlap times of the voltage across the power switch and the
current flowing into it during the turn ON and turn OFF phases. TSW is the equivalent
switching time.
● Quiescent current losses.

Equation 23
P Q = V IN • I Q

Where IQ is the quiescent current.

● Example:
– VIN = 5 V
– VOUT = 3.3 V
– IOUT = 1 A
RDSON has a typical value of 0.25 Ω @ 25 °C and increases up to a maximum value of 0.5 Ω
@ 150 °C. We can consider a value of 0.4 Ω.
TSW is approximately 120 ns. IQ has a typical value of 2.5 mA @ VIN = 12 V. The overall
losses are:

Equation 24
2
P TOT = R DSON ⋅ ( I OUT ) ⋅ D + V IN ⋅ I OUT ⋅ T SW ⋅ F SW + V IN ⋅ I Q =
2 –9 3 –3
0.4 ⋅ 1 ⋅ 0.7 + 5 ⋅ 1 ⋅ 120 ⋅ 10 ⋅ 250 ⋅ 10 + 5 ⋅ 2.5 ⋅ 10 ≅ 0.44W

The junction temperature of the device will be:

Equation 25
T J = T A + Rth J – A • P TOT

where TA is the ambient temperature and RthJ-A is the thermal resistance junction-to-
ambient.

20/31
AN1330 Application information

Considering the device in an SO-8 package mounted on the board with a good groundplane,
that it has a thermal resistance-junction to-ambient (RthJ-A) of about 115 °C/W and an
ambient temperature of about 70 °C.

Equation 26
T J = 70 + 0.44 • 115 ≅ 121°C

5.4 Short-circuit protection

In overcurrent protection mode, when the peak current reaches the current limit, the device
reduces the TON down to its minimum value (approximately 250 ns) and the switching
frequency to approximately one third of its nominal value (see Section 2.4: Current
protection). In these conditions, the duty cycle is strongly reduced and, in most of
applications, this is enough to limit the current to ILIM. In any event, in case of heavy short-
circuit at the output (VOUT=0 V) and depending on the application conditions (VCC value and
parasitic effect of external components) the current peak could reach values higher than
ILIM.
This can be understood considering the inductor current ripple during the ON and OFF
phases:
● ON phase

Equation 27
( VIN – Vout – DCRL • I )
∆I L = ---------------------------------------------------------------------
L
• TON
● OFF phase

Equation 28
( V D + V out + DCR L • I )
∆I L = ------------------------------------------------------------------
L
• T OFF
where VD is the voltage drop across the diode, and DCRL is the series resistance of the
inductor.
In short-circuit conditions, VOUT is negligible. So, during the TOFF, the voltage applied to the
inductor is very small and it may be that the current ripple in this phase does not
compensate for the current ripple during the TON.
The maximum current peak can be easily measured through the inductor with VOUT=0 V
(short-circuit) and VCC=VINmax. In cases where the application must sustain the short-
circuit condition for an extended period, the external components (mainly the inductor and
diode) must be selected based on this value.

21/31
Application information AN1330

Figure 14. Short-circuit current (VIN = 25 V)

Figure 15. Short-circuit current (VIN = 30 V)

In Figure 14 and Figure 15, for example, it can be observed that when the input voltage
increases for a given component list, the current peak increases also. The current limit is
immediately triggered but the current peak increases until the current ripple during the TOFF
is equal to the current ripple during the TON.

5.5 Application circuit

Figure 16 shows the demonstration board application circuit for the device in the SMD
version, where the input supply voltage, VCC, can range from 4.4 V to 25 V due to the rated
voltage of the input capacitor and the output voltage is adjustable from 1.235 V to VCC.

22/31
AN1330 Application information

Figure 16. Demonstration board application circuit

VREF
3.3V 6 OUT L1 33∝H VOUT=3.3V
1
VIN = 4.4V to 25V VCC
8 D1
L5970D STPS2L25U R1
SYNC. 2 5.6K
FB C2
COMP 5 100∝F
C1 4 3 7 10V
10∝F C4
25V 22nF INH. GND
R2
CERAMIC C3 3.3K
220pF R3
4.7K

AM00017v1

Table 5. Component list

Reference Part number Description Manufacturer

C1 GRM32DR61E106KA12L 10 µF, 25 V Murata

C2 POSCAP 10TPB100M 100 µF, 10 V Sanyo
C3 C1206C221J5GAC 220 pF, 5%, 50 V KEMET
C4 C1206C223K5RAC 22 nF, 10%, 50 V KEMET
R1 5.6 K, 1%, 0.1 W 0603 Neohm
R2 3.3 K, 1%, 0.1 W 0603 Neohm
R3 4.7 K, 1%, 0.1 W 0603 Neohm
D1 STPS2L25U 2 A, 25 V STMicroelectronics
L1 DO3316P-333 33 µH, 2 A Coilcraft

Figure 17. PCB layout (component side)

L5970D
EVAL.BOARD R
R2 R3
INH
REF C4
R1 L1
C3 SYN

VIN U1
VOUT
C1
D1
GND GND.
C2
www.st.com
AM00018v1

23/31
Application information AN1330

Figure 18. PCB layout (bottom side)

AM00019v1

Figure 19. PCB layout (front side)

AM00020v1

Below, some graphs are provided which show the Tj versus output current in different input
and output voltage conditions, as well as some efficiency measurements.

Figure 20. Junction temperature vs. output Figure 21. Junction temperature vs. output
current (VCC = 5 V) current (VCC = 12 V)
Tj(°C) Tj(°C)
130 130
120 120 Vo=5V Vo=3.3V
Vo=3.3V
110 Vo=2.5V 110
100 100 Vcc=12V Vo=2.5V
Vcc=5V
90 Vo=1.8V 90 Tamb=25°C
Tamb=25°C
80 80
70 70
60 60
50 50
40 40
30 30
20 20
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Io(A) Io(A)

24/31
AN1330 Application information

Figure 22. Junction temperature vs. output Figure 23. Efficiency vs. output current (VCC =
current (VCC = 24 V) 5 V)
Tj(°C)
94
140 Vo=12V 92
Vo=18V
90 Vo=3.3V
120
88

Efficiency (%)
100 Vcc=24V Vo=5V 86
Tamb=25°C 84 Vo=2.5V
80 82
80
60 Vo=1.8V
78
40 76
74
20 Vcc=5V
72
0 70
0.2 0.4 0.6 0.8 1 1.2 1.4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Io(A) Io (A)

Figure 24. Junction temperature vs. output current (VCC = 12 V)

92
Vo=5V
90
88
86 Vo=3.3V
Efficiency (%)

84
82
80
78 Vo=2.5V
76
74 Vcc=12V
72
70
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Io (A)

25/31
Application ideas AN1330

6 Application ideas

6.1 Positive buck-boost regulator

The device can be used to implement a step-up/down converter with a positive output
voltage. Figure 25 below shows the schematic diagram of this topology for an output voltage
of 12 V.
The input voltage can range from 5 V and 35 V. The output voltage is given by VO=VIN ·
D/(1-D), where D is duty cycle. The maximum output current is given by IOUT=1× (1-D). The
current capability is reduced by the term (1-D) and so, for example, with a duty cycle of 0.5,
the maximum output current deliverable to the load is 0.5 A. This is due to the fact that the
current flowing trough the internal power switch is delivered to the output only during the
OFF phase.

Figure 25. Positive buck-boost regulator

L1 D2
33uH STPS2L25U VOUT=12V/0.3A
VIN=5V VCC OUT
8 1
U1 D1
COMP STPS2L25U
L5970 24k
FB
4 5 C4
C1
2 6 7 3 M1 100uF
10uF
C2 C3 STN4NE03L 16V
25V GND INH
22nF SYNC VREF
Ceramic 220pF 2.7k
R3
4.7k 3.3V

Vin=5V Vout=12V Iout=0.3A Efficiency=76%

6.2 Buck-boost regulator

In Figure 26, the schematic circuit for a standard buck-boost topology is shown. The output
voltage is given by VO = - VIN · D/(1-D). The maximum output current is equal to IOUT=1 · (1-
D), for the same reason as that of the up-down converter. An important thing to take into
account is that the ground pin of the device is connected to the negative output voltage.
Therefore, the device is subjected to a voltage equal to VIN-VO, that has to be lower than 36
V (the maximum operating input voltage).

Figure 26. Buck-boost regulator

26/31
AN1330 Application ideas

6.3 Dual output voltage with auxiliary winding

When two output voltages are required, it is possible to create a dual output voltage
converter by using a coupled inductor. During the ON phase, the current is delivered to
VOUT while D2 is reverse-biased.
During the OFF phase, the current is delivered through the auxiliary winding to the output
voltage VOUT1. This is possible only if the magnetic core has stored sufficient energy. So, to
be certain that the application is working properly, the load related to the second output
VOUT1 should be much lower than the load related to VOUT.

Figure 27. Dual output voltage with auxiliary winding

6.4 Synchronization example

Two or more devices (up to 6) can be synchronized simply by connecting the
synchronization pins. In this case, the device with a slightly higher switching frequency value
will work as master and the ones with a slightly lower switching frequency values will work
as a slaves.
The device can also be synchronized from an external source. In this case the logic signal
must have a frequency higher than the internal switching frequency of the device (250 kHz).

Figure 28. Synchronization example

27/31
Compensation network with MLCC (multiple layer ceramic capacitor) at the output AN1330

7 Compensation network with MLCC (multiple layer

ceramic capacitor) at the output

MLCCs with values in the range of 10 µF-22 µF and rated voltages in the range of 10 V-25 V
are available today at relatively low cost from many manufacturers.
These capacitors have very low ESR values (a few mΩ) and thus are occasionally used for
the output filter in order to reduce the voltage ripple and the overall size of the application.
However, a very low ESR value affects the compensation of the loop (see Section 4: Closing
the loop) and in order to keep the system stable, a more complicated compensation network
may be required. Figure 29 shows an example of a compensation network that stabilizes the
system with ceramic capacitors at the output (the optimum component value depends on
the application).

Figure 29. MLCC compensation network example

7.1 External SOFT_START network

At the start-up, the device can quickly increase the current up to the current limit in order to
charge the output capacitor. If a soft ramp-up of the output voltage is required, an external
soft-start network can be implemented as shown in Figure 30.
The capacitor C is charged up to an external reference (through R), and the BJT clamps the
COMP pin.
This clamps the duty cycle, limiting the slew rate of the output voltage.

28/31
AN1330 Compensation network with MLCC (multiple layer ceramic capacitor) at the output

Figure 30. Soft start network example

33uH
Coilcraft VOUT=3.3V
VIN=4.4V to 25V Vcc OUT
8 1
VREF L1
D1
R=4K7
VREF 6 L5970D STPS2L25U R1=5.6K
COMP FB
4 5
C1 C4=22nF
10uF
BC327 2 7 3 R2=3.3K
C2
25V SYNC 100uF
Css=2.7nF GND INH
CERAMIC C3=220pF 10V
R3=4.7K

AM00026v1

29/31
Revision history AN1330

8 Revision history

Table 6. Document revision history

Date Revision Changes

– the document has been reformatted

22-May-2007 2 – Section 4: Closing the loop modified
– Minor text changes
– Restructured document sections
19-May-2008 3
– Minor text changes

30/31
AN1330

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