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Exercise 1:: U11:Y D:1 Clock:1

The document contains 6 exercises describing various digital logic circuits using flip-flops and gates. Exercise 1 describes a negative edge triggered D flip-flop using NOR gates with a circuit diagram and timing diagram. Exercise 2 describes a positive edge triggered J-K flip-flop with preset and clear functions, showing the effects of different control signal combinations on the output. Exercise 3 shows a positive edge triggered master-slave J-K flip-flop. Exercise 4 demonstrates a divide-by-8 circuit using flip-flops. Exercise 5 illustrates a 3-bit serial-to-parallel converter. Exercise 6 displays a 3-bit parallel-to-serial converter. Each exercise contains circuit diagrams and corresponding timing diagrams.

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Anik Paul
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142 views6 pages

Exercise 1:: U11:Y D:1 Clock:1

The document contains 6 exercises describing various digital logic circuits using flip-flops and gates. Exercise 1 describes a negative edge triggered D flip-flop using NOR gates with a circuit diagram and timing diagram. Exercise 2 describes a positive edge triggered J-K flip-flop with preset and clear functions, showing the effects of different control signal combinations on the output. Exercise 3 shows a positive edge triggered master-slave J-K flip-flop. Exercise 4 demonstrates a divide-by-8 circuit using flip-flops. Exercise 5 illustrates a 3-bit serial-to-parallel converter. Exercise 6 displays a 3-bit parallel-to-serial converter. Each exercise contains circuit diagrams and corresponding timing diagrams.

Uploaded by

Anik Paul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Exercise 1:

Figure 1: Circuit Diagram of Negative Edge Triggered D Flip-Flop Using NOR Gate

U11:Y
D:1
Clock:1
Figure 2: Timing Diagram of Negative Edge Triggered D Flip-Flop Using NOR Gate

0s 2us 4us 6us 8us 10us 12us 14us 16us 18us 20us
Time
Exercise 2:

Figure 3: Circuit Diagram of Positive Edge Triggered J-K Flip-Flop with Preset and Clear

Timing Diagram of Positive Edge Triggered J-K Flip-Flop with Preset and Clear:

Qbar
Preset:1
Clear:1
K:1
J:1
Q
Clock:1

Figure 4: Preset=Clear=1, Q in red indicates don’t care but should have been High.

Qbar
Preset:1
Clear:1
K:1
J:1
Q
Clock:1

Figure 5: Preset=0, Clear=0, Q=1, Qbar=1. Preset=0, Clear=0, Q=1, Qbar=1, Q determined by Preset and Qbar by Clear.

Qbar
Preset:1
Clear:1
K:1
J:1 98.33us 100.00us 104.00us 108.00us 112.00us 116.00us 120.00us 124.00us 127.50us
Q Time
Clock:1

Figure 6: Preset=0,1 and Clear=1. Q is determined by Preset and Qbar by Clear.

50us 55us 60us 65us 70us 75us 80us 85us 90us 95us 100us
Time

125us 130us 135us 140us 145us 150us 155us 160us 165us 170us 175us
Time
Exercise 3:

Figure 7: Circuit Diagram of Positive Edge Triggered Master-Slave J-K Flip-Flop

CLOCK:1
K:1
J:1
Qbar
Q
Figure 8: Timing Diagram of Positive Edge Triggered Master-Slave J-K Flip-Flop

10.0us 11.0us 12.0us 13.0us 14.0us 15.0us 16.0us 16.5us


Time
Exercise 4:

Figure 9: Circuit Diagram of Divide by 8 Device Using 7476

CLOCK
HIGH
Q2
U2A:Q
Q0
Figure 10: Timing Diagram of Divide by 8 Device Using 7476

0s 1us 2us 3us 4us 5us 6us 7us 8us 9us 10us
Time
Exercise 5:

Figure 11: Circuit Diagram of 3 bit Serial in Parallel out Using 7474

CLOCK
D
Qa
Qb
Qc
Figure 12: Timing Diagram of 3 bit Serial in Parallel out Using 7474

0.01us 1.00us 2.00us 3.00us 4.00us 5.00us 6.00us 6.51us


Time
Exercise 6:

Figure 13: Circuit Diagram of 3 bit Parallel in Serial out Using 7474

Output
D2:1
D1:1
D0:1
Clock:1
Figure 14: Timing Diagram of 3 bit Parallel in Serial out Using 7474

10us 12us 14us 16us 18us 20us 22us 24us 26us 28us 30us
Time

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