ECE 538

VLSI System Testing

Krish Chakrabarty

Logic Simulation

ECE 538 Krish Chakrabarty 1

Introduction
•  Motivation
•  Types of logic simulation
–  Compiled code
–  Event-driven
•  Delay models
•  Element evaluation
•  Hazard detection

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 Motivation
•  A design verification technique (functional and timing)
•  Compare results obtained with expected responses
specified by the specification
•  Use software model
Stimuli Simulation
and program Results
control

Internal
model

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Motivation
•  Correctness, independent of initial (power-on) state
•  Insensitive to small variations in component delays
•  Free of races, oscillations, “illegal” input
combinations, “unsafe” states
•  Evaluation of design alternatives (what-if scenarios)
•  Documentation (generation of timing diagrams)

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 Logic Simulation
•  What is simulation?
•  Design verification
•  Circuit modeling
•  True-value simulation algorithms
•  Compiled-code simulation
•  Event-driven simulation
•  Summary

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Simulation Defined
•  Definition: Simulation refers to modeling of a design, its
function and performance.
•  A software simulator is a computer program; an emulator is a
hardware simulator.
•  Simulation is used for design verification:
•  Validate assumptions
•  Verify logic
•  Verify performance (timing)
•  Types of simulation:
•  Logic or switch level
•  Timing
•  Circuit
•  Fault

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 Simulation for Verification
Specification

Synthesis

Response Design Design

analysis changes (netlist)

Computed True-value
Input stimuli
responses simulation

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Modeling for Simulation

•  Modules, blocks or components described by
•  Input/output (I/O) function
•  Delays associated with I/O signals
•  Examples: binary adder, Boolean gates, FET, resistors and
capacitors
•  Interconnects represent
•  ideal signal carriers, or
•  ideal electrical conductors
•  Netlist: a format (or language) that describes a design as
an interconnection of modules. Netlist may use hierarchy.

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 Example: A Full-Adder
HA;
c
inputs: a, b;
a
e outputs: c, f;
AND: A1, (a, b), (c);
d f AND: A2, (d, e), (f);
b OR: O1, (a, b), (d);
HA NOT: N1, (c), (e);

FA;
A D inputs: A, B, C;
Carry
B
HA1 E F outputs: Carry, Sum;
HA2 Sum HA: HA1, (A, B), (D, E);
C HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);

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Logic Model of MOS Circuit

VDD
pMOS FETs
a Da
a Dc c
Ca b Db
c
Cc
b Da and Db are
Cb
nMOS FETs interconnect or
propagation delays

Dc is inertial delay
Ca , Cb and Cc are of gate
parasitic capacitances
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 Options for Inertial Delay
(simulation of a NAND gate)
Transient
a
Inputs region

c (CMOS)

c (zero delay)
Logic simulation

c (unit delay)

X
c (multiple delay) rise=5, fall=5

Unknown (X)
c (minmax delay) min =2, max =5

0 5 Time units
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Signal States
•  Two-states (0, 1) can be used for purely combinational logic
with zero-delay.
•  Three-states (0, 1, X) are essential for timing hazards and
for sequential logic initialization.
•  Four-states (0, 1, X, Z) are essential for MOS devices. See
example below.
•  Analog signals are used for exact timing of digital logic and
for analog circuits.
Z
(hold previous value)
0
0

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 Modeling Levels
Modeling Circuit Signal Timing Application
level description values
Programming Clock Architectural
Function, 0, 1 and functional
language-like HDL boundary verification
behavior, RTL
Connectivity of 0, 1, X Zero-delay Logic
Logic Boolean gates, unit-delay, verification
flip-flops and and Z multiple- and test
transistors delay
Transistor size Logic
Switch 0, 1 Zero-delay
and connectivity, verification
and X
node capacitances

Transistor technology Analog Fine-grain Timing

Timing
data, connectivity, voltage timing verification
node capacitances
Continuous Digital timing
Circuit Tech. Data, active/ Analog
time and analog
passive component voltage, circuit
connectivity current verification

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True-Value Simulation
Algorithms
•  Compiled-code simulation (oblivious simulation)
•  Applicable to zero-delay combinational logic
•  Also used for cycle-accurate synchronous sequential circuits
for logic verification
•  Efficient for highly active circuits, but inefficient for low-
activity circuits
•  High-level (e.g., C language) models can be used
•  Event-driven simulation (exclusive simulation of activity)
•  Only gates or modules with input events are evaluated (event
means a signal change)
•  Delays can be accurately simulated for timing verification
•  Efficient for low-activity circuits
•  Can be extended for fault simulation

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 Types of Simulation (Contd.)
•  Compiled-code (oblivious)
–  The circuit is described in a programming language and an executable
model is generated
–  Circuit operation ≡ program execution
–  Fast and efficient but inflexible; practical only for small circuits
•  Event-driven
–  Exclusive simulation of activity
–  Circuit is a data structure, simulation program is same for all circuits
–  Flexible, but requires event list management (overhead)

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Compiled-Code Algorithm
•  Step 1: Levelize combinational logic and encode in a
compilable programming language
•  Step 2: Initialize internal state variables (flip-flops)
•  Step 3: For each input vector
–  Set primary input variables
–  Repeat (until steady-state or max. iterations)
•  Execute compiled code
–  Report or save computed variables

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 Compiled-Code Simulation
LDA B A F
AND Q D Q
B E C
INV
STA E
OR A
STA F
STA Q

Simulation program
•  Delays can be modeled by explicitly adding
them to the software model

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Event-Driven Simulation
Advance simulation time Done
No more
events
Determine current events

Update values

Propagate events

Evaluate activated elements

Schedule resulting events

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 Event-Driven Simulation
0 G
A 0
2
B 1 F
3
0
Y
C
2 0 E 1
1→0
D 2 0Z
at t = 0 0

Snapshot of event list

t=0 t=2 t=4
Event Time Event Time Event Time
F=1 t=2 G=1 t=4 Y=1 t=7
Z=1 t=4

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Event-Driven Algorithm
(Example) Scheduled Activity
events list

t=0 c=0 d, e
a =1 e =1
c =1 0 2 1
g =1 2 d = 1, e = 0 f, g
2
2
d=0 3
Time stack

4 f =0 4 g=0
b =1
5

6 f=1 g
g
4 8 7
0
Time, t
8 g=1

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 Time Wheel (Circular Stack)
Current max
time t=0
pointer Event link-list
1

4
5
6
7

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Efficiency of Event-driven
Simulator
•  Simulates events (value changes) only
•  Speed up over compiled-code can be ten times or
more; in large logic circuits about 0.1 to 10% gates
become active for an input change

Steady 0
Steady 0 Large logic
block without
(no event) activity
0 to 1 event

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 Delay Models
•  Transport delay (pure delay)
–  Single delay value for each gate
•  Rise/fall times
–  Two delay values for each gate output
•  Ambiguity delay
–  Min and max delay values for each gate
–  Ambiguity region becomes enlarged towards primary outputs
•  Inertial delay
–  Filter out narrow pulses (spikes and glitches)

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Element Evaluation
•  Simulation speed depends on fast elements (gates) that can be
evaluated
•  Truth tables
–  O(1) evaluation but O(2N) storage
–  Decision step needed (which truth table?)
•  Zoom table of size tS combines t individual truth tables, S is size of
largest truth table

Type t-1

Type 1 index
type values
Type 0

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 Input Scanning
evaluate (G,c,i) •  Controlling value c
begin •  Inversion value i
u_values = FALSE;
for every input value of G c X X c⊕i
begin X c X c⊕i
if v = c then return c ⊕ i X X c c⊕i
if v = u then u_values = TRUE c c c c⊕i
end
if u_values return u c i
return c ⊕ i AND 0 0
end OR 1 0
NAND 0 1
O(1) storage, O(N) evaluation NOR 1 1

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Input Counting
•  Maintain two counters c_count and u_count for every gate
–  c_count: number of inputs with c values
–  u_count: number of inputs with u values
•  These counters must be updated

evaluate (G,c,i)
begin •  O(1) storage
if c_count > 0 then return c ⊕ i •  O(1) evaluation
if u_count > 0 then return u
return c ⊕ i
end

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 Hazard Detection
0→1 A
Static hazard: 0 → 1 → 0
1 0 B
Dynamic hazard:
0 C 0→1→0→1

•  Simulator should detect hazards (analyze transient behavior of signals)

•  3-valued logic simulation:
Static hazard detected
0X1 A
1X0 B
0X0
000 C
•  How many logic values are necessary?
•  More the better, but…more complexity

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Summary
•  Logic or true-value simulators are essential tools for
design verification.
•  Verification vectors and expected responses are
generated (often manually) from specifications.
•  A logic simulator can be implemented using either
compiled-code or event-driven method.
•  Per vector complexity of a logic simulator is
approximately linear in circuit size.
•  Modeling level determines the evaluation procedures
used in the simulator.
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