STATIC TIMING

ANALYSIS
© Mirafra Technologies
1
Introduction
➢ Effective methodology for verifying the timing
characteristics of a design without the use of test vectors
➢ Conventional verification techniques are inadequate for
complex designs
➢ Simulation time using conventional simulators
➢ Thousands of test vectors are required to test all
timing paths using logic simulation ➢ Increasing design
complexity & smaller process technologies
➢ Increases the number of iterations for STA
© Mirafra Technologies
2
False timing paths
STA approach typically takes a fraction of the time it takes
to run logic simulation on a large design and guarantees
100% coverage of all true timing paths in the design
without having to generate test vectors
© Mirafra Technologies
0%

Simulation vs. Static

timing
Timing Simulation (adding vectors)
True timing paths
100%
Static timing analysis (eliminating false paths)
3
© Mirafra Technologies

OVERVIEW
Previous Verification Flow
4
OVERVIEW
© Mirafra Technologies
•
Requires extensive vector creation
• Valid for FPGAs and smaller ASICs
• Falls apart on multi-million gate ASICs
5
What is Static Timing
Analysis?
Static Timing Analysis is a method for
determining if a circuit meets timing
constraints without having to simulate
➢Much faster than timing-driven, gate-level
simulation
➢Proper circuit functionality is not checked
➢Vector generation NOT required
© Mirafra Technologies
6
STA in ASIC Design Flow
– Pre layout
Logic Synthesis
Constraints (clocks, input drive, output load)
Design For test
Floor
planning Static Timing Analysis
Static Timing Analysis (estimated parasitics)
© Mirafra Technologies
7
STA in ASIC Design Flow
– Post Layout
Floor planning
Constraints (clocks, input drive, output load)
Clock Tree Synthesis
Static Timing Analysis
Place and Route
(estimated parasitics)
Parasitic Extraction
Static Timing Analysis (extracted parasitics)
SDF (extracted parasitics)
© Mirafra Technologies
8
2 Types of Timing
Verification
Dynamic Timing Simulation
Advantages
➢Can be very accurate (spice-level)
Disadvantages
➢Analysis quality depends on stimulus
vectors
➢Non-exhaustive, slow
Examples:
VCS,Spice,ACE
© Mirafra Technologies
9
2 Types of Timing
Verification
Static Timing Analysis (STA)
Advantages
➢Fast, exhaustive
➢Better analysis checks against timing
requirements
Disadvantage
➢Less accurate
➢Must define timing
requirements/exceptions
➢Difficulty handling asynchronous designs,
false paths
© Mirafra Technologies
10
Three Steps in Static
Timing Analysis
➢ Circuit is broken down into sets of timing
paths
➢ Delay of each path is calculated
➢ Path delays are checked to see if timing
constraints
have been met
© Mirafra Technologies
11
A Timing Path is a point-to-point path in a
design which
can propagate data from one flip-flop to
another
❖Each path has a start point and an
endpoint
➢Start point:
➢Input ports Clock pins of flip-flops
➢Endpoints:
➢Output ports Data input pins of
flip-flops © Mirafra Technologies

What is a Timing Path?

12
Organizing Timing Paths
Into Groups
Timing paths are grouped into path groups
by the
clocks controlling their endpoints
Synthesis tools like PrimeTime and Design
Compiler organize timing reports by path
groups
© Mirafra Technologies
13
© Mirafra Technologies

Net and Cell Timing Arcs

The actual path delay is the sum of net and
cell delays along the timing path
14
© Mirafra Technologies

Net and Cell Delay

“Net Delay” refers to the total time needed to
charge or discharge all of the parasitics of a
given net
➢Total net parasitics are affected by
➢net length
➢net fanout
➢Net delay and parasitics are typically
➢Back-Annotated (Post-Layout) from data
obtained from
an extraction tool
➢Estimated (Pre-Layout)
15
Cell Delay
In ASICs, the delay of a cell is affected by:
➢The input transition time (or slew rate)
➢The total load “seen” by the output transistors
Net capacitance and “downstream” pin
capacitances
➢These will affect how quickly the input and
output transistors can “switch”
➢Inherent transistor delays and “internal” net
delays
© Mirafra Technologies
16
D-Type Register or Flip-Flop, Edge-Triggered
– data captured on rising edge of clock, held for rest of
cycle
© Mirafra Technologies

Clocked Storage
Elements
Transparent Latch, Level Sensitive
– data passes through when clock high, latched when
clock low
17
© Mirafra Technologies

Flip-Flops
18
Basic terminologies
➢ Pulse Width ➢ Setup & Hold times ➢ Signal
slew ➢ Clock latency ➢ Clock Skew ➢ Input
arrival time ➢ Output required time ➢ Slack and
Critical path
➢ Recovery & Removal times ➢ False
paths ➢ Multi-cycle paths
© Mirafra Technologies
19
Pulse Width
➢ Pulse width
➢ It is the time between the active and inactive states of
the same signal
© Mirafra Technologies
20
Both the above 2 timing violations can occur in a design
when
clock path delay > data path delay
© Mirafra Technologies

Setup and Hold time

➢ Setup time
➢ For an edge triggered sequential element, the setup
time is the time interval before the active
clock edge during which the data should remain
unchanged ➢ Hold time
➢ Time interval after the active clock edge during which
the data should remain unchanged
21
© Mirafra Technologies

Signal Slew
➢ Signal (Clock/Data) slew
➢ Amount of time it takes for a signal transition to occur ➢
Accounts for uncertainty in Rise and fall times of the signal
➢ Slew rate is measured in volts/sec
22
CLK
BUF

© Mirafra Technologies

Clock Latency
➢ Clock Latency
➢ Difference between the reference (source) clock slew to
the clock tree endpoint signal slew
values ➢ Rise latency and fall latency are specified
INV
INV

Rise=7 Fall=4
INV

Rise=7 Fall=4
INV

Rise=7 Fall=4
BUF
INV

Rise=7 Fall=4
Rise=7 Fall=4
Rise=7 Fall=4
INV

Rise=7 Fall=4
CLKB
CLKA
CLKC
23
© Mirafra Technologies

Clock Latency
24
Clock Skew
➢ Clock Skew is a measure of the difference in latency
between any two leaf pins in a clock tree.
➢ between CLKA and CLKB
rise = 22-8 = 14 fall = 22-14 = 8 ➢ between CLKB and
CLKC
rise = 8-7 = 1 fall = 14-4 = 10 ➢ between CLKA and CLKC
rise = 22-7 = 15 fall = 22-4 = 18 It is also defined as the
difference in time that a single clock signal takes to reach
two different
registers
© Mirafra Technologies
25
© Mirafra Technologies

Input Arrival time

➢ Input Arrival time
➢ An arrival time defines the time interval during which a
data signal can arrive at an input pin in
relation to the nearest edge of the clock signal that triggers
the data transition
26
© Mirafra Technologies

Output required time

➢ Output required time
➢ Specifies the data required time on output ports.
27
Slack and Critical path
➢ Slack
➢ It is the difference between the required (constraint)
time and the arrival time (inputs and delays). ➢ Negative
slack indicates that constraints have not been met, while
positive slack indicates that
constraints have been met. ➢ Slack analysis is used to
identify timing critical paths in a design by the static timing
analysis tool
➢ Critical path
➢ Any logical path in the design that violates the timing
constraints ➢ Path with a negative slack
© Mirafra Technologies
28
© Mirafra Technologies

Slack Analysis – Data

Path types
29
 Slack analysis – data path types ➢ Primary input-to-
register paths
➢ Delays off-chip + Combinational logic delays up to
the first sequential device. ➢ Register-to-primary output
paths
➢ Start at a sequential device ➢ CLK-to-Q transition delay
+ the combinational logic delay + external delay
requirements ➢ Register-to-register paths
➢ Delay and timing constraint (Setup and Hold) times
between sequential devices for synchronous
clocks + source and destination clock propagation
times. ➢ Primary input-to-primary output paths
➢ Delays off-chip + combinational logic delays + external
delay requirements.
© Mirafra Technologies
30
Hold Slack calculation
➢ Actual data arrival time definition
Data Input Arrival Timemin + Data path delaymin If the
data path starts in a primary input,
Data Input arrivalmin = Input arrival timemin If the
data path starts at a register,
(Source Clock Edgemin + Source Clock Path Delaymin) =
Data Input Arrivalmin
➢ Required Stability time definition
(Destination Clock Edgemax + Destination Clock Path
Delaymax) + Hold = Required Stability
Timemax
➢ Hold Slack definition
Actual Data Arrivalmin - Required Stability Timemax
© Mirafra Technologies
31
Min Data path delay = 0.802 ns Hold time constraint =
1.046 ns
© Mirafra Technologies

Calculate the hold slack

Source Clock signal timing parameters: Min Edge = 8.002
ns Min clock path delay = 0.002 ns
Destination Clock signal timing parameters: Max Edge =
2.020 ns Max clock path delay = 0.500 ns
32
© Mirafra Technologies

Hold slack calculation

33
Setup Slack calculation
➢ Actual data arrival time definition
Data Input Arrival Timemax + Data path delaymax If the
data path starts in a primary input,
Data Input arrivalmax = Input arrival timemax If the
data path starts at a register,
(Source Clock Edgemax + Source Clock Path Delaymax)
= Data Input Arrivalmax
➢ Required Stability time definition
(Destination Clock Edgemin + Destination Clock Path
Delaymin) - Setup = Required Stability
Timemin
➢ Setup slack definition
Required Stability Timemin - Actual Data Arrivalmax
© Mirafra Technologies
34
Source Clock signal timing parameters: Max Edge = 2.002
ns Max clock path delay = 0.002 ns
Destination Clock signal timing parameters: Min Edge =
20.02 ns Min clock path delay = 0.500 ns
Min Data path delay = 13.002 ns Setup time constraint =
0.046 ns
© Mirafra Technologies

Calculate the setup slack

35
© Mirafra Technologies

Setup slack calculation

36
Recovery and Removal
time
➢ Recovery time
Like setup time for asynchronous port (set, reset) ➢
Removal time
Like hold time for asynchronous port (set, reset)
➢ Recovery time
It is the time available between the asynchronous
signal going inactive to the active clock edge ➢ Removal
time
It is the time between active clock edge and asynchronous
signal going inactive
© Mirafra Technologies
37
False Paths
➢ False paths
➢ Paths that physically exist in a design but are not
logic/functional paths ➢ These paths never get sensitized
under any input conditions
Mux 1
A C C1 C2 B
Mux 2
S
OUT
© Mirafra Technologies
B1 B2
38
Multi-cycle paths
➢ Multi-cycle paths
➢ Data Paths that require more than one clock period for
execution
2 clock period delay
© Mirafra Technologies
39
Sequential Circuit Timing
Objectives
This section covers several timing considerations
encountered in the design of synchronous sequential
circuits. It has the following objectives:
➢ Define the following global timing parameters and show
how they can be derived from the basic
timing parameters of flip-flops and gates.
• Maximum Clock Frequency
• Maximum allowable clock skew
• Global Setup and Hold Times ➢ Discuss ways to
control the loading of data into registers and show why
gating the clock signal to do
this is a poor design practice.
© Mirafra Technologies
40
Maximum Clock
Frequency
➢ The clock frequency for a synchronous sequential circuit
is limited by the timing parameters of its flip-flops and
gates. This limit is called the maximum clock frequency for
the circuit. The minimum clock period is the reciprocal of
this frequency. ➢ Relevant timing parameters
❖ Gates:
• Propagation delays: min t
PLH

, min t
PHL

, max t
PLH

, max t
P
HL ❖ Flip-Flops:
• Propagation delays: min t
PLH

, min t
PHL

, max t
PLH
, max t
PHL

• Setup time: t
su

• Hold time: t
h

© Mirafra Technologies
41
© Mirafra Technologies
➢ Example
T
W

Q
DQ

Q CK
+t
su

For the 7474, max t

PLH

= 20ns T
W

= 25ns, max t
PHL

+t
su) T
W

≥ max (max t
PLH

+t
su,

max t
PHL ≥ max (25+20, 40+20) = 60
≥ max t
PFF

= 40ns, t
su

42
© Mirafra Technologies
➢ Example
DQ

CK
Q
T
W

≥ max t
PFF

+ max t
PINV

+t
su

43
+t
su

© Mirafra Technologies
➢ Example
DQ
Q

T
W
Q0 Q1
CK
≥ max t
PFF

+ max t
PMUX
0
1

MUX
DQ
Q

44
= 20 +10 = 30 ns
T
W

≥ max t
PDFF

+ max t
AND

+t
JKsu

= 20 + 12 + 10 = 42 ns
T
W

≥ max t
PJKFF

+t
OR

+T
Dsu

= 25 + 10 + 5 = 40 ns
T
W

≥ max t
PJKFF

+ max t
AND
+t
JKsu

= 25 + 12 + 10 = 47 ns
TW ≥ 47 ns
© Mirafra Technologies
➢ Example
Paths from Q1 to Q1:
Paths from Q1 to Q2:
Paths from Q2 to Q1:
Paths from Q2 to Q2:
None
T
W

≥ max t
PDFF

+t
JKsu

45
Clock Skew
➢ If a clock edge does not arrive at different flip-flops at
exactly the same time, then the clock is said
to be skewed between these flip-flops. The difference
between the times of arrival at the flip-flops is said to be
the amount of clock skew.
➢ Clock skew is due to different delays on different paths
from the clock generator to the various flip-
flops.
• Different length wires (wires have delay)
• Gates (buffers) on the paths
• Flip-Flops that clock on different edges (need to invert
clock for some flip-flops)
• Gating the clock to control loading of registers (a very
bad idea)
© Mirafra Technologies
46
- (if clock skewed, i.e., t
INV

> 0)
min t
INV

© Mirafra Technologies
• Example (Effect of clock skew on clock rate)
➢ Clock C2 skewed after C1
Q1

+ T (if W
clock not skewed, i.e., t
INV t
su

= 0)
≥ max T
PFF

+ max t
OR
Q2 D Q
Q

D2
DQ
Q

CK
C1
C2

T
W

≥ max T
PFF

+ max t
OR

+t
su

47
+ (if clock skewed, i.e., t
INV

> 0)
max t
INV

© Mirafra Technologies
➢ Clock C1 skewed after C2
Q1
Q2 D Q
Q

D2
DQ
Q

CK
C1
C2

T
W

T
W

≥ (if clock max not T

PFF

skewed, i.e., + t
INV t
su

= 0)
≥ max T
PFF

+ max t
OR

+ max t
OR

+t
su

48
➢ Summary of maximum clock frequency calculations
DQ
Q1 D2
Logic Network
C1
Q1
D2
DQ
C1 C2
T
W

T
W

t
SK

=t
INV

t
PFF

t
PFF

C2 skewed after C1: T

W
C1
t
SK

=t
INV

C2 C2
Q1
D2
t
OR

t
su
t
OR

t
su

≥ max T
PFF

+ max t
NET

+t
su

- min t
I
NV C2 skewed before C1: T
W

≥ max T
PFF

+ max t
NET

+t
su

+ max t
INV

© Mirafra Technologies
49
© Mirafra Technologies

Maximum Allowable Clock

Skew
➢ How much skew between C1 and C2 can be tolerated in
the following circuit?
– Case 1: C2 delayed after C1
Q1 D2
C1
DQ
DQ
Q
Q

C2
>t
PFF

t
h

+t
SK

t
SK

< min t
PFF
-t
h

50
© Mirafra Technologies
➢ Case 2: C1 delayed from C2
Q1 D2
C1
DQ
Q

C2
DQ
Q

51
-t
h

© Mirafra Technologies

➢How does additional delay

between the flip-flops affect
the skew calculations?guy
≤t
SK

min t
PFF

-t
h

t
sk

≤ min t
PFF

+ min t
MUX

52
-t
h

© Mirafra Technologies

➢Summary of allowable clock

skew calculations
≤tt
SK
SK

+ ≤ min t h
tt
PFF
PFF

++t
min NET
t
NET

53
➢ Example: What is the minimum clock period for the
following circuit under the assumption that the clock
C2 is skewed after C1 (i.e., C2 is delayed from C1)?
N2
D1
DQ

Q1 N1 D2 Q2 Q
C1 C2
DQ
Q

© Mirafra Technologies
54
N2
D1
DQ

Q1 D2 Q2 Q
C1 C2
N1
DQ
Q

➢ First calculate the maximum allowable clock skew.

t
SK

< min t
PFF

+ min t
N1

-t
h ➢ Next calculate the minimum clock period due to the
path from Q1 to D2.
T
W

> max t
PFF

+ max t
N1

+t
su

- min t
 SK ➢ Finally calculate the minimum clock period due to
the path from Q2 to D1
T
W

> max t
PFF

+ max t
N1

+t
su

+ max t
SK

T
W

> max t
PFF

+ max t
N2

+t
su

+ (min t
PFF

+ min t
N1

-t
h
)
T
W

> max t
PFF

+ min t
PFF

+ max t
N2

+ min t
N1

+t
su

-t
h

© Mirafra Technologies
55
Global Setup Time, Hold
Time and Propagation
Delay
➢Global setup and hold times
(data delayed)
T
SU

X
NET
D
DQ

CLK
CK
Q

=t
su

+ max t
NET

T
H
=t
h

- min t
NET

© Mirafra Technologies
56
© Mirafra Technologies
➢ Global setup & hold time (clock delayed)
D
DQ

CLK
Q

T
SU

CK
=t
su

- min t
C

T
H

=t
h

+ max t
C

57
+ max t
C

© Mirafra Technologies
➢ Global setup & hold time (data & clock delayed)
X
NET
D
DQ

CLK
CK
Q

T
SU

= + max =-0987654321\ - min . T

H

=t
h

- min t
NET

58
+t
NET

© Mirafra Technologies
➢ Global propagation delay
D Q CK
Q

NET CLK
T
P

=t
C

+t
FF

Q
Y
59
+ max t
PN

T
H

=t
h

+ max t
PC

- min t
PN

≤t
h

+ max t
PC

T
P

=t
PFF

+t
PN

+t
PC

© Mirafra Technologies
➢ Summary of global timing parameters
T
SU
=t
su

+ max t
PN

- min t
PC

≤t
su

60
➢ Example
❖ Find T
SU

LD
CLK D
DQ
Q
Q
T
SU

CK
and T
H

for input signal LD relative to CLK.

=t
su

+max t
NET

- min t
C

T
H

=t
su

+ max t
INV

+ max t
NAND

+ max t
NAND

- min t
INV

=t
h

- min t
NET

+ max t
C

=t
h

- min t
NAND

- min t
NAND

+ max T
INV

© Mirafra Technologies
61
© Mirafra Technologies

Register load control

(gating the clock)
• A very bad way to add a load control signal LD to a
register that does not have one is shown below
D
DQ
LD
CK
Q
• The reason this is such a bad idea CLK
is illustrated by the following timing diagram.
• The flip-flop sees two rising edges and will trigger twice.
The only one we want is the second one.
62
© Mirafra Technologies
➢ If LD was constrained to only change when the clock
was low, then the only problem would be the
clock skew.
63
© Mirafra Technologies
➢ If gating the clock is the only way to control the loading
of registers, then use the following approach:
D
DQ
CLK
Q
LD

➢ There is still clock skew, but at least we only have one

triggering edge.
64
➢ The best way to add a LD control signal is as follows:
LD
D CLK
DQ
Q
© Mirafra Technologies
65
➢ Use timing diagrams to determine the timing properties
of sequential circuits ➢ Using typical timing values from
the data sheet (use only max and/or min values) ➢ Gating
the clock
© Mirafra Technologies

Tips & Tricks

66
(a) Hold time for clocks is 1.5 ns
Determine if there are any timing violations in this design
© Mirafra Technologies
clk20Mhtzref

Detecting timing violations

– CASE 1
Data
DFF 1
Delay (min) = 5 ns
clk10Mhtz
DFF 2
67
(a) Hold time for clocks is 1.5 ns (b) Clock skew of 3.72 ns
between clk20mref and clk10mz
Determine if there are any timing violations in this design
© Mirafra Technologies
clk20Mhtzref

Detecting timing violations

– CASE 2
Data
DFF 1
Delay (min) = 5 ns
clk10Mhtz
DFF 2
68
Delay (min) = 5 ns
© Mirafra Technologies
clk20Mhtzref

Detecting timing violations

– CASE 3
(a) Hold time for clocks is 1.5 ns (b) Clock skew of 3.72 ns
between clk20mref and clk10mz
Data
DFF 1
clk10Mhtz
DFF 2
69
Propagation delay = 4 ns (thru clock tree buffers)
© Mirafra Technologies

Detecting timing violations

– CASE 4
Consider (a) Clock skew of 3.72 ns between clk20mref
and clk10mz (b) Clock network delays
clk20Mhtzref
Data
DFF 1
Propagation delay = 2 ns (thru clock tree buffers)
Delay (min) = 5 ns
clk10Mhtz
DFF 2
70
Thank you
© Mirafra Technologies
71