Chapter 3

Logic and Fault Simulation

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 1
 About the Chapter

Circuit simulation models

Logic simulation techniques

Fault simulation techniques

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 2
 Logic and Fault Simulation

Introduction

Simulation models

Logic simulation

Fault simulation

Concluding remarks

3
VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 3
 Logic Simulation

Predict the behavior of a design prior to its physical
realization
Specification

Design verification

Manual design or Testbench

via Synthesis Development

Circuit Expected
Input Stimuli
Description Responses

yes Simulated
Responses
Bug?
no Response
Analysis
Next Design
Stage
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 4
 Fault Simulation

Predicts the behavior of faulty circuits
 As a consequence of inevitable fabrication
process imperfections

An important tool for test and diagnosis

 Estimate fault coverage
 Fault simulator
 Test compaction
 Fault diagnosis

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 5
 Logic and Fault Simulation

Introduction

Simulation models

Logic simulation

Fault simulation

Concluding remarks

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 6
 Gate-Level Network

The interconnections of logic gates

A H
G2

G4 K
L

B J
G1 G3
C E F

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 7
 Sequential Circuits
x1 z1

The outputs depend on x2 z2
both the current and Combinational
past input values xn Logic zm

y1 Y1
y2 Y2
xi: primary input (PI)

zi: primary output (PO) yl Yl

yi: pseudo primary input (PPI)

Flip-Flops
Yi: pseudo primary output (PPO)

clock
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 8
 A Positive Edge-Triggered D-FF
PresetB

PresetB

Q
D Q
DFF
Clock QB
Clock QB

ClearB

ClearB

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 9
 Logic Symbols

The most commonly used are 0, 1, u and Z

1 and 0
 true and false of the two-value Boolean algebra

u
 Unknown logic state (maybe 1 or 0)

Z
 High-impedance state
 Not connected to Vdd or ground

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 10
 Ternary Logic

Three logic symbols: 0, 1, and u

AND 0 1 u OR 0 1 u NOT 0 1 u
0 0 0 0 0 0 1 u 1 0 u
1 0 1 u 1 1 1 1
u 0 u u u u 1 u

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 11
 Information Loss of Ternary Logic

Simulation based on ternary logic is pessimistic

A signal may be reported as unknown when its value
can be uniquely determined as 0 or 1
1
A u
G2 u
G4 K
u
B u
G1 G3
C u
0

1
A 0 or 1
G2 0
G4 K
0 or 1
B 1 or 0
G1 G3
C 0 or 1
0
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 12
 High-Impedance State Z

Tri-state gates permit several gates to time-share a
common wire, called bus

A signal is in high-impedance state if it is connected
to neither Vdd nor ground
 xi if ei = 1
oi = 
Z if ei = 0
e1
o1
x1 G1
pull-up
or down
e2
o2 y
x2 G2
DFF
Resolution
e3 Function
o3
x3 G3
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 13
 Resolving Bus Conflict

Bus conflict occurs if at least two drivers drive
the bus to opposite binary values

To simulate tri-state bus behavior, one may
insert a resolution function for each bus wire
 May report only the occurrence of bus conflict
 May utilize multi-valued logic to represent
intermediate logic states (including logic signal
values and strengths)

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 14
 Logic Element Evaluation Methods

Choice of evaluation technique depends on
 Considered logic symbols
 Types and models of logic elements

Commonly used approaches

 Truth table based
 Input scanning
 Input counting
 Parallel gate evaluation

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 15
 Truth Table Based Gate Evaluation

The most straightforward and easy to
implement
 For binary logic, 2n entries for n-input logic
element
 May use the input value as table index
 Table size increases exponentially with the
number of inputs

Could be inefficient for multi-valued logic
 A k-symbol logic system requires a table of 2mn
entries for an n-input logic element
– m = log2k
– Table indexed by mn-bit words

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 16
 Input Scanning

The gate output can be determined by the
types of inputs
 If any of the inputs is the controlling value, the
gate output is c⊕i
 Otherwise, if any of the inputs is u, the gate output
is u
 Otherwise, the gate output is c'⊕i
Table 3.2: The c (controlling) and
i (inversion) values of basic gates
c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 17
 Input Scanning - cont’d
Start

u_in ← false

Next no u_in is no
return c’⊕i
input? true?
yes yes

u_in ← true v ← next input return u

yes
no no yes
v == u? v == c? return c⊕i

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 18
 Input Counting

Keep the counts of controlling and unknown
inputs
 c_count: the number of controlling inputs
 u_count: the number of unknown inputs

Update counts during logic simulation
 Example:
One input of a NAND switches from 0 to u
– c_count --
– u_count ++

Same rules as input scanning used to
evaluate gate outputs
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 19
 Parallel Gate Evaluation

Exploit the inherent concurrency in the host computer
 A 32-bit computer can perform 32 logic operations in parallel

1 0 0 1
A 1 0 0 0
G2
H

G4 K
0 1 1 0
1 1 1 0
B E J
G1 G3
C 1 1 1 0 0 0 0 1
0 0 1 0

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 20
 Multi-Valued Parallel Gate Evaluation

Use ternary logic as example
 Assume
– w-bit wide word
– Symbol encoding: v0 = (00), v1 = (11), vu = (01)
 Associate with each signal X two words, X1 and X2
– X1 stores the first bits and X2 the second bits of the w
copies of the same signal
 AND and OR operations are realized by applying
the same bitwise operations to both words
– C = OR(A,B) ==> C1 = OR(A1,B1) and C2 = OR(A2,B2)
 Complement requires inversion
– C = NOT(A) ==> C1 = NOT(A2) and C2 = NOT(A1)
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 21
 Timing Models

Transport delay

Inertial delay

Wire delay

Function element delay model

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 22
 Transport Delay

The time duration it takes for the effect of gate input
changes to appear at gate outputs
A
G F
B=1

(a) Nominal delay A 1 2

dN = 2 ns F 2

(b) Rise/fall delay

A 1 1.5
dr = 2 ns
df = 1.5 ns F 2

2
(c) Min-max delay A 1.5 1
dmin = 1 ns
F
dmax = 2 ns
1
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 23
 Inertial Delay

The minimum input pulse duration necessary for the
output to switch states
A
G F dI = 1.5 ns, dN = 3 ns
B=1

(a) Pulse duration less than dI

A 1
F

(b) Pulse duration longer than dI

A 2 3
F 3 2

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 24
 Wire Delay

Wires are inherently resistive and capacitive

It takes finite time for a signal to propagate along a
wire

p q

b
da-b

a c
da-c
d
da-d

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 25
 Functional Element Delay Model

For more complicated functional elements like flip-
flops

Table 3.3: The D flip-flop I/O delay model

Present
Input condition Outputs Delays (ns)
state
D Clock PresetB ClearB q Q QB to Q to QB Comments
X X ↓ 0 0 ↑ ↓ 1.6 1.8 Asynchronous preset
X X 0 ↓ 1 ↓ ↑ 1.8 1.6 Asynchronous clear
1 ↑ 0 0 0 ↑ ↓ 2 3 Q: 0→1
0 ↑ 0 0 1 ↓ ↑ 3 2 Q: 1→0
X Š indicates donÕtcare

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 26
 Logic and Fault Simulation

Introduction

Simulation models

Logic simulation

Fault simulation

Concluding remarks

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 27
 Compiled Code Simulation

Translate the logic start

network into a series of

machine instructions that next no
end
vector?
model the gate functions yes

and interconnections read in next input

vector v

run compiled code

with input v in host
machine

output simulation
results
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 28
 Compiled Code Generation Flow
gate-level
description

logic optimization

logic levelization

code generation

compiled
code

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 29
 Logic Optimization

Enhance the simulation efficiency

before optimization after optimization

1 A
(a) A
B B

(b) A A

A
(c) 0
1

(d) A A

(e) A A
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 30
 Logic Levelization

Determine the order of gate evaluations
start

assign level 0 to
all PI’s

put all PI fanout

gates in Q

Q no pop next gate g append g’s fanout

empty? from Q gates to Q
yes
1. l = maximum of
no ready to yes g’s driving gate
end append g to Q
levelize g? levels
2. assign l+1 to g
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 31
 Example
A
G2
G4 K

B Table 3.4: The levelization process of circuit

G1 G3 step A B C G1 G2 G3 G4 Q
C
0 0 0 0 <G2, G1>
1 0 0 0 <G1, G2>
2 0 0 0 1 <G2, G3>
3 0 0 0 1 2 <G3, G4>
4 0 0 0 1 2 2 <G4>
5 0 0 0 1 2 2 3 <>

The following orders are produced

 G1 => G2 => G3 => G4
 G1 => G3 => G2 => G4

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 32
 Code Generation

High-level programming language source
code
 Easier to debug
 Can be ported to any target machine that has the
compiler
 Limited in applications due to long compilation
times

Native machine code
 Generate the target machine code directly
 Higher simulation efficiency
 Not as portable
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 33
 Code Generation - cont’d

Interpreted code
 The target machine is a software emulator
 The codes are interpreted and executed one at a
time
 Best portability and maintainability
 Reduced performance

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 34
 Event-Driven Simulation

Event: the switching of a signal’s value

An event-driven simulator monitors the occurrences
of events to determine which gates to evaluate

0→1
A H: 0 → 1
G2

G4 K: 1 → 0

0→1
B
G1 G3
C E: 1 J: 0
1

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 35
 Zero-Delay Event-Driven Simulation

Gates with events at their inputs are places in the
event queue Q
start

read in initial
condition
no Q yes
empty?
evaluate next gate next no
end
g from Q vector?
yes
output no read in new input
change? vector
yes
put g’s fanout put active Pis’
gates in Q fanout gates in Q

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 36
 Nominal-Delay Event-Driven Simulation

Need a smarter scheduler than the event queue
 Not only which gates but also when to evaluate

t0 p, vp+

t1 q, vq+ r, vr+ s, vs+

ti w, vw+

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 37
 Two-Pass Event-Driven Simulation
start

yes
no Next time LE yes LA
end
stamp? empty? empty?
yes no no
get next time get next event get next gate g
stamp t (g, vg+) from LE from LA

retrieve current yes evaluate g and

event list LE vg+==vg? schedule (g, vg+)
at t+delay(g)
no

1. vg ← vg+
2. append g’s
fanout gates to
activity list LA
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 38
 Example A
G2
H
G4 K

B E J
G1 G3
C

Table 3.5: Two-pass event-driven simulation

Time LE LA Scheduled events
0 {(A,1)} {G2} {(H,1,8)}
2 {(C,0)} {G1} {(E,1,10)}
4 {(B,0)} {G1} {(E,0,12)}
8 {(A,0),(H,1)} {G2,G4} {(H,0,16),(K,0,14)}
10 {(E,1)}
12 {(E,0)} { G2,G3} {(H,0,20),(J,1,16)}
14 {(K,0)}
16 {(H,0),(J,1)} {G4} {(K,0,22)}
20 {(H,0)}
22 {(K,0)}
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 39
 Example - cont’d
A

0 2 4 6 8 10 12 14 16 18 20 22 24

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 40
 Compiled-Code vs. Event-Driven Simulation

Compiled-code
 Cycle-based simulation
 High switching activity circuits
 Parallel simulation
 Limited by compilation times

Event-driven
 Implementing gate delays and detecting hazards
 Low switching activity circuits
 More complicated memory management

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 41
 A H
Hazards G2
G4 K

Unwanted transient B E J
pulses or glitches G1 G3
C

0 1 2 3 4 5 6 7 8 9 10 11
42
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 42
 Types of Hazards

Static or dynamic
 A static hazard refers to the transient pulse on a signal line
whose static value does not change
 A dynamic hazard refers to the transient pulse during a 0-to-
1 or 1-to-0 transition

1 or 0

Static 1-hazard Static 0-hazard Dynamic 1-hazard Dynamic 0-hazard

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 43
 Static Hazard Detection

Let V 1 = v11v12 Lv1n and V 2 = v12v 22 Lv n2 be two
consecutive input vectors
+ + + +

Add a new vector V = v1 v 2 Lv n according to
the following rule
v 1
if v 1
= v 2
v i+ =  i i
1
i
2
 u if v i ≠ v i

Simulate the V1V+V2 sequence using ternary
logic

Any signal that is 1u1 or 0u0 indicates the
possibility of a static hazard.
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 44
 Multi-Valued Logic for Hazard Detection

6-valued logic for static hazard detection

8-valued logic for dynamic hazard detection

Worst case analysis
Table 3.6: Multi-valued logic for hazard detection
Symbol Interpretation 6-valued logic 8-valued logic
0 Static 0 {000} {0000}
1 Static 1 {111} {1111}
R Rise transition {001,011}=0u1 {0001,0011,0111}
F Fall transition {100,110}=1u0 {1110,1100,1000}
0* Static 0-hazard {000,010}=0u0 {0000,0100,0010,0110}
1* Static 1-hazard {111,101}=1u1 {1111,1011,1101,1001}
R* Dynamic 1-hazard {0001,0011,0101,0111}
F* Dynamic 0-hazard {1000,1010,1100,1110}
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 45
 Logic and Fault Simulation

Introduction

Simulation models

Logic simulation

Fault simulation

Concluding remarks

46
VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 46
 Fault Simulation

Introduction

Serial Fault Simulation

Parallel Fault Simulation

Deductive Fault Simulation

Concurrent Fault Simulation

Differential Fault Simulation

Fault Detection

Comparison of Fault Simulation Techniques

Alternative to Fault Simulation

Conclusion

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 47
 Introduction

What is fault simulation?
 Given
– A circuit
– A set of test patterns
– A fault model
 Determine
– Faulty outputs
– Undetected faults
– Fault coverage

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 48
 Time Complexity

Proportional to
 n: Circuit size, number of logic gates
 p: Number of test patterns
 f : Number of modeled faults

Since f is roughly proportional to n, the overall

time complexity is O(pn2)

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 49
 Serial Fault Simulation

First, perform fault-free logic simulation on the
original circuit
 Good (fault-free) response

For each fault, perform fault injection and

logic simulation
 Faulty circuit response

50
VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 50
 start

Algorithm Flow
F ← collapsed fault list

fault-free simulation for

all patterns

no next
end
fault?
yes
1. get next fault f from F
2. reset pattern counter

next no
pattern?
yes
1. get next pattern p
2. fault simulation for p

no mis- yes
delete f from F
match? 51
VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 51
 Example
A H
f: A stuck-at 1 G2

G4 K
L

B g: J stuck-at 0
G1 G3
C E F J

Pat. # Input Internal Output

A B C E F L J H Kgood Kf Kg

P1 0 1 0 1 1 1 0 0 1 0 1
P2 0 0 1 1 1 1 0 0 1 0 1
P3 1 0 0 0 0 0 1 0 0 0 1

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 52
 Fault Dropping

Halting simulation of the detected fault

Example
 Suppose we are to simulate P1, P2, P3 in order
 Fault f is detected by P1
 Do not simulate f for P2, P3

For fault grading
 Most faults are detected after relatively few test
patterns have been applied

For fault diagnosis
 Avoided to obtain the entire fault simulation results

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 53
 Pro and Con

Advantages
 Easy to implement
 Ability to handle a wide range of fault models
(stuck-at, delay, Br, …)

Disadvantages
 Very slow

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 54
 Parallel Fault Simulation

Exploit the inherent parallelism of bitwise
operations

Parallel fault simulation [Seshu 1965]
 Parallel in faults

Parallel pattern fault simulation [Waicukauski
1986]
 Parallel in patterns

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 55
 Parallel Fault Simulation

Assumption
 Use binary logic: one bit is enough to store logic
signal
 Use w-bit wide data word

Parallel simulation
 w-1 bit for faulty circuits
 1 bit for fault-free circuit

Process faulty and fault-free circuit in parallel
using bitwise logic operations

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 56
 Fault Injection
A H
f: A stuck-at 1 G2

G4 K
L

B g: J stuck-at 0
G1 G3
C E F J

A
Gf H
0 1 0 G2

G4 K
L

B J
G1 G3
C E F Gg
0 1 0
57
VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 57
 Example
Input Internal Output
Pat #
A Af B C E F L J Jg H K

FF 0 0 1 0 1 1 1 0 0 0 1

P1 f 0 1 1 0 1 1 1 0 0 1 0

g 0 0 1 0 1 1 1 0 0 0 1

FF 0 0 0 1 1 1 1 0 0 0 1

P2 f 0 1 0 1 1 1 1 0 0 1 0

g 0 0 0 1 1 1 1 0 0 0 1

FF 1 1 0 0 0 0 0 1 1 0 0

P3 f 1 1 0 0 0 0 0 1 1 0 0

g 1 1 0 0 0 0 0 1 0 0 1

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 58
 Pro and Con

Advantages
 A large number of faults are detected by each
pattern when simulating the beginning of test
sequence

Disadvantages
 Only applicable to the unit or zero delay models
 Faults cannot be dropped unless all (w-1) faults
are detected

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 59
 Parallel Pattern Fault Simulation

Parallel pattern single fault propagation
(PPSFP)

Parallel pattern
 With a w-bit data width, w test patterns are packed
into a word and simulated for the fault-free or
faulty circuit

Single fault
 First, fault-free simulation
 Next, for each fault, fault injection and faulty circuit
simulation
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 60
 start

Algorithm Flow
F ← collapsed fault list

no new w
end
patterns?
yes
1. apply next w patterns
2. Ogood ← good circuit outputs

next no F
fault? empty?
yes yes
get next fault f from F end
delete f from F
1. remove last fault
2. inject fault f
no
yes Of ← faulty circuit outputs
Of == Ogood? 61
of w patterns
VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 61
 Example
A H
f: A stuck-at 1 G2

G4 K
L

B g: J stuck-at 0
G1 G3
C E F J

Input Internal Output

A B C E F L J H K
P1 0 1 0 1 1 1 0 0 1
Fault
P2 0 0 1 1 1 1 0 0 1
Free
P3 1 0 0 0 0 0 1 0 0
P1 1 1 0 1 1 1 0 1 0
f P2 1 0 1 1 1 1 0 1 0
P3 1 0 0 0 0 0 1 0 0
P1 0 1 0 1 1 1 0 0 1
g P2 0 0 1 1 1 1 0 0 1
P3 1 0 0 0 0 0 0 0 1
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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 62
 Pro and Con

Advantages
 Fault is dropped as soon as detected
 Best for simulating test patterns that come later,
where fault dropping rate per pattern is lower

Disadvantages
 Not suitable for sequential circuits

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 63
 Deductive Fault Simulation

[Armstrong 1972]

Based on logic reasoning rather than
simulation

Fault list attached with signal x denoted as Lx
 Set of faults causing x to differ from its fault-free
value

Fault list propagation
 Derive the fault list of a gate output from those of
the gate inputs based on logic reasoning

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 64
 Fault List Propagation Rules
c i
c : controlling value
AND 0 0
i : inversion value
OR 1 0
I : set of gate inputs
NAND 0 1
z : gate output
S : inputs holding controlling value NOR 1 1

All gate inputs hold non-controlling value

 
Lz = ∪ L j ∪ {z /(c ⊕ i) } (3.1)
 j ∈I 

At least one input holds controlling value
Lz = [( ∩ L j ) − ( ∪ L j )]∪{z /c ⊕ i'} (3.2)
j ∈S j ∈I −S

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 65
 Algorithm Flow
start

F ← collapsed fault list

no next
end
pattern?
yes
apply next pattern

1. fault-free simulation
2. propagate fault list
no
delete detected faults yes
F empty? end
from F

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 66
 Example

P1
LK = LH ∪ LJ ∪ {K / 0} by Eq. (3.1)

LA = {A/1} {A/1, H/1}

A H
0 G2
0 1
G4 K
1 L {A/1, H/1, B/0,
{B/0, E/0, L/0} E/0, F/0, J/1, K/0}
LB = {B/0}
1
B 1 1 0
G1 G3
C E F J
0 {B/0, E/0} {B/0, E/0, F/0} {B/0, E/0, F/0, J/1}
LC = {C/1}

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VLSI Test Principles and Architectures
EE141 Ch. 3 - Logic & Fault Simulation - P. 67
 Example (cont’d)

P2

0
A H
G2
0 1
G4 K
1 L {C/0}
{C/0}
LB = {B/1}
0
B 1 1 0
G1 G3
C E F J
1 {C/0} {C/0} {C/0}
LC = {C/0}

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 Example (cont’d)

P3
LK = (LJ − L H ) ∪ {K /1} by Eq. (3.2)

LA = {A/0} {B/1, C/1, E/1, L/1}

A H
1 G2
0 0
G4 K
0 L {F/1, J/0, K/1}
{B/1, E/1, L/1}
LB = {B/1}
0
B 0 0 1
G1 G3
C E F J
0 {B/1, C/1, E/1} {B/1, C/1, E/1, F/1} {B/1, C/1, E/1, F/0, J/0}
LC = {C/1}

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 Pro and Con

Advantages
 Very efficient
 Simulate all faults in one pass

Disadvantages
 Not easy to handle unknowns
 Only for zero-delay timing model
 Potential memory management problem

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 Concurrent Fault Simulation

[Ulrich 1974]

Simulate only differential parts of whole circuit

Event-driven simulation with fault-free and
faulty circuits simulated altogether

Concurrent fault list for each gate
 Consist of a set of bad gates
– Fault index & associated gate I/O values
 Initially only contains local faults
 Fault propagate from previous stage
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 Good Event and Bad Event

Good event
 Events that happen in good circuit
 Affect both good gates and bad gates

Bad event
 Events that occur in the faulty circuit of
corresponding fault
 Affect only bad gates

Diverge
 Addition of new bad gates

Converge
 Removal of bad gates whose I/O signals are the
same as corresponding good gates
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 Algorithm Flow start

F ← collapsed fault list

next no
end
pattern?
yes
apply next pattern

1. analyze events at gate inputs

2. execute events
3. compute events at gate outputs

yes more
events?
yes no
no F delete detected faults
end
empty? from F
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 Example

P1

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 Example (cont’d)

P2

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 Example (cont’d)

P3

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 Pro and Con

Advantages
 Efficient

Disadvantages
 Potential memory problem
– Size of the concurrent fault list changes at run time

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 Differential Fault Simulation

[Cheng 1989]

Combines the merits of two techniques
 Concurrent fault simulation
 PPSFP

Idea
 Simulate in turn every fault circuit
 Track only difference between faulty circuit and
last simulated one
 Inject differences as events
 Easily implemented by event-driven simulator

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 Simulation Sequence

P1 P2 … Pi Pi+1 … Pn

Good G1 G2 … Gi Gi+1 … Gn

f1 F1,1 F1,2 … F1,i F1,i+1 … F1,n

f2 F2,1 F2,2 … F2,i F2,i+1 … F2,n

. . . … . . … .

fk Fk,1 Fk,2 … Fk,i Fk,i+1 … Fk,n

fk+1 Fk+1,1 Fk+1,2 … Fk+1,i Fk+1,i+1 … Fk+1,n

. . . … . . … .

fm Fm,1 Fm,2 … Fm,i Fm,i+1 … Fm,n

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EE141 Ch. 3 - Logic & Fault Simulation - P. 79
 start

Algorithm Flow F ← collapsed fault list

no next
end
pattern?
yes
restore good circuit state

1. apply next pattern

2. Ogood ← good circuit outputs
no
next no
F empty?
fault?
yes yes
delete f from F get next fault f end

no 1. restore faulty circuit state

yes 2. remove last fault
Of == Ogood? 3. inject fault f
4. Of ← fault circuit outputs
5. store gate difference 80
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 Pro and Con

Advantages
 Suitable for sequential fault simulation

Disadvantages
 Order of events caused by faulty sites is NOT the
same as the order of the timing of their occurrence

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 Fault Detection

Hard detected fault
 Outputs of fault-free and faulty circuit are different
– 1/0 or 0/1
– No unknowns, no Z

Potentially detected fault

 Whether the fault is detected is unclear
 Example: stuck-at-0 on enable signal of tri-state
buffer

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 Fault Detection (cont’d)

Oscillation faults
 Cause circuit to oscillate
 Impossible to predict faulty circuit outputs

Hyperactive faults
 Catastrophic fault effect
– Fault simulation is time and memory consuming
 Example: stuck-at fault on clock
 Usually counted as detected
– Save fault simulation time

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 Comparison of Fault Simulation Techniques (1)

Speed
 Serial fault simulation: slowest
 Parallel fault simulation: O(n3), n: num of gates
 Deductive fault simulation: O(n2)
 Concurrent fault is faster than deductive fault simulation
 Differential fault simulation: even faster than concurrent fault
simulation and PPSFP

Memory usage
 Serial fault simulation, parallel fault simulation: no problem
 Deductive fault simulation: dynamic allocate memory and
hard to predict size
 Concurrent fault simulation: more severe than deductive fault
simulation
 Differential fault simulation: less memory problem than
concurrent fault simulation
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 Comparison of Fault Simulation Techniques (2)

Multi-valued fault simulation to handle
unknown (X) and/or high-impedance (Z)
 Serial fault simulation, concurrent fault simulation,
differential fault simulation: easy to handle
 Parallel fault simulation: difficult

Delay and functional modeling capability
 Serial fault simulation: no problem
 Parallel fault simulation, deductive fault simulation:
not capable
 Concurrent fault simulation: capable
 Differential fault simulation: capable
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 Comparison of Fault Simulation Techniques (3)

Sequential circuit
 Serial fault simulation, parallel fault simulation,
concurrent fault simulation, differential fault
simulation: no problem
 PPSFP: difficult
 Deductive fault simulation: difficult due to many
unknowns

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 Comparison of Fault Simulation Techniques (4)

PPSFP and concurrent fault simulation are
popular for combinational (full-scan) circuits

Differential fault simulation and concurrent
fault simulation is popular for sequential
circuits

Multiple-pass fault simulation
 Prevent memory explosion problem

Distributed fault simulation
 Reduce fault simulation time

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 Alternative to Fault Simulation

Toggle Coverage

Fault Sampling

Critical Path Tracing

Statistical Fault Analysis

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 Toggle Coverage

Popular for estimating fault grading

Only one single fault-free simulation

A net is toggled if
 Relaxed def: its value has been set to zero and
one during fault-free simulation
 Stringent def: it has both a zero-to-one transition
and a one-to-zero transition during fault-free
simulation

Toggle coverage
number of toggled nets
number of total nets in the circuit

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 Fault Sampling

[Butler 1974]

Simulate only a sampled group of faults

Error depends on two factors
 Sample size
 The sample is biased or not

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 Critical Path Tracing

[Abramovici 1984]

Critical value
 For net x, stuck-at v’ can be detected by test
pattern t ↔ Net x has critical value v

Critical path
 Path consisting of nets with critical value

Special attention required for fanout
reconvergence

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 Example

P1

0
A H
G2
0

1 1
L
G4 K

1
1 1 0
B
G1 G3
C E F J
0

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 Example (cont’d)

P3

1
A H
G2
0

0 0
L
G4 K

0
0 0 1
B
G1 G3
C E F J
0

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 Statistical Fault Analysis (STAFAN)

[Jain 1985]

Use probability theory to estimate expected
value of fault coverage

Detectability of fault f (df)
 1-controllability, C1(x)
 0-controllability, C0(x)
 Observability, O(x)
 Sensitization probability, S(x)

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 Summary

Fault simulation is very important for
 ATPG
 Diagnosis
 Fault grading

Popular techniques
 Serial, Parallel, Deductive, Concurrent, Differential

Requirements for fault simulation
 Fast speed, efficient memory usage, modeling
functional blocks, sequential circuits

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 Logic and Fault Simulation

Introduction

Simulation models

Logic simulation

Fault simulation

Concluding remarks

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 Conclusions

Logic and fault simulations, two fundamental
subjects in testing, are presented

Into the nanometer age, advanced
techniques are required to address new
issues
 High performance
 High capacity
 New fault models

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