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ECE 429 Syllabus

The document provides information about the ECE 429 - Introduction to VLSI Design course including the instructor, prerequisites, meeting times, textbook, course objectives to teach CMOS VLSI design from system to circuit level, topics covered, grading breakdown, lab assistants, homework and exam policies.

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125 views

ECE 429 Syllabus

The document provides information about the ECE 429 - Introduction to VLSI Design course including the instructor, prerequisites, meeting times, textbook, course objectives to teach CMOS VLSI design from system to circuit level, topics covered, grading breakdown, lab assistants, homework and exam policies.

Uploaded by

Raja
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 429 - Introduction to VLSI Design

Fall 2012

Instructor: Professor Erdal Oruklu


Office: 301 Siegel Hall
Phone: 312 567-8814
E-Mail: [email protected]

Prerequisite: ECE 218 and ECE 311:


Familiarity with circuits, logic and digital system design.
Experience with CAD tools and UNIX is a plus.

Class Time: Monday Wednesday: 1:50 PM - 3:05 PM

Class Location: Life Sciences - Room 111

Office Hrs: Monday and Wednesday: 3:00 PM - 4:00 PM at SH-301

Class Home Page: Blackboard

Required Textbook: “CMOS VLSI DESIGN: A Circuits and Systems


Perspective” (4th Edition) Neil H.E. Weste, and David
Harris, Pearson/Addison-Wesley, 2011.
ISBN: 0-321-54774-8

Course Objective: To give students a clear understanding of the


fundamental concepts of modern CMOS VLSI design.
Students will learn the design of complex and high
performance CMOS systems from system level to circuit
level.

Topics Covered: MOS transistors, static and dynamic behavior, stick


diagrams, MOS circuit fabrication, design rules,
resistance and capacitance extraction, scaling, logical
effort, combinational and sequential design, data-path
and control unit design, clocking schemes, memory
design. CAD synthesis techniques, floorplanning and
layout.

Grading: Homeworks 5%
Midterm Exam: 25%
Final Exam: 40%
LABs and Project: 30%
Lab/Teaching Assistants: Cecilia Garcia Martin
E-Mail: [email protected]
Office hr: TBD

Xuanxing Xiong
E-Mail: [email protected]
Office hr: TBD

Homework Policy: Homework is due at the start of class. Late


homework will not be accepted. Working
together on homework is encouraged, but
copying assignments will call for disciplinary
action.

Exam Policy: Makeup exams will not be given, except for


extraordinary reasons. The final is comprehensive.

Reference Books: “Digital Integrated Circuits - A Design


Perspective, 2nd Edition” by Jan M. Rabaey, Anantha
Chandrakasan, and Borivoje Nikolic, Prentice Hall,
2003.
ISBN:0130909963

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