Scribd
Upload
245 views

Multiplexer 4 Inputs and Test Bench

The document contains Verilog code for implementing multiplexers and demultiplexers using different techniques like if-else statements, case statements, instantiating gates, and dataflow modeling. It also includes code for a D flip-flop with synchronous reset, set, and clock enable and a testbench for a 1-to-4 demultiplexer.

Uploaded by

sagar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
245 views

Multiplexer 4 Inputs and Test Bench

The document contains Verilog code for implementing multiplexers and demultiplexers using different techniques like if-else statements, case statements, instantiating gates, and dataflow modeling. It also includes code for a D flip-flop with synchronous reset, set, and clock enable and a testbench for a 1-to-4 demultiplexer.

Uploaded by

sagar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

Multiplexer 4 inputs and test bench

module mux1( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

wire q;
wire[1:0] select;
wire[3:0] d;

assign q = d[select];

endmodule

module mux_tb;

reg[3:0] d;

reg[1:0] select;

wire q;

integer i;

mux1 my_mux( select, d, q );


initial

begin

#1 $monitor("d = %b", d, " | select = ", select, "


| q = ", q );

for( i = 0; i <= 15; i = i + 1)

begin

d = i;

select = 0; #1;

select = 1; #1;

select = 2; #1;

select = 3; #1;

$display("d=%b,select=%b,q=%b", d,select,q);

end

end

endmodule

if and always
module mux3( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

reg q;
wire[1:0] select;
wire[3:0] d;

always @( select or d )
begin
if( select == 0)
q = d[0];

if( select == 1)
q = d[1];

if( select == 2)
q = d[2];

if( select == 3)
q = d[3];
end

endmodule

case
module mux4( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

reg q;
wire[1:0] select;
wire[3:0] d;

always @( select or d )
begin
case( select )
0 : q = d[0];
1 : q = d[1];
2 : q = d[2];
3 : q = d[3];
endcase
end

endmodule

// Verilog code for Multiplexer implementation using conditional statement.


module mux5( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

wire q;
wire[1:0] select;
wire[3:0] d;
assign q = ( select == 0 )? d[0] : ( select == 1 )? d[1] : ( select == 2 )?
d[2] : d[3];

endmodule

// Verilog code for Multiplexer implementation in dataflow


level.
module mux6( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

reg q;
wire[1:0] select;
wire[3:0] d;

always @( select or d)
begin
q = ( ~select[0] & ~select[1] & d[0] )
| ( select[0] & ~select[1] & d[1] )
| ( ~select[0] & select[1] & d[2] )
| ( select[0] & select[1] & d[3] );
end

endmodule

// Verilog code for Mux implementation using instantiating


gates.
module mux7( select, d, q );

input[1:0] select;
input[3:0] d;
output q;

wire q, q1, q2, q3, q4, NOTselect0, NOTselect1;


wire[1:0] select;
wire[3:0] d;

not n1( NOTselect0, select[0] );


not n2( NOTselect1, select[1] );

and a1( q1, NOTselect0, NOTselect1, d[0] );


and a2( q2, select[0], NOTselect1, d[1] );
and a3( q3, NOTselect0, select[1], d[2] );
and a4( q4, select[0], select[1], d[3] );

or o1( q, q1, q2, q3, q4 );

endmodule

D flip flop with Synchronous Reset,Set and Clock Enable:

module DFF(
Clk,
CE,
reset,
D,
set,
Q
);

//list the inputs


input Clk;
input CE;
input reset;
input D;
input set;
//list the outputs
output Q;
//Internal variables
reg Q;

//flip flop state is affected only on postive edge of clock


always @(posedge(Clk))
begin
if(Clk == 1)
begin
if (reset == 1) //check for active high reset
Q = 0;
else if(set == 1) //check for set
Q = 1;
else if (CE == 1) //check if clock is enabled
Q = D;
end
end

endmodule
1:4 Demux:

//Verilog module for 1:4 DEMUX


module demux1to4(
Data_in,
sel,
Data_out_0,
Data_out_1,
Data_out_2,
Data_out_3
);

//list the inputs and their sizes


input Data_in;
input [1:0] sel;
//list the outputs and their sizes
output Data_out_0;
output Data_out_1;
output Data_out_2;
output Data_out_3;
//Internal variables
reg Data_out_0;
reg Data_out_1;
reg Data_out_2;
reg Data_out_3;

//always block with Data_in and sel in its sensitivity list


always @(Data_in or sel)
begin
case (sel) //case statement with "sel"
//multiple statements can be written inside each case.
//you just have to use 'begin' and 'end' keywords as shown below.
2'b00 : begin
Data_out_0 = Data_in;
Data_out_1 = 0;
Data_out_2 = 0;
Data_out_3 = 0;
end
2'b01 : begin
Data_out_0 = 0;
Data_out_1 = Data_in;
Data_out_2 = 0;
Data_out_3 = 0;
end
2'b10 : begin
Data_out_0 = 0;
Data_out_1 = 0;
Data_out_2 = Data_in;
Data_out_3 = 0;
end
2'b11 : begin
Data_out_0 = 0;
Data_out_1 = 0;
Data_out_2 = 0;
Data_out_3 = Data_in;
end
endcase
end

endmodule

Testbench for Demux:

module tb_demux;

// Inputs
reg Data_in;
reg [1:0] sel;

// Outputs
wire Data_out_0;
wire Data_out_1;
wire Data_out_2;
wire Data_out_3;

// Instantiate the Unit Under Test (UUT)


demux1to4 uut (
.Data_in(Data_in),
.sel(sel),
.Data_out_0(Data_out_0),
.Data_out_1(Data_out_1),
.Data_out_2(Data_out_2),
.Data_out_3(Data_out_3)
);

initial begin
//Apply Inputs
Data_in = 1;
sel = 0; #100;
sel = 1; #100;
sel = 2; #100;
sel = 3; #100;
Data_in = 0;
end

endmodule

You might also like