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NAND and NOR Test

The document discusses multi-level implementation of logic functions using NOR and NAND gates. It provides examples of 3-level and 4-level logic functions and shows how to convert their AND-OR schematics into equivalent schematics using only NOR or NAND gates. The key steps are to first draw the AND-OR schematic, then convert it to mixed notation by replacing AND with AND-INVERT and OR with INVERT-OR, and finally redraw the schematic using only NOR or NAND gates by replacing the mixed gates. Bubbles are accounted for by inserting inverters or complementing inputs as needed.

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Yasyr
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158 views

NAND and NOR Test

The document discusses multi-level implementation of logic functions using NOR and NAND gates. It provides examples of 3-level and 4-level logic functions and shows how to convert their AND-OR schematics into equivalent schematics using only NOR or NAND gates. The key steps are to first draw the AND-OR schematic, then convert it to mixed notation by replacing AND with AND-INVERT and OR with INVERT-OR, and finally redraw the schematic using only NOR or NAND gates by replacing the mixed gates. Bubbles are accounted for by inserting inverters or complementing inputs as needed.

Uploaded by

Yasyr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Multi-level Implementation using NOR Gate

Suppose a 4-level function:

F = ( A + B ( C + D )) ( B + D’ )

First, we will draw its schematic using AND, OR, NOT gates.

Notice the OR-AND pattern like two-level implementation. It can be easily converted since the bubble
cancels each other.

Now we will convert it into mixed notation for NOR.

The two bubbles along a single line cancel each other. However, there is a single bubble at the 2 nd
level gate’s input. so we will complement the input B to compensate the bubble.

Now redraw the whole schematic replacing OR-Invert and Invert-AND with NOR gate symbol as
shown in the figure below.

3-Level Implementation & Example using NOR Gate

A 3-level implementation using NOR gate’s Example is given below;

F = ( AB’ + CD’ ) ( A’ + B )
First, we will draw its schematic using AND,OR, NOT gates as given in the figure below.

Now we will convert it into mixed notation for NOR.

The single bubbles at the input line of all first level gates need an inverter or the inputs to be
complimented. The two bubbles along the same line cancel each other.

Now that all the bubbles have been accounted for, we will redraw this schematic by replacing OR-
Invert and Invert-AND with NOR gates as shown in the figure below.
MULTI-LEVEL Implementation using NAND Gate
Schematic having more than two levels of gates is known as a multi-level schematic.

We can implement multi-level SOP expression using NAND gate. The conversion of multi-level
expression into NAND gate has the same method as two-level implementation.

The multi-level expression can be converted into two-level expression but for the sake of realization,
we will implement a multi-level expression.

Suppose a multi-level function be;

F = A ( B + CD ) + BD’

This is a four-level function

First, we will draw its AND-OR schematic

Notice the AND-OR pattern. So it can be easily converted into NAND gates. Now we will convert this
into mixed notation i.e. AND gate will be converted into AND-INVERT and OR will be converted into
INVERT-OR as shown in the figure given below.

Remember double bubbles along a single line cancel each other, and a single bubble along a line
should be compensated by inserting an inverter in that line.

Notice the 3rd line of input B, there is a single bubble. To compensate this bubble, either an inverter
should be added or the input B should be complimented.

Then redraw the whole schematic using all NAND gates by replacing AND-INVERT and INVERT-OR
with NAND gates as shown in the figure below.
Three-level Implementation & Example using NAND Gate
Suppose 3-level function be F = ( AB’+CD’) ( A’+B )

First, we will draw its AND-OR schematic as shown in the figure below;

Then we will convert it into Mixed notation by converting AND into AND-INVERT and OR into INVERT-
OR.

Notice the last two lines with single bubbles. These single bubbles should be compensated by
inserting inverters in those lines or complementing the inputs. The output also contains a single bubble
so an inverter at the output should also be connected to compensate the bubble.

And the last step is to redraw the whole schematic using all NAND gates instead of AND-INVERT and
INVERT-OR as shown in the figure given below.

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