28 DMA Chip 8237A - A Detour Highway in the PC

Besides the CPU, the PC has another chip that accesses the main memory or peripherals on its
own - the 8237A DMA controller chip. Compared with access via the CPU, direct memory
access was already placed in the background in the AT, probably because IBM was unable to
make up its mind and implement a fast-clocked l&bit DMA chip. Instead, the Stone Age era
chips of the K/XT are also used here. Only with RISA and MCA has DMA become interating
again because of the Liz-bit chip employed. But first let us see what’s biding behind the often
neglected and seemingly obscure term DMA.

28.1 Direct Memory Access with beripherals and Memory

Powerful computers with a multitasking operating system in particular use the DMA concept
to free the CPU from simple but time-consuming data transfers. The DMA chip or DMA contmf-
ler establishes a second path between the peripheral’and main memory in a computer system.
Figure 28.1 shows the principles of the direct memory access concept

The CPU transfers data from a peripheral in@ an internal register, and from this register into
the main memory. Of course, the transfer can also be carried out in the opposite direction. The
arrows in Figure 28.1 indicate that this is a Z-step process, where an internal CPU register is
‘always involwcl. If a large data block is to be transferred, the CPU can be occupied for quite
:a long time with this rather trivial job.
Remedial action uses the DMA chip, which establishes a second data path between theperiph-
eraI and main memory. The data transfer is not carried out via an internal register of the DMA
chip, but immediately via the data bus between the peripheral and main memory. The DM.4
controller outputs only the address and bus control signals, thus the Griphera can access main
 DMA Chip 8237A - A Detour Hlghway in the PC 701

memory directly for a read or write-hence the reason for the name DMA. The CPU is therefore
freed from data transfers, and can execute other processes.
The peripherals are usually allocated a DMA channel, which they activate by means of a DMA
request signal (DREQ). The DMA chip responds to this request and carries out data transfer via
this channel. This is useful, for example, when reading a s&or from disk: the CPU initializes
the DMA controller in a suitable manner and issues the corresponding FDC (Floppy Disk
Controller) command. The FD (Floppy Disk) controller moves the read/write head to the in-
tended sector, and activates the read head and the DMA controller. Then the DMA controller
transfers the sedor data into a buffer in the main memory. By means of a hardware interrupt,
the FD controller informs the CPU about the completion of the command. The whole process
between outputting the command to the FDC and the hardware interrupt from the FDC is
carried out by the FDC and the DMA controller without any intervention from the CPU. Mean-
while, the prwzessor has, for example, calculated the shading of a drawing or the makeup of a
:pt page to be printed.
ol- i
Some DMA chips (for example, the 8237A used in PCS) additionally implement a transfer within
In.
main memory, that is, copying a data block to another memory address. Because of the very
powerful i386 i486 and Pentium processors with their 32-bit data bus and the repeatable string
instruction REP MOVSW, this capability is rarely used.

28.2 Standard 8237A DMA Chip

The personal computer normally uses the 8237A or a compatible chip. Also, advanced EISAI
MCA or local-bus PCs follow the original DMA architecture designed for the PC/XT and AT.
@ Thus, the following discussion is valid even today-even when the discrete 8237A chip has been
‘I:,. part of a highly integrated system controller for a long time. Neither port addresses nor the
logical structure are affected by that.

8: z8.2.1 8237A Connections and Signals

% ‘.
$, The original 8237A comes in a 40pin DIP. Its pin assignment scheme is shown in Figure 28.2.
.$. As is the case for other chips, tw, the DMA controller is often integrated together with other
;; functional units (like the 8259A PIC or the 8253/8254 PlTJ into a single LSl chip.

? AO-A3 (I/O)
,to ,, +s 32-35
‘he Thee four connections form a bidirectional address nibble. In the 8237A’s standby state the
is i CPU addresses internal 8237A registers. If the 8237A is active then the four low-order address
lite : bib ire supplied by A&A3.
7.. .

rh-
,IA
,IA
Ai”
702 Chapter 28

ADSTB (0)
Pin.9
The address strobe signal is used to fetch the high-order address byte A&A15 into an external
DMA address latch. The SZ37A activates ADSTB if the high-order address byte AB-A15 is
available on the data bus DBC-DB7.

AEN (0)
Pin 9
The SZ37A provides an address enable signal at thispin to activate the external DMA addrffs
latch. If AEN is at a FSh level, the DMA address latch puts the stored address as address bits
AS-A15 onto the address bus. AEN can also be wed to disable other bus drivers that generate
address bits AS-Al5 on their own, or to deactivate peripheral components.

CLK (1)
Pin 12
This input is supplied with the DMA clock signal. In the PC the DMA chips usually run at
4.77 MHz, and sanetinws at 7.16 MHz.

The CPU activates the chip select signal a to get an access to the internal 8237A registers if
command and data bytes are to be read or written. The data exchange with the CPU is then
carried out via the data bus DLU-DB7. During DMA transfers, the @<“put is disabled by the
8237A both internally and automatically.
 DMA Chip B237A - A Detour Highway in the PC 703

DACKO-DACKJ (0)
Pins 25, 24, 14, 15
An active DMA acknowledge signal DACKx indicates that the DMA channel concerned is
enabled and the corresponding peripheral that issued a DMA request via DREQx is now ser-
viced. Only a single DACKx can be active at a time. The 8237A activatff a line DACKx only _
once it has taken over control of the local bus by means of HRQ and HLDA. The signal polarity .
(active-low or active-high) can be individually programmed with the mode register.

DBO-DB7 (I/O)
Pins 30-26, 23-21
These eight pins form the bidirectional 8237A data bus for read and write accesses to internal
registers or during DMA transfers. In DMA cycles the high-order eight bits of the DMA address
are output to DBO-DB7 and latched into the external DMA address latch with ADSTB. During
the course of memory-memory transfers, the data byte to be transferred is first loaded into the
internal temporary register (memory-DMA half cycle), anb then output again by the temporary
register via DB&DB7 (DMA-memory half cycle).

DREQO-DREQS (1)
pins 19-16
An active DMA request signal DREQx from a peripheral indicate that the device concerned
requests a DMA transfer. For example, a floppy contmller may activate a ORE@ line to carry
11
mt the transfer of read data into main memory. Usually, DREQO has the highest and DREQ3
is the lowest priority. A corresponding DACKx signal from the 8237A acknowledges the request.
Also, the polarity of these signals (acttve-low or activehigh) can be individually programmed
by means of the mode register.

itiF (l/O)
B Pin 36
ts
The end-of-process signal at this bidirectional connection indicates the completion of a DMA
te
transfer. If the count value of the active 8237A channel reaches the value 0, then the 8237A
provides an active EOP signal with a low level to inform the peripheral about the termination
Of the DMA transfer. On the other hand, the peripheral may also pull EOP to a low level to
inform the DMA chip about the early termination of the DMA transfer. This is the case, for
example, if a buffer in the peripheral that requested the DMA service has been emptied by the
at fZ37A and all data has been transferred to main meinory. By the internal as well as the external
B condition, the TC bit in the status register is set, the corresponding request bit is reset, and
the DMA transfer terminated.
. _
HLDA (1)
if pin7
en ,.: The hold acknowledge signal HLDA from the CPU or another busmaster informs the DMA chip
he ::_&d the CPU has released the local bus, and that the 8237A is allowed to take over control to
Wry out a data transfer.
 704 Chapter 28

HRQ (0)
Pin 10
With the hold request signal HRQ, the 8237A DMA chip requests control of the local bus from
the CPU or another busmaster. The CPU responds with an HLDA signal. The 8237A activates
HRQ if a non-masked DREQx signal or a DMA request by software OCCUR.

In the 8237A standby state, the CPU reads an internal register of the DMA chip by pulling the
I/O read signal m to a low level. If the8237A is qtive and controls the data and address bus,
then an active IOR signal indicates that the DMA chip is reading data from a peripheral via a
port address. The IOR signal can be active during a write transfer @ripher&memory).

low (I!O)
Pin2
In the 8237A standby state the CPU
-writes data into an internal register of the DMA chip by
activating the I/O write
- signal IOW. If the 8237A is active and controls the data and address
bus, then an active IOW signal indicates
- that the DMA chip is currently writing data to a
peripheral via a port address. The IOW signal can be active during a read transfer (memory-
peripheral).

MRMR (I/O)
Pin 3
The 8237A uses the memory read signal MEMR to inform the bus contml that data is being
read from main memory. The MEMR signal can be active (that is, low) during a read transfer
or a memo~-lnemoly transfer.

MEhlW (YO)
Pin4
The 8237A uses the memory write signal MEMW to inform the bus control that data is being
written into main memory. The MEMW signal can be active (that is, low) during a write trans.
fer or a memory-memoly transfer.

READY (1)
Pin6
Slow metnor& or peripherals may activate the input signal READY to extend the 8237A read
. .bnd write cy~ies. The 80x84 processors use the sane strategy during accesses to main memory
‘and peripherals.

RESET (1)
Pin 13
By means of a high-level RESET signal, the 8237A is reset.
 DMA Chip 8237A - A Detour Highway I” the PC 705
!a
_
VCC
Pin.9 5, 31
This pin is supplied with the supply voltage (usually +5 V)

GND
Pin 20
This pin is grounded (usually 0 V)

he 28.2.2 Internal Structure and Operation Modes of the 8237A

1%
18 The 8237A is, despite its Limited functions, a rather cornpI& chip, which has 27 internal regista
with a width between four and 16 bits. Table 28.1 lists all registers and their widths. The 8237A
has four independently working DMA channels 03, so the base and current registers are
implemented four times.

by
:55
,a
Y-

.“g
fer

The temporary registers hold the corresponding values for the currently active channel during
i; the course of exea,ting a DMA function. Only one channel may be active at any time, so one
temporary register is sufficient for all four channels. By means of the status register you may
read information concerning the current 8237A status; the remaining registers are for program-
ming the DMA controller. Figure 28.3 shows the 8237A’s internal structure.
The 8237A has two different priority modes for seividng arriving DMA requests: fixed priwity
and rotating priority. With fixed priority channel 0 is assigned the highest and channel 3 the
kwest priority. This means that requests on channel 0 are always sewiced, but on channel 3
they ak serviced ottly if no other channel is active. With rotating priority the DMA requests alp
Serviced in the order of their occurrence. Afterwards, the currently serviced channel is assigned
.: the lowest priority level.
“S From Table 28.1 you can see that the count value registers are 16 bib wide. Thus the 8237A can
2 Carry out a maximum of 64k transfers before a wraparound of the count *is&r wars. How
 706 Chamer 28

many bytes these 64k transfers correspond to depends upon the connectian of the 8237A to the
computer’s data and address bus. How the DMA chip is used in the FK architecture is described
in Part 3. The CPU write a value into the count register which defines the number of DMA
transfers of the channel concerned. The 8237A terminates the DMA transfer for the active chan-
nel when the count register wraps from KlKlh to ffffh. Because, after every transfer, the count
register is decreased by one, the actual number of DMA transfers is equal to the value written
by the CF’U plus one. Thus, 64k transfers can be carried out if you initially Iwd the count
register with the value ffffh.
As soon as the count register reaches the value ffffh, this is called a tminaf count (TO. The end
df the transfers is only reached upon a TC or an egtemal EOP but not if the DREQ signal is
disabled in a demaqd transfer.
If you look at the 8237A pin assignment in Figure 28.2 and compare it to Table 28.1, you can
see that the 8237A address registers are 16 bits wide but the 8237A address bus comprises only
eight bits AO-A7. To save terminals and to accommodate the 8237A in a standard DIP with 40
pins, the designers intended to have an external DMA address k~fch which holds the high-order
address byte AB-A15 of the address registers. However, only a Whit address space is thus
accessible - tm little for a PC. For the complete address a so-called DMA page register is addi-
tionally required, which holds the address bits beyond A15. Figure 28.4 shows this schematically
tpr the 24-bit AT address bus, which serves the complete 16 Mbyte address space of the 80286.
. .
he DMA address latch is an external chip loaded by the 8237A with the high-order addrffs
byte in the address register. For this purpose, the 8237A puts address bits A&Al5 onto data bus
DBC-DB7 and activates the AD5TB signal. The DMA address latch then fetches and latches the
.&bit address onto the data bus. Thus the DMA chip need only provide the lomwrder address
byte via its address bus AO-A7.
 8 IA Chip 8237A - A Detour HIghway in the PC 707

ae
?d
A
n-
“t
en
“t

,d he DMA page register, on the other hand, is loaded by the CPU and accommcdates the
is idress bits beyond A15. Each channel has its own page rqjster, which is activated according
) the active DMA channel. In a PC/XT with its X-bit addras bus, only a 4-bit page register
therefore necessary, bat an AT with a fully quipped 16 Mbyte memory requires an &bit
a” zgtster. Motherboards with i386, i486 and Pentium pmsors that support a physical DMA
dY ddrms space of more than 16 Mbytes have an additional DMA page register for every channel,
40 rhich holds the necessary address bits AZ4 and beyond. Figure 28.5 shows the scheme for DMA
le1 Idressing.
us
di- Blmuse of the addressing structure with DMA page registers, the address space is physically
ditided into pages (or segments, if you like) of 64 kbytes each for E-bit channels O-3, or into
I’Y
86. Plge$ of 128 kbytes each for l&bit channels 5-7. Thus the page size is 64 kbytes for S-bit chan-
“6 ?ls @3 and 123 kbytes for %-bit channels 5-7. Within these pages, the DMA address latch and
th me address bits AO-A7 from the 8237A indicate the offset. The DMA address cannot go beyond
th me current page. If, for instance, you write the base address ffOGh into the address register and
thme value Offfb into the count register (that is, you want to transfer 4 kbytes via a DMA channel)
tk len the address register wraps around from ffffh to CQGUh during the course of this transfer.
rm he DMA transfer is not completed by this, of course, as the count registn further holds the
 708 Chaoter 28

2 value OfOOh. The rest of the data is therefore written to the beginning of the DMA page. This
wrap-around of the address register is called a DMA segment overflow. Thus when programming
a DMA transfer, you must always ensure that all data to be transferred can be accommodated
contiguously in the remaining seetion of the DMA page. The DMA chip doesn’t report any
message if a DMA overflow OCCUR .

The 8237A Standby Mode

If the 8237A is in standby mode it checks with every clock cycle whether the E signal is active
and the CPU is trying to access one of its registers. If B is active (that is, on a low level), the
8237A enters the programming state and waits for addresses and, eventually, data from the
CPU to write them into the mrresponding register, or to provide data from the addressed
register to the CPU. Address lines A&A3 determine the register selected. To be able to read
from and write to the l&bit 8237A registers via the g-bit data bus DLGDB7, the 8237A uses an
internal flip-flop for switching between low-order and high-order data bytes. If you attempt to
read or write a I&bit register you must reset this tlip-flop first, and then read or write the least
significant and then the most significant data byte. (Details on programming the 8237A are
.discussed in Section 28.2.3.)
In the standby mode, the 8237A further samples its DREQ inputs upon every clock cycle t0
determine whether a peripheral has issued a DMA request. If the corresponding DMA channel
is not masked internally then the DMA chip outputs a request for the local bus to the CPU via
the HRQ pin to take over control of the local bus. After the CPU has responded with an HLDA
signal and has released the bus, the requesting 8237A enters the active mode to carry out a DMA
28 DMA Chip 8237A - A Detour Hlghway in the PC 709
-

service. Depending “pan the programming. it is able to operate in four different modes, ex-
plained now in brief.

Single Transfer
ln this mode the 8237A carries o”t only a single transfer. The cwnt qister is decremented by
one and the address register, depending upon the programmed state, is also decremented or
incremented by one. If the co”nt register reaches the value ffffh, starting from OOWh, then the
BZ37A internally issues a TC and with a comportding pmgrammed state also an autoinitialization
of the DMA chip.
With this mode you can also move a whole block of sequentially ordered data. Unlike the block
tiansfer mode, though, you have to start every data tramfer individually by a signal DREQ or
a set bit on the request register. As compensation for this restriction, however, the CPU can
again get control of the lacal bus between two transfers.
The single transfer mode is used in the PC for transferring a data sector from the floppy disk
t
dnve mto the main memory. For this purpae, the CPU ,)as to load the ccunt register with the
( value 511 (512 bytes to transfer) and the address and page register with the buffer address in
@, the main memory. The floppy controller activatff the DRXQZ line with every decoded data byte
B from the floppy disk to issue a single transfer cycle. After transferring 512 bytes into main
P memory, a wraparound in the co”nt register occurs, and a TC is generated. The 8237A then
@ terminates the DMA transfer.

lis :j Block Transfer

“B
ed ; This mode causes the 8237A to transfer data contbwously after acknowledging the DREQ re-
& guest and the output of DACK. For this purpose, the co”nt register is decremented by one upon
“Y I each transfer, and the address register (depending upon the programmed state) decremented or
I.mcremented until a TC or an external m ocmrs. A TC is p-t if the count register reach-
the value ffft’h, starting from OWOh. With a correspondingly programmed state an autoinitial-
ization is carried ““t.
ve
he 6 Demand Transfer )
he F
^ Jn demand transfer mode the BZ37A carries o”t data transfer contin”o”sly until a TC or an external
Ed ocmrs, or the peripheral deactivates DREQ. Thus the demand transfer differs fro”, the block
ad in that disabling DREQ also leads to intermption of the data transfer. In block transfer
an j mode this has no consequences. Moreover, in demand transfer mode the data transfer continues
to i
u at the location of the intermption if the peripheral activates DREQ again. Demand transfer
1St % mode is of some importance in the PC, as the bus slots don’t have a connection for m through
re _.;, which a peripheral might indicate the end of the data transfer to the DMA chip, Disabling
: DREQ only leads to an intermption, not to the transfer’s termination. Autoinitialization is there.
$ fore not carried 0°C This is only possible by means of a TC or an external ?X%
to a:.
,el
iia i&ding
_
,A $ Dne characteristic of the 8237A is its capability for cascading. The number of DMA channels
IA 4, Qn thus be extended, simitar to the 8259A PIC and its intermpt channels. unlike the PIC the
i.
q’
 710 Chapter 28

extension with the 8237A works to any depth. Figure 28.6 shows a scheme for this cascading
capability.
-

L CPU

-1
-3-

Cascading is carried out by amntiing one channel’s DREQ and DACK of a DMA chip of a
higher level with HRQ and HLDA, rq&ively, of a Dh4A chip of a lower level. Normally, an
8237A take control of the local bus by means of HFZQ and HLDA when it re&vm a DMA
request via DRRQ. With the cascading scheme, however, a DMA request to a second level DMA
chip (the slaop) leads to a DMA request to the DMA chip of the first level (the master), as the
slave’s HRQ signal is passed to the DMA chip of the fint level via the DREQ input. “ihe master
takes control of the local bus by means of HRQ and HLDA, and activates its output DACK,
which is conneded to the input HLDA of the DMA slave. Thus the DMA slave interprets the
DACK signal from the master as an HLDA from the CPU. Cascading therefore leads the conhOl
signals HRQ and HLDA through master and slave. The figure shows further that the cascading
scheme is extendable up to any Level. “ihe A? uses one slave and one master. The slaVe is
ccmnected to channel 0 of the master, thus the slave channels have a higher priority than the
aastefs chann$s. Channel 0 of the AT’s master is usually denoted as DMA channel 4.
. _
Besides the conn&ions shown, the master channel concerned needs to be programmed in
cascading mode to realize cascading. It is then only used for passing the control signals from
the DMA slave, and dwsn’t provide any address or control signals for the bus.
The three transfer modes (single, block and demand) can carry out four transfer types, each of
which differs in the source and target of the transfer. The following discusses these four transfer
types.
 DMA Chip 8237A - A Detour Highway in the PC 711

Read Transfer
In read transfer, data is transferred from main memory to an I/O - device, thus from
_ memory
to the I/O address space. For this purpose, the 8237A uses the MEMR and IOW signals. By
activating MEMR, data is read from memory -onto the data bus. The data on the data bus is
transferred to the I/O device by activating IOW. Figure 28.7 shows a signal diawam for a read

. ,

: During the course of the shown read transfer, the 8237A initially outputs the high-order address
)i byte of the memory address via the data bus DBGDB7, and activates AD!STB to latch ad&s
%: bits A&A15 onto the DMA address latch. At the same time, the low-order address byte of the
memory address is output via address lines AO-A7. Activating MEMR to a low lwel causes
g. the memory subsystem &read data from memory, and to put it onto the system data bus. The
’ memory buffer (see Figure 4.2) latches the read data and keeps it stable on the system data bus.
i By activating IOW the peripheral is advised to fetch the data on the system data bus into its
_ I/O buffer (see Figure 4.8). The peripheral takes the data directly off the system data bus. No
h temporary storage in the temporary register of the 8237A is carried cut.

2 As you can see from the figure, the 8237A doesn’t generate any I/O address for the peripheral.
:Tile peripheral is only accessed via the assigned lines DREQx and DACKX, while the other
” peripherals in the I/O address space are disabled, for example, by the active AEN signal from
,-? the DMA chip. Nowbnly the intended device responds to the 8237A mntrol signal. Figure 28.7
kw further that one DMA cycle lasts for four DMA clock cycles. If a slow memory or I/O
a device is addressed, one or more wait cycles may be inserted between 52 and 53, or between
; $3 and 54. The DMA cycle is then extended accordingly.
.-1 .
*i%he high-order address byte A&A15 need not be output during each DMA cycle, but only if
i the high-order address byte really changes This wars only every 256 bytes. In the second cycle
 712 Chapter 28

of the figure, phase S2 is therefore missing, so only three clock cycles are required for a single
DMA cycle. This means a time saving of 25% in the end.

Write Transfer
The write transfer is, so to spe.,k, the opposite of the read transfer. Data is transferred from an
I/O device into main memory, that is, from the I/O to memory address space. The 8237A uses
the m and MEMW signals for this purpose. By activating IOR, data is read from the I/O
device onto the data bus. The data is then transferred to memory by an active -_ MEMW. The
signal- diagram in Figure
- 28.7 is also valid for a write transfer if you replace MEMR by IOR
and IOW by MEMW, The DMA cycle is four clock cycles long if the high-order address byte
needs to be supplied to the DMA address latch, o(hetvise it is three clock cycles. If the DMA
chip has to insert wait cycles because of slow memories or I/O devices, the Dh4A cycle is
extended accordingly.

Verify Transfer
:
Verify transfer is merely a pseudo-transfer as the B237A operates internally in the same way as
in a read or mite transfer, therefore it generate addresses and responds to - m and - other-
signals but doesn’t provide any I/O and memory control signals such as IOR, IOW, MEMR,
MEMW, etc. externally. Thus the verify transfer serves only for internal 8237A checking to
determine whether the addressing and control logic are operating mrrwtly. With a real verifi-
cation of data this has nothing to do.

1 Memory-Memory Transfer
With memory-memory transfer the 8237A may move a complete data block from one address
area in the main memory to another. However, this type of transfer is only available for than-
nels 0 and 1; channels 2 and 3 only carry out the three transfer types indicated above. Channel
0 determines the source and channel 1 the de&nation of the data transfer. For memory-memory
transfer, the temporary register is important because it accommodates the data byte read from
the source area in the main memory before it is written to another location in main memorY via
channel I. The memory-memory transfer is issued by a software request for channel 0, because
an external Dh4A request with DREQO is not possible here. As usual, the B237A requests contlOl
of the local bus by means of HRQ and HLDA. The memory-memory transfer is generally
terminated by a ‘I’C of channel 0 or 1 if the count register reaches the value ffffh, starting with
WWh. The 8237A responds in memory-memory transfer to an external m signal. Through
.* this, external diagnostic hardware, for example, may terminate the DMA transfer if the source
or destination address b~omes of a certain value. Figure 28.8 shows a signal diagram for a
memory-memny transfer.
‘1 During the fast half cycle the DMA chip reads the data byte into the temporary register by fat
. ’ providing the high-order address byte AS-AI5 on DBO-DB7. The address byte is then loaded
into the DMA address latch by activating ADSTB. At the same time, the 8237A outputs the lw’-
order address byte via AO-A7, and activates MEMR to read out the data byte onto the system
data bus. The 8237A fetches the data, via DKDB7, into its temporary register. The next half
cycIe then writes the data byte held by the temporary register to a nerV address in main rnem~~~~
MA Chtp 8237A - A Detour Highway in the PC 713

> carry out this process, the 8237A first writes the high-order add,ess byte into the DMA
Idress latch and pub the data byte via DB&DB7 onto the system bus afterwards. The follow-
g activation of MEMW instructs the memory to write the data byte to the corresponding
Idress. Thus the memory-memory transfer is complete. As can be seen from Figure 28.8, such
transfer requires eight DMA cldck cycles.
Tote that CLK indicates the DMA dock and not the CFTJ clock. Even in i386 systems with 33
4Hz, the DMA chip usually runs at 4.77 MHz. Thus a memory-memory transfer lasts for about
680 ns. If we assume a 70 ns main memory with about 120 w cycle time and three CFTJ clock
ydes for the execution of one i386 MOVS in&u&n, then the transfer of one word via the CPU
lsts only 330 ns. This is five times faster. If we further take into account that the i386 can
~ansfer 32 bits all at once, but the 8237A only eight, then the i386 transfers data from memory
) memory 20 times faster than the 8237A.
is a feature, channel 0 can be programmed to keep the &me address duling the muse of the
rhole memory-memory transfer. The 8237A then carries out a memory block initialization. ne
we of this block is defined by the count value in the count register of channel 1.

ompressed Mode
DT fast memories and I/O devices the 8237A may be programmed so that it carries out a
>mprewzd mode. The transfer time is then compr&sed to two DMA clock cycles. Figure 28.9
mws a signal diagram for the compressed mode.
s ydu can see, cycle 53 is missing. It extends the read pulse with slower memorig and I/O
e&s so that the addressed unit has enough time to provide the data. With modem devices
ds is no longer required, and 53 can be dropped. Note that the 8237A runs only at 4.77 MHz
I the PC. Every device as slow as the 8237A can easily follow, but after 256 bytes at most .$I
lditional cycle Sl is required, because a new high-order address byte for the DMA address
Itch must then be supplied via DBODB7. .
714 Chapter 28

The compressed mode is only implemented for read and write transfers. For a memory-memory
transfer the compressed mode is not possible, although today’s RAM chips are among the
fastest compo”e”ts i” a PC.

Autoinitialization

The individual 8237A channels may be programmed so that they initialize themselves to the
initial values after a TC or m automatically. For this purpae, the current address register
and the current count register are loaded with the values horn the base address register and the
base count register. The base address register and base count register are not accessible, but are
loaded during the cause of a write to the current address register and the current ccant register
by the CPU with the same values. The base address register and base ccmnt register are not
altered by the following Dh4A cycles, and hold the initial values wen after a” ??@ from which
the current address register and the current count register are restored during autoinitialization.
Afterwards, the 8237A channel concerned is again ready for a DMA transfer.

Autoinitializati”” is used if data quantities of the same size are always to be transfer& to a
fixed buffer in the main memory, “r horn the main memory. This can be the case, for example,
when reading a s&or fmm a floppy disk into the main memory. Here it would be sufficient to
program the DMA chip once. For all succeeding sector transfers, the chip initializes itself again
and again.

.2&2.3 Programming the 8237A

For programming the 8237A five control registers are available. Additionally, you can determine
the 8237A’s current state by a status register. From the temporary register you may read the last
transferred data byte of a memory-memory transfer. Table 28.2 lists the I/O addresses of the
registers concerned. Note that the K/XT only has the DMA 1 chip,
DMA Chip 8237A - A Detour Highway in the PC 715

DYA I” DMA 2”

Wh dOh
@3h dOh
Wh dZh
Oah d4h
Obh d6h
Wh dab
Mh deh

The read-only status register provides some infornxation on the current state of the individual
channels in the 8237A. Figure 28.10 shows the shllcture of this register.
:

The four high-order bits REQ34EQO indicate whether a quest is pending via a DREQX signal
for the channel concerned. Bib TC3-TCO show whether the 8?7A has reached a terminal count
of the corresponding channels according to a transition from OOOOh to ffffh of each count reg-
ister. If you read the status r&ister, the four bits TC3-TCO are automatically cleared.
Before programming an 8237A channel you should disable the whole chip, or at least the
channel to be programmed. According to Murphy’s law, no DMA request for this channel ’
0ccum all year - until you try to pmgram it! If a Dh4A request occurs, for example after
programming the low-order address register byte, then the 8237A immediately responds to the ..
t’equest and carries out the DMA transfer with the new low-order and the old high+rder
address byte. You can surely imagine what this means. Once the catastrophe is complete, the
8237A enters program mode again and the CPU can write the high-order address byte - if it is
Wally able to do this an; more. You may disable the complete DMA controller with the COND
bit in the mntrol register. An individual channel can be masked by means of the channel mask
or the mask register. Figure 28.11 shows the command register.
With the DARP bit you can determine the active level of the DACK signals. If DAKF’ is cleared,
then the 8237A pmvidff a low-level signal at the DACKx pin if it is servicing 2 DMA request
 716 Chapter 28

via DRQx; otherwise, the pin outputs a high-level signal. With a set DAKP bit the 8237A
supplies a high-level signal at the DACKx if it is servicing a DMA request via OR&, othemise
a low-level signal is supplied. The standard setup after a reset is a cleared DAKP bit, which is
also used by the PC. Thus, DACK signals are always active-low in the PC. The DRQP bit has
a similar effect. With this bit you can define the active level that the 8237A assigns to the DMA
request signals. A cleared DRQP bit means that the 8237A interprets a high level at its DRQx
input as a DMA request for the channel x mncerned. With a set DRQP bit, on the other hand,
the 8237A issues a DMA transfer if a high-lwel signal is supplied. Thus DRQP and DAKP
behave in opposite ways. The standard setup aft&a reset is a cleared DRQP bit, which is also
used in the PC. DRQ signals are therefore always active-high in the P C.
- -
The EXTW bit conhols the length of the write pulse IOW or MEMW during a DMA transfer.
With a set EXTW bit the write pulse will already have started one DMA clock cycle earlier
during DMA phase s3; thus it is longer. You can see this in Figure 28.7: the broken line indicates
an extended write, and the salid line a late write. In compressed mode (that is, with a set COMP
bit), the value of EXTW is immaterial as the 53 cycle is missing. With the PRIO bit you may set
up the priority strategy that the 8237A uses to service incoming DMA requests. After a reset,
PRIO is set So that the 8237A uses fixed priority with the order 0, 1,2,3. A set COMP bit advise
.?he 8237A to Carry out compressed clocking where phase 53 is missing. Memory-memory traw
‘fers do not allow compressed mode - a relic of memory access times of 200 ns and more.
Using the COND bit you can disable the DMA controller completely. It doesn’t respond to any
DMA requests but must always be kept in programming mode. Thus the 8237A can only accept
commands, and enables the CPU to access its internal registers. *
‘r 28 blA Chip 8237A-A Detour Htqhwav I” the PC 717
-

w AHDE bit is important for memory-memory transfers. With a set AHDE bit the 8237A
!ep the value in the address register of channel 0 unchanged; only the address register of
cannel 1 is continuously increased or decreased. A whole memory block can thus be initialized
ith the value to which the channel 0 address register points. If AHDE is cleared, a real memory-
emory transfer of a complete data block is executed. The value of AHDE is only effective with
set MMT bit.
‘ith a set MMT bit the 8237A enters memory-memory transfer mode. Note that only a few
otherboards support this transfer mode. For the memory-memory transfer only channels
and 1 are available. Channel 0 defines the source and channel 1 the target of the transfer. All
her modes are defined via the mode register (Figure 28.12).

37A
vise
h is
has
MA
0
md.
KP sides a hardware DMA request via the DRQx signals, you also have the option to start a DMA
llso ansfer by a software command. The 8237A behaves in the same way as if activated by a DRQx.
MA requests by softwhre are imperative for memory-memory transfers, as the memory sut-
&em is unable to provide a DRQx signal for initiating the data transfer. The request of a DMA
fer.
ansfer is carried out with the request register (Figure 28.12). Bits SELI, SELO determine the
lier
tannel for which the request is to be issued The STCL bit defines whether the accompanying
ttes
guest bit is to be set or cleared. If no further DMA requests are currently active, or of a high
MP
riority, then setting the request bit immediately leads to a DMA transfer. The request is other-
set
ise queued according to the programmed priority strategy. You may remove a DMA transfer
set,
zd yet initiated from the queue by clearing the corresponding request bit.
se5
“S-

he channel mask register (Figure 28.13) masks a single channel. With the related mask register,
R the other hand, you can mask 0’ release several.channels all at once. Bits SELI, SELO define
the channel to be masked or released. YKL determines whether this channel is to be masked
or released.

With the mode register (Figure 28.14) you may set the operation mode and the transfer type of
an 8237A channel. Bits MODI, MOW define the operation mode of the channel concerned;
demand, single and block transfer as well as cascading are available, though in cascading mode
the following bits are of no meaning. With IDEC you can define whether the address register
is to be increased or decreased after each data transfer. AUTO activates or disables the
autoinitfalizatfon of the 8237A for one channel. If you haven’t s&&d cascading mode by
means of MODI. MODO, then you must now define the transfer mode with TRAI, TRAO. SELI,
SELO determine the 8237A channel for which the definitions by means of bits 7-2 hold.
 DMA ChnD 8237A - A Detour Hiqhway I” the PC 719

As already mentioned, you have the option of masking or releasing several channels all at once
using the mask register (Figure 28.15). Bits STC3-STCO indicate whether the corresponding
mask bit is set and whether the DMA request for the channels concerned is masked, or whether
the mask bit is cleared and the channel released.

The 8237A implements three additional commands, but they are programmed as an output to
a register. This tneans that you have to exe-ate an OUT command with any data byte to the
corresponding address to issue the command. By decoding the address bits AO-A3, the 8237A
rrcognizes that a command and not a data write to a register has occurred. The data byte passed
by the OUT instruction is ignored. Table 28.3 lists the three additional commands. . .

DMA 1” DMA 2”
(kh d8h
Wh dab
Oeh dch

~~ You need the command resel flip-flop to reset the intern.4 flip-flop in the 8237A if you want to
I write to a l&bit register. Afterwards, you pass the low-order and then the high-order data byte.
Without the command the flipflop may be in an unpredictable state, and low- and high-tier
data bytes are possibly interchanged.
‘*
s Exan,ple: n..er &-rw of nr 1.
mn am. *1 i OYrDur any rm,ue ro P)rt *m
, +c-n.a =re..r tlip4or.r .xscuted
; The master clw command has the same effect as a hardware reset of the 8237A. Command,
;~ Status, request and temporary registers are cleared, and the flipflop is reset.

:!,,
720 Chant., ,I(

DMA P Rqlister name :

cob address register channel o/4

clh count register channel 04
c2h address register channel l/5
c3h count register channel Ii5
C4h address register channel 2/C
c5h count register channel .?I6
cm address register channel 3”
Oh CO”“, regmr channel 3 ”
DMA Chip 8237A -A Detour Highway in the PC 721

Port Page RgiRer Port Page regimr

87h channel 0 8fh channel 4 (refresh,
83h ‘hanIle, 1” 8bh channel 5
8th channel 2 8% channel 6
82h channel 3 *all channel 7

I’ KM only: Yln”ll.“eoWly Ck”nd 0

Ial< 285: Po*r rrgirter I,0 n&f-

Note that in the PC/XT channels 0 and 1 are assigned the same physical page register. There-
fore, you access the same physical register via the two different I/O addresses 87h and 83h. On
the AT the page register for channel 4 - which is used for cascading - is the page address for
memory refresh.

28.2.4 Example: Initialize DMA 1, Channel 2 for Floppy Data Transfer

The following program example initializes channel 2 of Dh4A I for a write transfer to transfer
one floppy disk sector with 512 bytes from the controller into main memory. The segment and
offset of the read buffer are passed in the repisters FSBX. A check whether a DMA segment
overflow might occur is not carried out. The DMA transfer is initiated by a DREQZ from the
floppy disk controller. The pmgram code can be part of a routine by which the CPU drives
the floppy controller to transfer one sector with a read command. If several sectcrs are to be
transferred in succession, then the value in the count registers mwt be increased accordingly.
‘ ..~...~......~...~.~....~.~.....~.......~..~.~....~~...~..~....~..~~.......~.......~.....
,** Lss, buft*r S-t . ..* *a*m -=.a B.S. .*
I’. 8x: buuftsr otfS*r ---- *.
,** ..
,** hS. ad&.s.z as.. S.,. . . . . ..S. - ..
,** * OOOD--mm *.
I** ..
i** DDDD hhhh hbM 1111 1111 *.
i** .*
i** WpDi atry Lox tha - Dig. rWf.t*r ..
a** hhhb hMh: hf.zhh-ord*r wra tar a. Mad*.*. rql1st.r ..
i** 1111 1111: la-or&r Lyre for w nu addran. rSgi,rer *.
, . . ..~.*.*.*.........*.~*.*.................*....*...........*.*...........~.*....**.*..~.
~l_*ie.bl.: / dieable nr 1
cm OBh. 1.h / .aepuL 0001 OlOOb to caand rsgi.ter to .aisam* aId iniLialize u,e 81311
, 1ixFi: actin low. DRQi actira MS?,. Iar.rrira, Driority: flxe.3,
‘* , claklnsi lIo~1, cont.oll.ri df.able.3, addre.. hold: dicmblaa.
. _ ; malow--w: dimbla.5~
-8 , q e “P mm mod. for chalm*l 1
m obh. 56h I o”tDUL 0101 011Ob to lode rwi.rer
/ h3a.r single fren.f.r, a.3.3rasm incremm.tatic.n. ma auroinitiali~.tion.
/ rr.ncdar mcdei write. ch-1: 1)
mu_aadr.m: / .Dlir d&m.. in E9,bx inro DDW hhhh hmh 1111 111).
 Chapter 28

Alternatively, you may also mask only the channel concerned of the first DMA controller 1. All
other channels remain enabled during the initialization of channel 2. Some 386 memory drivers
need one or more DMA channels of the first DMA controller to accw extended memos
Masking the controller, espexially for a longer time period, may lead to the crash of these
drivers.

‘.
’ 28.2.5 DMn’ Cycles in Protected and Virtual 8086 Mode

If you want to initialize and execute a DMA transfer in protected or even virtual 8086 m&with
active paging, you are confronted with many problems; in most cases, the task crashes ime
diately after the DMA transfer. The addresses that the 8237A. the DMA address latch, and the
DMA page register provide are physical addresses. If you try to load one of these registers with
DMA Chip 8237A - A Detour Highway in the PC 723

a segment descriptor, the address points somewhere, but certainly not to the intended location.
In virtual 13086 mode the situation doesn’t get any better. Even if you succeed in eliciting the
linear address from the segment dexriptor, this doesn’t help if paging is active. The linear
address is completely replaced by the paging mechanism and the page concerned till possibly
have been swapped by the operating system a long time before. The DMA contmlIer realizes
nothing, of course, as it is only running in a real mode and doesn’t understand the CPU’s
segmentation and paging mechanisms.
In the environment of a protected mode operating system or virtual 8086 monitor, application ,
pmgrams have no chance of initiating a DMA transfer on their own. This is the job of the
operating system only. All attempts to write the Dh4A registers by OUT inawtions are inter-
cepted by an exception if the IOPL tlag isn’t privileged enough, or the I/O part is protected by
meana of the I/O permission bit map. A DMA transkr is not a trivial jab, espwially when
paging is enabled, even for the operating system or the virtual 8086 monitor, as the DMA
controller overwrites the physical memory contents mercilessly without any care for the pre
t&ion mechanisms of the protected mode. Therefore an ipcorrectly intttalimd DMA chip may
overwrite proteded memory locations even in protected mode. This inevitably gives rise to a
crash of the task mncemed immediately, or of tk complete computer system.