Interconnect Parasitic

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Output load classified as three components.

-Internal parasitic capacitances of transistors

-Interconnect (line) capacitances

-Input capacitances of fanout gates.

Interconnection in sub micron circuit causes problems.

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BITS Pilani, Pilani Campus
If the load from each interconnection can be approximated by
a lumped capacitance, total load seen by primary is sum of all
capacitive components.

Each wire in a bus network connects a transmitter (or

transmitters) to a set of receivers and is implemented as a chain
of wire segments of various lengths and geometries.

Line itself three dimensional in metal/ and or polysilicon, has a

negligible resistance. Parameters are distributed ( length / width
ratios)

Interconnect line in very close proximity to a number of other

lines either on same level (or) different level.
Capacitive/inductive coupling and signal interference to be
considered.
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In general, if the time of flight across the interconnection line ( as determined
by the speed off light) is much smaller than the signal rise/fall times- wire can
be modeled as a capacitive load or as a lumped distributed RC network.

rise (fall ) < 2.5 x (l/v) ; transmission line model

2.5 x (l/v) < rise (fall ) < 2.5 x (l/v) ; either transmission line
or lumped model.

rise (fall ) > 5 x (l/v) ; lumped model.

l- interconnect length, v- propagation speed

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Longest wire on a VLSI chip about 2cm.

The time of flight of a signal across this wire assuming r = 4 is

133ps.

Shorter than typical on chip signal rise/fall times

Lumped RC model adequate.

Time of flight on a 10cm Multichip module in an alumina

substrate is 1ns same order as rise/fall time.

modeled as RLGC parasitic.

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As the fabrication technologies move to finer sub-
micron design rules, the intrinsic gate delays tend to
decrease

and as overall chip size and worst case line length on

a chip tend to increase- Interconnect delay dominates.

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 Capacitive Cross Talk

X
CXY
VX Y
CY

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 VDD

CLK C XY
Y

CY
In 1 X
In 2 PDN
In 3 2.5 V

0V
CLK

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 Cross Talk and Performance
- When neighboring lines switch
in opposite direction of victim
line, delay increases
Cc
DELAY DEPENDENT UPON
ACTIVITY IN NEIGHBORING
WIRES

Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0  Vdd, Vdd  0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)

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Chip designers need efficient means for

-estimating interconnect parasitics

-Simulating transient effects.

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Interconnect Capacitance Estimation.

Each interconnection line is a three dimensional structure in

metal/or polysilicon, with significant variation in shape, thickness
and vertical distance from ground plane ( substrate) ; surrounded
by number of other lines.
wire has
length l
width w and
thickness t

 di
cint  WL
h
Runs parallel to chip
Surface separated by
Dielectric layer by ‘h’
To minimize the resistance of the wires while scaling technology, it is
desirable to keep cross section of the wire ( Wxt) as large as possible.

Small values of W lead to denser wiring and less area overhead. Over
the years it has witnessed a steady reduction in W/t ratio.

Under these circumstances, the parallel plate model assumed earlier

becomes inaccurate. The capacitance between the sidewalls of the
wires and the substrate, called fringing capacitance, can no longer be
ignored

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Fringing field significantly increases the total capacitance.
Fringing field is a function of (t/h), (w/h), (w/l).
 Fringing Capacitance

(a)

H W - H/2

(b)

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fringing parallel

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C =  [ (w- t/2)/h +2/ (ln(1+2h/t +{2h/t(2h/t+2)}1/2 ) ]

for w  t/2

C =  [w/h + ( 1- 0.0543. t/2h)/ (ln (1+2h/t +

(2h/t)1/2 (2h/t +2)
+ 1.47]

for w < t/2

Developed by Yuan and Trick.

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 Wire Resistance

R= L
HW

L Sheet Resistance
H Ro

R1 R2
W

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Interconnect resistance

the resistance of a line depends on the type of material,

dimensions of the line

Rwire = Rsheet. (l/w)

Rsheet - sheet resistance of line, in (/square)

Rsheet - polysilicon 20 – 40 /square

Total resistance measured based on geometry of line.

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 2
8

2

R = 1 square x Rs
R = 4 squares x Rs
= 10 4 ohm
= 4 x10 4 ohm
 Calculation of interconnect delay

RC Delay Model.

Simplest model. – lumped resistance and lumped capacitance.

Vout(t) = VDD ( 1 – exp ( -t/RC) )

The rising output reaches the 50% point at t =  PLH

V 50% = VDD ( 1 – exp ( -  PLH /RC) ) =>  PLH = 0.69RC
 Other models.

T model

Ladder network

Accuracy of model depends on increasing the value of N.

A uniform polysilicon line with a length 1000m
And a width of 4 m.
Assume a sheet resistance of 30/square

R lumped = Rsheet x (no of squares)

30/square x (1000/4)
= 7.5k 

To calculate the total capacitance.

C parallel-plate = (unit area capacitance) x area

66(poly over field oxide)pF/ m2 (1000x4) m2

= 264fF
C fringe = (unit length capacitance)x(perimeter)
= 46pF/ m x(1000+1000+4+4) m = 92fF
Clumped = 356fF
Lumped RC = 1.9ns, 10 segment distributed RC = 1.1nS
Line consisting of two segments each 500 m long
Width different.
R lumped –1 = 30 (500/2) = 7.5k

R lumped –2 = 30 (500/6) = 2.5k

R lumped -total = 2.5+7.5 = 10k

C pp-1= 66 (500x2) = 66fF

C pp-1= 66 (500x6) = 198fF

C fringe1= C fringe2=46fF

C lumped –total = 356fF

Elmore delay model.

RC Tree network.
There are no resistor loops in the circuit.

All capacitors in a RC tree are connected between a node

and ground.

There is one input node in the circuit.

There is a unique resistive path from the input node to any

other node in the circuit.

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Pi denote the unique path from input node to node i
i = 1,2,3,…..N

Pij = Pi  Pj denote the portion of the path between the input

and the node i, which is common to the path between input
node and node j.

input signal is a step input at time t = 0,

The Elmore delay at node I of this RC tree given by

N
D7 =  Cj  Rk
j=1 for all k  Pij

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D7 = R1C1 + R1C2 +R1C3 + R1C4 +R1C5+
(R1+R6)C6 + (R1+R6+R7)C7 + (R1+R6+R7)C8

for node 5.

D5 = R1C1 +( R1+R2)C2 +( R1+R2) C3 + (R1+R2+R4)C4

+ (R1+R2+R4+R5)C5 + R1C6+R1C7+R1C8

RC/2.
RC ladder consisting of one branch.
 Impact of Wire Length to Delay

Using distributed RC model

Assume that
Unit length resistance is R
Unit length capacitance is C
Then the delay constant of a wire of k-unit length will be:
RC· N· (N+1)/2
 i.e., delay is quadratically proportional to the wire length
 For example, increasing a wire length by 10 times
will approximately increase the delay by 100 times
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