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Binary Multiplier - VHDL

The document describes the operation of a 4-bit binary multiplier. It involves a multiplicand register, multiplier register, 4-bit full adder, and 8-bit product register acting as an accumulator. The multiplier bits are checked sequentially. If a bit is 1, the multiplicand is added to the accumulator and both are shifted right. If the bit is 0, only a right shift occurs. A control circuit outputs add and shift signals based on the multiplier bits and a start signal to perform the multiplication over 4 cycles.

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95 views

Binary Multiplier - VHDL

The document describes the operation of a 4-bit binary multiplier. It involves a multiplicand register, multiplier register, 4-bit full adder, and 8-bit product register acting as an accumulator. The multiplier bits are checked sequentially. If a bit is 1, the multiplicand is added to the accumulator and both are shifted right. If the bit is 0, only a right shift occurs. A control circuit outputs add and shift signals based on the multiplier bits and a start signal to perform the multiplication over 4 cycles.

Uploaded by

ziko karim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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20/11/2017 Binary Multiplier | VHDL

ALL SYLLABUS

Home About Search Unit 1 Unit 2 Unit 3 Unit 4 Unit 5 Unit 6 Unit 7 Unit 8

Binary Multiplier
STATE
GRAPHS
FOR
CONTROL
NETWORKS

Serial adder
with
Accumulator

VHDL
CODE for
the 16 bit
serial adder

Binary
Multiplier

VHDL code
for 4 X 4
Binary
Multiplier

Multiplier
Control with
Counter

Operation of Multiplication of Two 4 bit numbers requires the following architecture


Multiplier • 4-bit multiplicand register
using a
Counter • 4-bit multiplier register
• 4-bit full adder
4-bit • 8-bit product register which serves as an accumulator to accumulate the sum of partial
Multiplier products.
Partial
Products Note: In the conventional adder Shifting multiplicand left every time would require an 8-bit
State Graph Adder. Instead we shift the contents of the product register right each time
for 2’s The operation of the 4-bit binary multiplier shown in figure is elaborated in the below steps.
Complement • 4-bits from accumulator and 4-bits from multiplicand register are inputs to adder.
Multiplier • 4 sum bits and carry are connected back to accumulator.
• When an Ad signal occurs, adder outputs are transferred to ACC at next clk.
Block
diagram for • Extra bit carries temporarily any carry that is generated.
Faster • Sh signal causes all 9 bits to be shifted right at next clk.
Multiplier • Multiplier is stored in lower 4 bits of ACC.
• Control circuit outputs proper sequence of add and shift signals after the start signal St=1.
VHDL Code
--Behavioral
Model for 2’s
Complement
Multiplier

https://www.allsyllabus.com/aj/note/ECE/Digital_System_Design_Using_VHDL/Unit4/Binary%20Multiplier.php#.WhQsqnmDO01 1/4
20/11/2017 Binary Multiplier | VHDL

Test Bench
for Signed
Multiplier

Design of the
control
circuit in a
Multiplier
using a
counter
(74163)

Binary
Divider

Block
diagram for
Signed
Divider

VHDL
Model of 32-
bit Signed
Divider

Multiplication Steps

Algorithm:
1. If current multiplier bit M (LSB of acc) is 1, multiplicand is added to accumulator and
shifted right.
2. If M=0, addition is skipped and contents shifted right.
The below figure briefly illustrates the contents of the binary multiplier for the example
illustrated above.

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20/11/2017 Binary Multiplier | VHDL

Question: What should the control circuit of the multiplier do??

• Output proper sequence of Ad and Sh signals.


• Start when S=1.
• Load; Ld=1.
• Check if M=1. If yes then make Ad=1 (to add). Then make Sh=1.
• If M =0, then don’t change Ad to 1. Just make Sh=1.

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20/11/2017 Binary Multiplier | VHDL

• A shift is always generated after Add operation.


• A done signal generated after 4 shifts (indicating multiplication is complete).

State Graph for Binary Multiplier Control

28

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