D.Y.

PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO: 01

TITLE OF EXPERIMENT: Implementation of Traffic light controller using VHDL.

A. Diagram:

B. Problem Statement :

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO.01

1.1 AIM:

To write VHDL code for Traffic Light Controller and verify the result using FPGA/CPLD
kit.

1.2 APPARATUS:

1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

1.3 PROCEDURE:

1. Write a VHDL code for Traffic Light Controller by any one method.

2. Verify the functional simulation after synthesizing the code.

3. Implement the code and verify the timing simulation.

4. Download the program on FPGA/CPLD and verify the operation.

5. Generate the RTL schematic for each modeling style.

1.4 RESULTS:

1. Operation of Traffic Light Controller is verified on FPGA/CPLD kit.

2. The worst case timing delay observed during timing simulation for Traffic Light Controller
is___________.

3. The percentage of FPGA/CPLD utilized for Traffic Light Controller is _____________

1.5 CONCLUSIONS:

1. What are the 3 different ways to implement any code using state machine?

2. Compare Moore and Mealy machines?

3. What are the different state encoding techniques? Compare them in brief.

4. Can we represent asynchronous circuits with state diagram?

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO: 01

TITLE OF EXPERIMENT: Implementation of Lift Controller using VHDL.

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO.01

1.1AIM:

To write VHDL code for Lift Controller and verify the result using FPGA/CPLD kit.

1.2 APPARATUS:

1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

1.3 PROCEDURE:

1. Write a VHDL code for Lift Controller by any one method.

2. Verify the functional simulation after synthesizing the code.

3. Implement the code and verify the timing simulation.

4. Download the program on FPGA/CPLD and verify the operation.

5. Generate the RTL schematic for each modeling style.

1.4 RESULTS:

1. Operation of Lift Controller is verified on FPGA/CPLD kit.

2. The worst case timing delay observed during timing simulation for Lift Controller
is___________.

3. The percentage of FPGA/CPLD utilized for Lift Controller is _____________

1.5 CONCLUSIONS:

1. Explain the test benches in short?

2. Explain the difference between the data flow modeling and sequential modeling?

3. Define the term ‘Entity’?

4. Define the term ‘Architecture’?

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO: 02

TITLE OF EXPERIMENT: To read/write into RAM using VHDL.

A. DIAGRAM:

CLK

rd

wr

en RAM data_out

rd_addr

wr_addr

data_in

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO.02

2.1 AIM: To write VHDL code for RAM (read/write) and verify the result using FPGA/CPLD
kit.

2.2 APPARATUS:

1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

2.3 PROCEDURE:

1. Write a VHDL code for RAM by any one method.

2. Verify the functional simulation after synthesizing the code.

3. Implement the code and verify the timing simulation.

4. Download the program on FPGA/CPLD and verify the operation.

5. Generate the RTL schematic for each modeling style.

2.4 RESULTS:

1. Operation of RAM is verified on FPGA/CPLD kit.

2. The worst case timing delay observed during timing simulation for RAM is___________.

3. The percentage of FPGA/CPLD utilized for RAM is _____________.

2.5 CONCLUSIONS:

1. How many address lines are required for RAM?

2. Write the applications of RAM?

3. What is the difference between RAM and FIFO?

4. Is it synchronous or asynchronous?

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO: 03

TITLE OF EXPERIMENT: To generate ramp or square waveform using DAC.

A. DIAGRAM:

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
EXPERIMENT NO.03

3.1 AIM: To write VHDL code to generate ramp or square waveform and verify the result using
FPGA/CPLD kit.

3.2 APPARATUS:

1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

3.3 PROCEDURE:

1. Write a VHDL code to generate ramp or square waveform by any one method.

2. Verify the functional simulation after synthesizing the code.

3. Implement the code and verify the timing simulation.

4. Download the program on FPGA/CPLD and verify the operation.

5. Generate the RTL schematic for each modeling style.

3.4 RESULTS:

1. Operation of DAC_counter is verified on FPGA/CPLD kit.

2. The worst case timing delay observed during timing simulation for generation of ramp
waveform using DAC is___________.

3. The percentage of FPGA/CPLD utilized for generation of ramp waveform using DAC is
_____________.

3.5 CONCLUSIONS:

1. Which IC is used as DAC? What is its resolution?

2. How many digital inputs are given to DAC IC?

3. What is the value of maximum analog output?

4. Is it synchronous or asynchronous?

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO: 04

TITLE OF EXPERIMENT: Design of 7 segment display counter from 0 to 9.

A. DIAGRAM:

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO.04

4.1 AIM: To write VHDL code for design of 7 segment display counter from 0 to 9 and verify the
result using FPGA/CPLD kit.

4.2 APPARATUS:

1. Computer with Xilinx software.

2. FPGA/CPLD kit with JTAG cable.

4.3 PROCEDURE:

1. Write a VHDL code design of 7 segment display counter from 0 to 9 by any one method.

2. Verify the functional simulation after synthesizing the code.

3. Implement the code and verify the timing simulation.

4. Download the program on FPGA/CPLD and verify the operation.

5. Generate the RTL schematic for each modeling style.

4.4 RESULTS:

1. Design of 7 segment display counter from 0 to 9 is verified on FPGA/CPLD kit.

2. The worst case timing delay observed during timing simulation for 7 segment display counter
is___________.

3. The percentage of FPGA/CPLD utilized for 7 segment display counter is _____________

4.5 CONCLUSIONS:

1. What is the test bench?

2. What is function and procedure?

3. What are the selection criteria of FPGA?

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO.05

TITLE OF EXPERIMENT: Implementation of CMOS inverter using Microwind.

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO.05

5.1 AIM:

To implement and verify the functionality of CMOS inverter using Microwind.

5.2 APPARATUS:

Computer with Microwind Software.

5.3 PROCEDURE:

Part A:

1. Create your own NMOS & PMOS transistors.

2. Use the design rules for 90 nm process.

3. Plot the characteristics of NMOS transistor

Part B:

1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.

2. Instantiate NMOS or PMOS transistors from the symbol library and place them in the
editor window.

3. Connect the drains and sources of the transistors.

4. Connect VDD and GND from the symbol library to the schematic.

5. Connect inputs and output.

6. Simulate the circuits to check the logic functionality

Part C:

For Inverter following points to be considered,

1. Design rise & fall time, considering fan out in the form of a capacitive load.

2. Measure current drawn & hence power dissipation.

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
3. Calculate propagation delay.

5.4 RESULTS:

5.5 CONCLUSIONS:

1. Explain VTC and CTC of CMOS inverter.

2. What is CMOS switching characteristics of Inverter.

3. What do you mean by rise-time model of CMOS inverter.

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO.06

TITLE OF EXPERIMENT: Implementation of CMOS NAND and NOR gate using Microwind.

Diagram: CMOS NAND Gate

Diagram: CMOS NOR Gate

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO.06

6.1 AIM: To implement and verify the functionality of CMOS NAND and NOR gate using
Microwind.

6.2 APPARATUS:

Computer with Microwind Software.

6.3 PROCEDURE:

Part A:

1. Create your own NMOS & PMOS transistors.

2. Use the design rules for 90 nm process.

3. Plot the characteristics of NMOS transistor

Part B:

1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.

2. Instantiate NMOS or PMOS transistors from the symbol library and place them in the
editor window.

3. Connect the drains and sources of the transistors.

4. Connect VDD and GND from the symbol library to the schematic.

5. Connect inputs and output.

6. Simulate the circuits to check the logic functionality.

6.4 RESULTS:

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

6.5 CONCLUSIONS:

1. What do u mean by power dissipation?

2. What are the design considerations in VLSI?

3. What do you mean by technology scaling?

EXPERIMENT NO.07

TITLE OF EXPERIMENT: To implement 2:1 mux using conventional method and also using
transmission gate and compare both.

Diagram: Transmission gate symbols

Diagram: 2:1 MUX using transmission gate

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks

EXPERIMENT NO.07

7.1 AIM: To implement 2:1 mux using conventional method and also using transmission gate
and compare both.

7.2 APPARATUS:

Computer with Microwind Software.

7.3 PROCEDURE:

Part A:

7. Create your own NMOS & PMOS transistors.

7. Use the design rules for 180 nm process.

7. Plot the characteristics of NMOS transistor

Part B:

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.

2. Instantiate NMOS or PMOS transistors from the symbol library and place them in the
editor window.

3. Connect the drains and sources of the transistors.

4. Connect VDD and GND from the symbol library to the schematic.

5. Connect inputs and output.

6. Simulate the circuits to check the logic functionality.

6.4 RESULTS:

6.5 CONCLUSIONS:

1. What is a CMOS transmission gate?

2. Explain body effect in CMOS.

EXPERIMENT NO.08

TITLE OF EXPERIMENT: Implementation CMOS combinational logic for any 4 variable

logical expression using Microwind.

8.1 AIM:

Implementation of following 4 variable logical expression using Microwind.

Z = a+b+c+d

8.2 APPARATUS:

Computer with Microwind Software.

8.3 PROCEDURE:

Part A:

1. Create your own NMOS & PMOS transistors.

Dept. of E&TC Semester: I

 D.Y. PATIL COLLEGE OF ENGINEERING, AKURDI, PUNE

Subject: VLSI Design and technology Class: B.E. (E&TC)

Practical: 50 Marks
2. Use the design rules for 90 nm process.

3. Plot the characteristics of NMOS transistor

Part B:

1. Open the Schematic Editor in Microwind. Click on the transistor symbol in the Symbol
Library on the right.

2. Instantiate NMOS or PMOS transistors from the symbol library and place them in the
editor window.

3. Connect the drains and sources of the transistors.

4. Connect VDD and GND from the symbol library to the schematic.

5. Connect inputs and output.

6. Simulate the circuits to check the logic functionality.

6.4 RESULTS:

6.5 CONCLUSIONS:

1. Explain parasitic Capacitance in CMOS.

2. What do u mean by hot electron effect.

Dept. of E&TC Semester: I