CD4538BM/CD4538BC Dual Precision Monostable

February 1988

CD4538BM/CD4538BC Dual Precision Monostable

General Description Features
The CD4538B is a dual, precision monostable multivibrator Y Wide supply voltage range 3.0V to 15V
with independent trigger and reset controls. The device is Y High noise immunity 0.45 VCC (typ.)
retriggerable and resettable, and the control inputs are inter- Y Low power Fan out of 2 driving 74L
nally latched. Two trigger inputs are provided to allow either TTL compatibility or 1 driving 74LS
rising or falling edge triggering. The reset inputs are active Y New formula: PWOUT e RC
low and prevent triggering while active. Precise control of (PW in seconds, R in Ohms, C in Farads)
output pulse-width has been achieved using linear CMOS Y g 1.0% pulse-width variation from part to part (typ.)
techniques. The pulse duration and accuracy are deter- Y Wide pulse-width range 1 ms to %
mined by external components RX and CX. The device does
not allow the timing capacitor to discharge through the tim-
Y Separate latched reset inputs
ing pin on power-down condition. For this reason, no exter-
Y Symmetrical output sink and source capability
nal protection resistor is required in series with the timing Y Low standby current 5 nA (typ.)
@ 5 V
pin. Input protection from static discharge is provided on all DC
pins. Y Pin compatible to CD4528B

Block and Connection Diagrams

Dual-In-Line Package
CD4538BM
CD4538BC

TL/F/6000 – 2
Top View

Order Number CD4538B

TL/F/6000 – 1
RX and CX are External Components
VDD e Pin 16
VSS e Pin 8

Truth Table
H e High Level
Inputs Outputs L e Low Level
u e Transition from Low to High
Clear A B Q Q v e Transition from High to Low
É e One High Level Pulse
L X X L H ß e One Low Level Pulse
X H X L H X e Irrelevant
X X L L H
H L v É ß
H u H É ß

C1995 National Semiconductor Corporation TL/F/6000 RRD-B30M105/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 and 2) Recommended Operating
If Military/Aerospace specified devices are required, Conditions (Note 2)
please contact the National Semiconductor Sales
DC Supply Voltage (VDD) 3 to 15 VDC
Office/Distributors for availability and specifications.
Input Voltage (VIN) 0 to VDD VDC
DC Supply Voltage (VDD) b 0.5 to a 18 VDC
Operating Temperature Range (TA)
Input Voltage (VIN) b 0.5V to VDD a 0.5 VDC
CD4538BM b 55§ C to a 125§ C
Storage Temperature Range (TS) b 65§ C to a 150§ C CD4538BC b 40§ C to a 85§ C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§ C

DC Electrical Characteristics CD4538BM (Note 2)

b 55§ C a 25§ C a 125§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent VDD e 5V VIH e VDD 5 0.005 5 150 mA
Device Current VDD e 10V
VDD e 15V ( VIL e VSS
All Outputs Open
10
20
0.010
0.015
10
20
300
600
mA
mA
VOL Low Level VDD e 5V 0.05 0 0.05 0.05 V

(
Output Voltage VDD e 10V l l
IO k 1 mA
0.05 0 0.05 0.05 V
VIH e VDD, VIL e VSS
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VDD e 5V 4.95 4.95 5 4.95 V

(
Output Voltage VDD e 10V l l
IO k 1 mA
9.95 9.95 10 9.95 V
VIH e VDD, VIL e VSS
VDD e 15V 14.95 14.95 15 14.95 V
VIL Low Level lIOl k 1 mA
Input Voltage VDD e 5V, VO e 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD e 10V, VO e 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e 15V, VO e 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level lIOl k 1 mA
Input Voltage VDD e 5V, VO e 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
VDD e 10V, VO e 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e 15V, VO e 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level VDD e 5V, VO e 0.4V 0.64 0.51 0.88 0.36 mA

(
VIH e VDD
Output Current VDD e 10V, VO e 0.5V 1.6 1.3 2.25 0.9 mA
VIL e VSS
(Note 3) VD e 15V, VO e 1.5V 4.2 3.4 8.8 2.4 mA
IOH High Level VDD e 5V, VO e 4.6V b 0.64 b 0.51 b 0.88 b 0.36 mA

(
VIH e VDD
Output Current VDD e 10V, VO e 9.5V b 1.6 b 1.3 b 2.25 b 0.9 mA
VIL e VSS
(Note 3) VD e 15V, VO e 13.5V b 4.2 b 3.4 b 8.8 b 2.4 mA
IIN Input Current, VDD e 15V, VIN e 0V or 15V
g 0.02 g 10 b 5 g 0.05 g 0.5 mA
Pin 2 or 14
IIN Input Current VDD e 15V, VIN e 0V or 15V
g 0.1 g 10 b 5 g 0.1 g 1.0 mA
Other Inputs
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for acutal device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.

2
 DC Electrical Characteristics CD4538BC (Note 2)
b 40§ C a 25§ C a 85§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent VDD e 5V VIH e VDD 20 0.005 20 150 mA
Device Current VDD e 10V
VDD e 15V ( VIL e VSS
All Outputs Open
40
80
0.010
0.015
40
80
300
600
mA
mA
VOL Low Level VDD e 5V 0.05 0 0.05 0.05 V

(
Output Voltage VDD e 10V l l
IO k 1 mA
0.05 0 0.05 0.05 V
VIH e VDD, VIL e VSS
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VDD e 5V 4.95 4.95 5 4.95 V

(
Output Voltage VDD e 10V l l
IO k 1 mA
9.95 9.95 10 9.95 V
VIH e VDD, VIL e VSS
VDD e 15V 14.95 14.95 15 14.95 V
VIL Low Level lIOl k 1 mA
Input Voltage VDD e 5V, VO e 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD e 10V, VO e 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e 15V, VO e 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level lIOl k 1 mA
Input Voltage VDD e 5V, VO e 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
VDD e 10V, VO e 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e 15V, VO e 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level VDD e 5V, VO e 0.4V 0.52 0.44 0.88 0.36 mA

(
VIH e VDD
Output Current VDD e 10V, VO e 0.5V 1.3 1.1 2.25 0.9 mA
VIL e VSS
(Note 3) VD e 15V, VO e 1.5V 3.6 3.0 8.8 2.4 mA
IOH High Level VDD e 5V, VO e 4.6V b 0.52 b 0.44 b 0.88 b 0.36 mA
Output Current
(Note 3)
VDD e 10V, VO e 9.5V
VD e 15V, VO e 13.5V ( VIL e VSS b 1.3
b 3.6
b 1.1
b 3.0
b 2.25
b 8.8
b 0.9
b 2.4
mA
mA
IIN Input Current, VDD e 15V, VIN e 0V or 15V
g 0.02 g 10 b 5 g 0.05 g 0.5 mA
Pin 2 or 14
IIN Input Current VDD e 15V, VIN e 0V or 15V
g 0.3 g 10 b 5 g 0.3 g 1.0 mA
Other Inputs
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for acutal device
operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.

3
AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, and tr e tf e 20 ns unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
tTLH, tTHL Output Transition Time VDD e 5V 100 200 ns
VDD e 10V 50 100 ns
VDD e 15V 40 80 ns
tPLH, tPHL Propagation Delay Time Trigger OperationÐ
A or B to Q or Q
VDD e 5V 300 600 ns
VDD e 10V 150 300 ns
VDD e 15V 100 220 ns
Reset OperationÐ
CD to Q or Q
VDD e 5V 250 500 ns
VDD e 10V 125 250 ns
VDD e 15V 95 190 ns
tWL, tWH Minimum Input Pulse Width VDD e 5V 35 70 ns
A, B, or CD VDD e 10V 30 60 ns
VDD e 15V 25 50 ns
tRR Minimum Retrigger Time VDD e 5V 0 ns
VDD e 10V 0 0 ns
VDD e 15V 0 ns
CIN Input Capacitance Pin 2 or 14 10 pF
Other Inputs 5 7.5 pF
PWOUT Output Pulse Width (Q or Q) VDD e 5V 208 226 244 ms
RX e 100 kX
(Note: For Typical Distribution, VDD e 10V 211 230 248 ms
CX e 0.002 mF
see Figure 9 ) VDD e 15V 216 235 254 ms
VDD e 5V 8.83 9.60 10.37 ms
RX e 100 kX
VDD e 10V 9.02 9.80 10.59 ms
CX e 0.1 mF
VDD e 15V 9.20 10.00 10.80 ms
VDD e 5V 0.87 0.95 1.03 s
RX e 100 kX
VDD e 10V 0.89 0.97 1.05 s
CX e 10.0 mF
VDD e 15V 0.91 0.99 1.07 s
Pulse Width Match between VDD e 5V g1 %
RX e 100 kX
Circuits in the Same Package VDD e 10V g1 %
CX e 0.1 mF
CX e 0.1 mF, RX e 100 kX VDD e 15V g1 %
Operating Conditions
RX External Timing Resistance 5.0 ** kX
CX External Timing Capacitance 0 No Limit pF
*AC parameters are guaranteed by DC correlated testing.
**The maximum usable resistance RX is a function of the leakage of the Capacitor CX, leakage of the CD4538B, and leakage due to board layout, surface
resistance, etc.

Logic Diagram

TL/F/6000 – 3
FIGURE 1

4
Theory of Operation

TL/F/6000 – 4
FIGURE 2

Trigger Operation via the input trigger without regard to the capacitor voltage.
The block diagram of the CD4538B is shown in Figure 1 , Thus, propagation delay from trigger to Q is independent of
with circuit operation following. the value of CX, RX, or the duty cycle of the input waveform.
As shown in Figures 1 and 2 , before an input trigger occurs,
the monostable is in the quiescent state with the Q output Retrigger Operation
low, and the timing capacitor CX completely charged to
The CD4538B is retriggered if a valid trigger occurs l fol-
VDD. When the trigger input A goes from VSS to VDD (while
lowed by another valid trigger m before the Q output has
inputs B and CD are held to VDD) a valid trigger is recog-
returned to the quiescent (zero) state. Any retrigger, after
nized, which turns on comparator C1 and N-Channel tran-
the timing node voltage at pin 2 or 14 has begun to rise from
sistor N1 j . At the same time the output latch is set. With
VREF1, but has not yet reached VREF2, will cause an in-
transistor N1 on, the capacitor CX rapidly discharges toward
crease in output pulse width T. When a valid retrigger is
VSS until VREF1 is reached. At this point the output of com-
initiated m , the voltage at T2 will again drop to VREF1 before
parator C1 changes state and transistor N1 turns off. Com-
progressing along the RC charging curve toward VDD. The
parator C1 then turns off while at the same time comparator
Q output will remain high until time T, after the last valid
C2 turns on. With transistor N1 off, the capacitor CX begins
retrigger.
to charge through the timing resistor, RX, toward VDD. When
the voltage across CX equals VREF2, comparator C2 chang-
es state causing the output latch to reset (Q goes low) while Reset Operation
at the same time disabling comparator C2. This ends the The CD4538B may be reset during the generation of the
timing cycle with the monostable in the quiescent state, output pulse. In the reset mode of operation, an input pulse
waiting for the next trigger. on CD sets the reset latch and causes the capacitor to be
A valid trigger is also recognized when trigger input B goes fast charged to VDD by turning on transistor Q1 n . When
from VDD to VSS (while input A is at VSS and input CD is at the voltage on the capacitor reaches VREF2, the reset latch
VDD) k . will clear and then be ready to accept another pulse. If the
CD input is held low, any trigger inputs that occur will be
It should be noted that in the quiescent state CX is fully inhibited and the Q and Q outputs of the output latch will not
charged to VDD, causing the current through resistor RX to change. Since the Q output is reset when an input low level
be zero. Both comparators are ‘‘off’’ with the total device is detected on the CD input, the output pulse T can be made
current due only to reverse junction leakages. An added significantly shorter than the minimum pulse width specifica-
feature of the CD4538B is that the output latch is set tion.

5
Typical Applications

TL/F/6000–5
TL/F/6000 – 6

TL/F/6000–7

TL/F/6000 – 8
FIGURE 3. Retriggerable Monostables Circuitry FIGURE 4. Non-Retriggerable Monostables Circuitry

TL/F/6000 – 9
FIGURE 5. Connection of Unused Sections

6
Typical Applications (Continued)

TL/F/6000 – 10
FIGURE 6. Switching Test Waveforms

RX e RXÊ e 100 kX
CX e CXÊ e 100 pF
C1 e C2 e 0.1 mF

*CL e 50 pF

TL/F/6000 – 11

TL/F/6000 – 12
Input Connections
Characteristics CD A B
tPLH, tPHL, tTLH, tTHL
VDD PG1 VDD
PWOUT, tWH, tWL
tPLH, tPHL, tTLH, tTHL
VDD VSS PG2 TL/F/6000 – 14
PWOUT, tWH, tWL
Duty Cycle e 50%
tPLH(R), tPHL(R),
PG3 PG1 PG2
tWH, tWL FIGURE 8. Power Dissipation Test
Circuit and Waveforms
*Includes capacitance of probes,
wiring, and fixture parasitic
Note: Switching test waveforms
for PG1, PG2, PG3 are
shown in Figure 6 .

TL/F/6000 – 13
FIGURE 7. Switching Test Circuit

7
Typical Applications (Continued)

TL/F/6000 – 15
TL/F/6000 – 16
FIGURE 9. Typical Normalized Distribution of Units FIGURE 12. Typical Pulse Width Error
for Output Pulse Width Versus Temperature

TL/F/6000 – 17
TL/F/6000 – 18
FIGURE 10. Typical Pulse Width Variation as a FIGURE 13. Typical Pulse Width Error
Function of Supply Voltage VDD Versus Temperature

TL/F/6000 – 19 TL/F/6000 – 20
FIGURE 11. Typical Total Supply Current Versus FIGURE 14. Typical Pulse Width Versus
Output Duty Cycle, RX e 100 kX, CL e 50 pF, Timing RC Product
CX e 100 pF, One Monostable Switching Only

8
Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4538BMJ or CD4538BCJ
NS Package Number J16A

9
CD4538BM/CD4538BC Dual Precision Monostable
Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number CD4538BMN or CD4538BCN
NS Package Number N16E

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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