4/27/2017 VLSI QnA: Interview Questions on Blocking and Nonblocking Assignments

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VLSI QnA
This blog provides VLSI interview questions.

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Friday, 23 May 2014

Interview Questions on Blocking and
Nonblocking Assignments
This post is continuation to our previous post on blocking and non­blocking assignments.
For better understanding of how the blocking and nonblocking assignments are scheduled
in Verilog, please go through this post.

Q.1) What will be the output of following code?
         module seq;
         reg clk, rst, d;
         initial
         begin
               $monitor("%g clk = %b rst = %b d = %b", $time, clk, rst, d);
               #1   clk = 0;
               #10 rst = 0; Subscribe
               #5   d = 0;
               #10 $finish; Subscribe in a reader
          end
          endmodule
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Answer) 0     clk = x   rst = x   d = x
              1     clk = 0   rst = x   d = x Enter your email address:
              11   clk = 0   rst = 0   d = x 
              16   clk = 0   rst = 0   d = 0

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Q.2) What will be the output of following code?
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         module parallel;
         reg clk, rst, d;
         initial
         begin
VLSI QnA
             $monitor("%g clk = %b rst = %b d = %b", $time, clk, rst, d); 2,375 likes
             fork
                   #1   clk = 0;
                   #10  rst = 0;
                   #5   d = 0; Liked Share
             join
             #1 display("%t Terminating simulation", $time);  You and 5 other friends like this
         end
         endmodule
(Note : fork­join block causes the statements to be evaluated in parallel, i.e. all at the
same time.)

Answer) 0     clk = x    rst = x   d = x
              1     clk = 0    rst = x   d = x
              5     clk = 0    rst = x   d = 0
             10    clk = 0    rst = 0   d = 0
Blog Archive
             11    Terminating simulation
▼  2014 (34)

http://hellovlsi.blogspot.in/2014/05/interview­questions­on­blocking­and.html 1/3
4/27/2017 VLSI QnA: Interview Questions on Blocking and Nonblocking Assignments

Q.3) What will be the output of the following code ? ►  June (5)
         blocking                                                                          nonblocking ▼  May (16)
         always @(i1 or i2)                                                          always @(i1 or i2) VLSI Glossary
         begin                                                                               begin
Interview Questions on Blocking and
                i1 = 1;                                                                              i1 = 1;
Nonblocking As...
                i2 = 2;                                                                              i2 = 2;
                #10;                                                                                 #10; Verilog "Stratified Event Queue"
                i1 = i2;                                                                             i1  <= i2; Blocking, Nonblocking Assignments and
                i2 = i1;                                                                             i2  <= i1; Verilog Race...
         end                                                                                  end Finite State Machine (FSM)
                      (a)                                                                                   (b)
Synchronous and Asynchronous resets

Answer) In the case of (a), i.e. blocking the values of i1 and i2 will be both '2', whereas in T Flip Flop
the case of (b) (nonblocking) the values of i1 and i2 will be '2' and '1' respectively. Verilog Interview Questions ­ v1.5
    
J­K Flip Flop
Q.4) What will be the output of the following code ?
         module tp; D Flip flop

                reg i1; S­R latch and flip­flop
                initial 
Verilog Interview Questions ­ v1.4
                      $monitor("\$monitor: i1 = %b", i1);
                initial  Verilog Interview Questions ­ v1.3
                begin CMOS Interview Questions ­ v1.2
                       $strobe ("\$strobe : i1 = %b", i1);
VHDL Interview Questions ­ v1.0
                       i1 = 0;
                       i1 <= 1; CMOS Interview Questions ­ v1.1
                       $display ("\$display: i1 = %b", i1);
►  April (13)
                      #1 $finish;
                end
         endmodule

Answer) $display: i1 = 0
              $monitor: i1 = 1
              $strobe : i1 = 1

Q.5) What will be the output of the following code?
         module tp;
                  reg i1, i2;
                  initial 
                  begin
                           i1 = 0;
                           i2 = 1;
                           i1 <= i2;
                           i2 <= i1;
                           $monitor ("%0dns: \$monitor: i1=%b i2=%b", $stime, i1, i2);
                           $display ("%0dns: \$display: i1=%b i2=%b", $stime, i1, i2);
                           $strobe ("%0dns: \$strobe : i1=%b i2=%b\n", $stime, i1, i2);
                    #0   $display ("%0dns: #0 : i1=%b i2=%b", $stime, i1, i2);
                    #1   $monitor ("%0dns: \$monitor: i1=%b i2=%b", $stime, i1, i2);
                           $display ("%0dns: \$display: i1=%b i2=%b", $stime, i1, i2);
                           $strobe ("%0dns: \$strobe : i1=%b i2=%b\n", $stime, i1, i2);
                           $display ("%0dns: #0 : i1=%b i2=%b", $stime, i1, i2);
                     #1  $finish;
                  end
         endmodule

Answer) 0ns: $display: i1=0 i2=1
              0ns: #0 : i1=0 i2=1
              0ns: $monitor: i1=1 i2=0
              0ns: $strobe : i1=1 i2=0
              1ns: $display: i1=1 i2=0
              1ns: #0 : i1=1 i2=0
              1ns: $monitor: i1=1 i2=0
              1ns: $strobe : i1=1 i2=0

http://hellovlsi.blogspot.in/2014/05/interview­questions­on­blocking­and.html 2/3
4/27/2017 VLSI QnA: Interview Questions on Blocking and Nonblocking Assignments
In case of any doubt regarding the above solutions, feel free to leave a comment.

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Posted by Kamlesh Bhesaniya at 22:54 

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Labels: $display, $monitor, $strobe, blocking assignments, nonblocking assignments, verilog event
queue, VLSI Interview Questions

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