International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882

90 EATHD-2015 Conference Proceeding, 14-15 March, 2015

LOW POWER & AREA EFFICIENT LAYOUT

ANALYSIS OF CMOS ENCODER
Tanuj Yadav Rajesh Mehra
Electronics & Communication department Electronics & Communication department
National Institute of Teacher‟s Training and Research National Institute of Teacher‟s Training and Research
Chandigarh Chandigarh

ABSTRACT
An Encoder is a device, circuit, transducer, software CMOS circuits use a combination of p-type and n-
program, algorithm or person that converts information type metal oxide semiconductor field-effect transistors
from one format or code to another, for the purposes of (MOSFETs) to implement logic gates and other digital
standardization, speed, secrecy, security or circuits. For the most recent CMOS feature sizes,
compressions. Encoder is mainly used for the encoding leakage power dissipation has become an overriding
of the data.It is having application in much area. The concern for VLSI circuit design [2].
purpose of this paper is to design the 4 to 2 line encoder
using universal gates with the help of CMOS logic and 2. ENCODER
the most important. The further advanced version of the
digital Encoder is 8 to 3 line Encoder, which is also A Digital Encoder more commonly called a Binary
proposed here. In this paper different design Encoder take all its data inputs one at a time and then
methodologies are used such as standard cell based converts them into a single encoded output unlike a
design, semicustom design and full custom design of the multiplexer that selects one individual data input line
Encoder to reduce area, power and size of the circuit. and then sends that data to a single output line or
The paper analyzes and optimizes area and power of the switch,. So can say that a binary encoder is a multi-input
Encoder using 45 nm technologies. combinational logic circuit that converts the logic level
“1” data at its inputs into an equivalent binary code at its
Keywords: CMOS, Encoder, Integrated circuits, Priority output.Binary number of n bit is called Binary Coded
Encoder. Decimal (BCD), a coding scheme used in digital to
encode informations. Encoders can be used in a wide
1. INTRODUCTION variety of applications. They act as feedback transducers
for motor-speed control, as sensors for measuring,
Encoders are sensors that generate digital signals in cutting and positioning, and as input for speed and rate
response to movement. Both shaft encoders, which controls. Some examples are Door control devices,
respond to rotation, and linear encoders, which respond Assembly machines, Robotics, Labeling machines, Lens
to motion in a line, are available. When used in grinding machines, x/y indication, Plotters, Testing
conjunction with mechanical conversion devices, such as machines. Encoders can use either optical or magnetic
rack-and-pinions, measuring wheels, or spindles, shaft sensing technology. Optical sensing provides high
encoders can also be used to measure linear movement, resolutions, high operating speeds, and reliable, long life
speed, and position. An encoder is a digital circuit that operation in most industrial environments. Magnetic
performs the inverse operation of a decoder. An encoder sensing, often used in such rugged applications as steel
has 2 (or fewer) input lines and n output lines. The and paper mills, provides good resolution, high
output lines as an aggregate generate the binary code operating speeds, and maximum resistance to dust,
corresponding 10 the input value [1]. An encoder is a moisture, and thermal and mechanical shock. There are
device, circuit, transducer, software program, algorithm mainly two types of encoder/decoder: memoryless and
or person that converts information from one format or with memory. The memoryless encoder/decoder will
code to another, for the purposes of standardization, only deal with current measurement without information
speed, secrecy, security or compressions. Digital about the past, while the encoder will take the past
Encoder is a Digital Device that uses binary number of n information to encoder the current measurement
bit to represent a number of base ten. "CMOS" refers to [3].Error Correcting Control is very important in modern
both a particular style of digital circuitry design and communication systems. Two correcting codes that are
the family of processes used to implement that circuitry BCH and RS codes, BCH encoder is usually
on integrated circuits (chips). implemented with a serial linear feedback shift register

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
91 EATHD-2015 Conference Proceeding, 14-15 March, 2015

(LFSR) architecture. In order to realize a higher data encoded, „n‟ are the number of output bits encoded and
rate, parallel BCH encoder should be employed [4]. In „m‟ are the number of shift registers used then (n, k, m)
digital audio technology, an encoder is a program that is used for expressing convolutional codes. [5]
converts an audio WAV file into an MP3 file, a highly-
compressed sound file that preserves the quality of a CD
recording. (The program that gets the sound selection
from a CD and stores it as a WAV file on a hard drive is
called a ripper) An MP3 encoder compresses the WAV
file so that it is about one-twelfth the size of the original
digital sound file. The quality is maintained by an
algorithm that optimizes for audio perception, losing
data that will not contribute to perception. The program
that plays the MP3 file is called aplayer. Some audio
products provide all three programs together as a
package.
Fig. 2 Convolutional Encoder [5]
Classification of Encoder
The Encoder is mainly of two types, rotary and linear Priority Encoder (PE)
encoder. Rotary Encoder is mainly used for Convert Priority encoders establish the priority of competing
Angular Position into Analog or Digital Signal, for inputs (such as interrupt requests) by outputting a binary
rotary motion and measuring angle, speed or velocity. code representing the highest-priority active input.For
Whereas the Linear Encoder Convert Linear distance producing n no. of output when there is 2^n no. of
movement to Analog or Digital Signal, for measuring inputs. A 4-bit priority encoder. This circuit basically
distance travelled, positioning, location information. converts the 4-bit input into a binary representation. If
Some further classification is also there in these two the input n is active, all lower inputs (n-1 …. 0) are
types of the encoders, as shown in figure. ignored. The circuit operation is simple. Each output is
driven by an OR-gate which is connected to the NAND-
INV outputs of the corresponding input lines. The
NAND gate of each stage receives its input bit, as well
as the NAND gate outputs of all higher priority stages.
This structure implies that an active input on stage n
effectively disables all lower stages n-1…..0. A common
use of priority encoders is for interrupt controllers, to
select the most critical out of multiple interrupt requests.
Due to electrical reasons (open collector outputs) priority
encoders with active-low inputs are also often used in
practice.
Fig.1. Encoder Tree

Convolutional Encoder
Convolutional codes are used to check and correct the
errors. It can take a single bit or multiple bits as an input
which gives matrix of encoded outputs. Bit sequence can
be altered in Digital modulation communication systems
because of noise and other external factors. To minimize
the noise factor, certain additional bits are added to the
encoded output which makes the bit error checking more
successful and it will also yields more accurate results.
This transmission of more number of bits than the
original one is used to get the original signal even in the
vicinity of noise. Convolution codes are considered to be Fig.3 4 to 2 line Priorty Encoder basic building block
best codes for controlling error and gives better and truth table.
performance. If „k‟ are the number of input bits to be

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
92 EATHD-2015 Conference Proceeding, 14-15 March, 2015

Match address encoder

In the presence of multiple matches, the MMR always
favors the highest priority match (lowest physical
address). We designed the MAE to take advantage of
this property [6]. Priority Encoder (PE) is a basic
building block in many digital and mixed-signal
systems. Unlike a simple encoder that allows only one of
its inputs at logic-1 state, a PE does not have such
restriction. It can resolve multiple logic-1 inputs and
perform encoding according to the one with the highest
Fig.4 4 to 2 line Priority Encoder using basic building priority [7].
logic gates.
3. RESULT AND SIMULATION

Fig.5 8 to 3 Bit Priority Encoder basic building block

and truth table.

Fig.7. Schematic of 4 to 2 line Encoder using NAND

gates.

Fig.6 Digital Encoder using Logic Gates

A PE resolves the highest priority match and encodes

this match location into binary format, which is used by
an off-chip SRAM to retrieve the corresponding data.
Typically, a PE is designed in two stages: (i) multiple
match resolver (MMR), and (ii) match address encoder
(MAE).

Multiple match resolver

An MMR is an n-bit input, n-bit output datapath circuit.
Assuming the active-high logic convention and highest Fig.8. Standard cell layout Design of 4 to 2 line Encoder
priority for the lowest address, an MMR.

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
93 EATHD-2015 Conference Proceeding, 14-15 March, 2015

Table .1 Area and Power consideration

Encoder Technology
Area Power
layout used
Standard cell
45 nm 32 um2 28.37 µW
based design

Semi custom 30.4

45 nm 13.82 μW
based design um2

5. CONCLUSION

This analysis has proposed two different type layout

Fig.9 .Simulation Result of 4 to 2 line Encoder with design of 4 to 2 line Encoder. Standard cell based layout
standard cell design. and semicustom based layout for the 4 to 2 line Encoder.
Area, power and complexity of the different design
methods are parameters taken for analysis.Table-1 shows
that semi custom based layout design has 5% of
reduction in the area compared to the standard cell based
design. Power consumption of the semi custom layout
design is 51.68 % less that standard cell based layout
design.

ACKNOWLEDGEMENT

The authors would also like to thank Director, National

Institute of Technical Teacher‟s Training & Research,
Fig.10. Semi Custom Design of 4 to 2 line Encoder Chandigarh, India and Mr. Mahesh Yadav for their
constant inspirations and support throughout this
research work.

REFERENCES

[1] “M. Morris Mano and Michael D. Ciletti”,

“Digital Design”, Pearson Prentice Hall, Fourth
Edition, pp.150.
[2] “Wayne Wolf”, “FPGA-Based System Design”,
Pearson Education, Third Edition, pp.682-689, 2008.
[3] W. Li and Z.C. Zhu,” Encoder and decoder design for
fault detection over networks”, IEEE International
Conference on Control Applications, pp.1785-1789,
Fig.11. Simulation Result of 4 to 2 line Encoder with September 2010.
semi custom cell design. [4] Rajesh Mehra, Garima Saini, Sukhbir Singh, “FPGA
Based High Speed BCH Encoder for Wireless
4. COMPARATIVE ANALYSIS Communication Applications” International
Conference on Communication Systems and Network
The main parameters of consideration are area, Technologies, IEEE, 2011.
complexity and power of the Encoder design in this [5] Dr. Rajesh Khanna, Abhishek Aggarwal, “SDR
paper. Table 1 shows the area and power consumption 4 Implementation of Convolutional Encoder and
to 2 line Encoder. Viterbi Decoder” International Journal of Advanced
Research in Electrical, Electronics and

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
94 EATHD-2015 Conference Proceeding, 14-15 March, 2015

Instrumentation Engineering, Vol.3, pp.9571-9578,

May 2014.
[6] Nitin Mohan, Wilson Fung and Manoj Sachdev,
“Low Power Priority Encoder and Multiple Match
Detection Circuit for Ternary Content Addressable
Memory”, IEEE, pp.253-256, 2006
[7] Wilson W. Fung and Manoj Sachdev, “High-
Performance Priority Encoder for Content
Addressable Memories”, Micronet Annual Workshop
2004.

Authors

Tanuj Yadav received the Bachelors of

Technology degree in Electronics and
Communication Engineering from Gautam
Buddha Technical Universtity Lucknow,
Uttar Pradesh, India in 2010, and pursuing
Masters of Engineering in Electronics and
Communication Engineering from National
Institute of Technical Teacher‟s Training &
Research, Punjab University, and
Chandigarh, India.

Rajesh Mehra received the Bachelors

of Technology degree in Electronics
and Communication Engineering from
National Institute of Technology,
Jalandhar, India in 1994, and the
Masters of Engineering degree in
Electronics and Communication
Engineering from National Institute of Technical
Teacher‟s Training & Research, Punjab University,
Chandigarh, India in 2008. He is pursuing Doctor of
Philosophy degree in Electronics and Communication
Engineering from National Institute of Technical
Teacher‟s Training & Research, Punjab University,
Chandigarh, India. He is an Associate Professor with the
Department of Electronics & Communication
Engineering,, National Institute of Technical Teacher‟s
Training & Research, Ministry of Human Resource
Development, Chandigarh, India. His current research
and teaching interests are in Signal and Communications
Processing, Very Large Scale Integration Design. He has
authored more than 175 research publications including
more than 100 in Journals. Mr. Mehra is member of
IEEE and ISTE.

Shanti Institute of Technology, Meerut (U.P.) - 250501, India