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Introduction To Static Timing Analysis: Cristiano Forzan

Static timing analysis provides a fast way to analyze timing in digital circuits by calculating delays along timing paths in the circuit. It works by representing the circuit as a directed acyclic graph and then summing the delays of each node and link along all topological paths. This allows it to exhaustively check all paths and find violations, but it requires defining timing constraints, path exceptions, and clock models.

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195 views

Introduction To Static Timing Analysis: Cristiano Forzan

Static timing analysis provides a fast way to analyze timing in digital circuits by calculating delays along timing paths in the circuit. It works by representing the circuit as a directed acyclic graph and then summing the delays of each node and link along all topological paths. This allows it to exhaustively check all paths and find violations, but it requires defining timing constraints, path exceptions, and clock models.

Uploaded by

indirasornakumar_672
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Introduction to

Static Timing Analysis

Cristiano Forzan

STMicroelectronics
Outline

Timing verification

Delay calculation

Constraints

NVM Design Platform – Cristiano Forzan


Dynamic Timing Simulation

Advantages Disadvantages

– Can check asynchronous – Analysis quality depends on


interfaces stimulus vectors
– No need to specify false and – Non-exhaustive – virtually
multicycle paths, clock impossible to check every
model, etc path
– Can be very accurate – Long run times
(SPICE)

NVM Design Platform – Cristiano Forzan


Static Timing Simulation

Advantages Disadvantages

– Fast – design is analyzed in – Less accurate


one pass, for one clock – Must define timing
cycle requirements / exceptions
– Exhaustive – checks all – Difficulty handling
topological paths in design asynchronous designs, false
– Does not require verification paths
environment

NVM Design Platform – Cristiano Forzan


Principles of
Static Timing Verification

Netlist is represented as DAG – Directed Acyclic


Graph
Delay values associated with nodes (Cells) and
links (Nets)
Total path delay is the sum of Path delay values
1
In
1
3 1
1 1
1
4 Out
2 1
2

NVM Design Platform – Cristiano Forzan


Path-based STA

Timing information is associated with topological


paths
– First, extract all possible topological paths
– Next, for each path calculates its delay and compare it
with endpoint (required) value
Path-based:
AT=2 2+2+3 = 7 (OK)
2
1 2+3+1+3 = 9 (OK)
3 RAT=10 2+3+3+2 = 10 (OK)
3
1 2 5+1+1+3 = 10 (OK)
AT=5 3 5+1+3+2 = 11 (Problem!)
1 5+1+2 = 8 (OK)

NVM Design Platform – Cristiano Forzan


Timing Paths Types
Four types of Timing Paths
l Input to Register (Synchronous)
l Register to Register (Synchronous)
l Register to Output (Synchronous)
l Input to Output (Asynchronous)
Each path has:
l StartPoint (Input port or FF output)
l EndPoint (Output port or FF input)
l Calculated value for path delay

In Out

In Out

NVM Design Platform – Cristiano Forzan


Outline

Timing verification

Delay calculation

Constraints

NVM Design Platform – Cristiano Forzan


Path delay calculation

The actual path delay is the sum of the Net and


the Cell delays along the timing path
– Net Delay – total time for charging/discharging all the
parasitics of a given net. It is a function of:
l Net capacitance
l Net resistance
– Cell Delay – delay arc between corresponding input
and output ports of the cell. It is a function of:
l Input transition time (Slew)
l Total output load
l Process parameters (Temperature, Power supply)

NVM Design Platform – Cristiano Forzan


Net Delay Calculation (PreLayout)
Wire Load Model
– Net length is a function of net fanout and chip area
– For a given area, averages of R and C are estimated
for different fanouts
– Net delay is calculated simply as R * C
Capacitance as a Resistance as a
function of fanout : function of fanout : For fanout = 3
Net delay = 0.046 * 0.020
1 0.015 1 0.012
2 0.030 2 0.016

3 0.046 3 0.020

NVM Design Platform – Cristiano Forzan


Cell Delay Calculation

Temperature,
Power Level,
Process

Cell delay is a function of


– Input Transition Time (calculated by previous gate)
– Total Output Capacitance (Net cap + sum of attached
Pin Caps)
– Operating Conditions

NVM Design Platform – Cristiano Forzan


Cell Delay and Slew Calculation
Delay is calculated using 2-Dimensional Nonlinear Delay Model. Main
calculation part is interpolation between nearest table values:

Total Cload (fF)


0.2 0.3 0.4 0.5
Input 0 3 4.5 6 7
Transition
(ns) 0.1 5 8 10 13

A similar model is used for the Cell Slew calculation


After calculation, delay is scaled by the operating conditions:
– Final_delay = Table_delay * Kvoltage * Ktemp * Kprocess

NVM Design Platform – Cristiano Forzan


Types of Cell Timing Arcs
Combinatorial Cells: from all inputs to output:
A

B Y

Sequential Cells: from Clock Input to outputs (propagation delay) and


from Clock Input to Data Input (setup, hold checks):

D Qn

Clk Q

NVM Design Platform – Cristiano Forzan


Outline

Timing verification

Delay calculation

Constraints

NVM Design Platform – Cristiano Forzan


Path Constraints Types

Main path constraints include:


l Setup time (Input-to-Reg and Reg-to-Reg paths)
l Hold time (Input-to-Reg and Reg-to-Reg paths)
l Input delay (Input-to-Reg and Input-to-Output paths)
l Output delay (Reg-to-Output and Input-to-Output paths)

In Out

Clk
Out
In

NVM Design Platform – Cristiano Forzan


Setup and Hold Times
Setup: amount of time data must be stable at the data pin
of FF before the clock capturing edge
Hold: amount of time data must remain stable at the data
pin of FF after the clock capturing edge

In D
Hold Check refers to the same
Clk clock edge:
TD – TCLK > THold
Hold Setup
Clk Setup Check refers to the next
Clock edge (add clock period) :
D (TCLK + TPeriod) – TD > TSetup

NVM Design Platform – Cristiano Forzan


Other constraints: Design Rules Check

Design Rules are electrical checks performed on each


gate. They are defined in the technology library
Checking min and max limits for:
l Net / Port capacitance
l Net Transition times
l Net fanout

Max capacitance example:

Total capacitive
max_capacitance
load includes
attribute from
pin load and net
Technology library
capacitance

NVM Design Platform – Cristiano Forzan

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