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Cache Quiz

This document contains an answer key and questions for a quiz on chapter 4 about cache memory. It tests knowledge of various cache memory terms like cache hit, cache miss, direct mapping, set-associative mapping, access time, and transfer rate. The relationship between access time, memory cost, and capacity is also discussed, noting that faster access time means greater cost per bit, while greater capacity means smaller cost per bit but slower access time. Different mapping techniques for cache like direct mapping, associative mapping, and set-associative mapping are defined in a few sentences.

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jamaica cancejo
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415 views3 pages

Cache Quiz

This document contains an answer key and questions for a quiz on chapter 4 about cache memory. It tests knowledge of various cache memory terms like cache hit, cache miss, direct mapping, set-associative mapping, access time, and transfer rate. The relationship between access time, memory cost, and capacity is also discussed, noting that faster access time means greater cost per bit, while greater capacity means smaller cost per bit but slower access time. Different mapping techniques for cache like direct mapping, associative mapping, and set-associative mapping are defined in a few sentences.

Uploaded by

jamaica cancejo
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ANSWER KEY QUIZ 1 MIDTERM

CHAPTER 4 CACHE MEMORY 04/23/2018

1. It is a small fast array of memory placed between the processor core and main memory that
store portions of recently referenced main memory.

a. Cache
b. Main memory
c. Registers

2. Refers to whether memory is internal or external to computer.

a. Capacity
b. Location
c. Performance

3. This is the time it takes to perform a read and write operation, that is, the time from the instant
that an address is presented to the memory to the instant that data have been stored or made
available for use.

a. Memory Cycle Time


b. Transfer Rate
c. Access Time

4. This is the rate at which data can be transferred into or out of a memory unit.

a. Memory Cycle Time


b. Transfer Rate
c. Access Time

5. Time required for the memory to “recover” before next access.

a. Memory Cycle Time


b. Transfer Rate
c. Access Time

6. It is a memory characteristic which information decays naturally or lost when electrical power is
switched off.
a. Volatile Memory
b. Nonvolatile Memory
c. ROM

7. It is a type of access method which starts at the beginning and read through in order.

a. Sequential Access Method


b. Direct Access Method
c. Random Access Method

8. It is a type of access method which individual blocks or records have unique address based on
physical location.

a. Sequential Access Method


b. Direct Access Method
c. Random Access Method

9. It is the fastest storage in memory hierarchy.

a. Cache
b. Registers
c. RAM

10. It stores data using virtual addresses.

a. Main Memory
b. Physical Cache
c. Logical Cache

11. A mapping technique that maps each block of main memory into only one possible cache line.

a. Direct Mapping
b. Associative Mapping
c. Set-Associative Mapping

12. The “natural” unit of organization of memory.

a. Addressable Units
b. Word
c. Unit of Transfer
13. It is the physical arrangement of bits to form word.

a. Physical Characteristics
b. Performance
c. Organization
14. This occurs when the information or data needed by the CPU is available in Cache.

a. Cache Hit
b. Cache Miss
c. Victim Cache

15. This occurs when the information or data needed by the CPU is not available in Cache.

a. Cache Hit
b. Cache Miss
c. Victim Cache

II

1. What is the general relationship among access time, memory cost, and capacity?

Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater capacity, slower
access time.

2. What are the differences among direct mapping, associative mapping, and set associative mapping?

In a cache system, direct mapping maps each block of main memory into only one possible cache line.
Associative mapping permits each main memory block to be loaded into any line of the cache. In set-
associative mapping, the cache is divided into a number of sets of cache lines; each main memory
block can be mapped into any line in a particular set.

PREPARED BY:

SABLAY, KRISTINE JOY CANCEJO, JAMAICA

CUREG, APRIL TAGUIBAO, ADRIAN KEITH

PADDAYUMAN, JAYSON MALLILLIN, JOHN

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