INTERFACING ADC/DAC

AIM:
a) To interface the DAC unit to microprocessor and to write an ALP
to convert the given digital word to analog voltage and also to
generate sawtooth, triangular and sinewaves.
b) To interface ADC unit to microprocessor and to write an ALP to
convert the given analog voltage to digital word.

APPARATUS REQUIRED:
8085 microprocessor kit, ADC/DAC interfacing board, CRO probe,
CRO, power supply(variable), digital multimeter and connecting wires.
THEORY:
DAC INTERFACE SECTION:
DAC 0800 is a monolithic, high speed, current output D/A Converter. Its
unique features are:

 Typical settling time of 100ns

 Complementary current outputs
 Differential output voltages of 20V peak to peak with simple
resistor load
 2-quadrant wide range multiplying capability

The DAC interface section comprises of

i. I/O Decoding
ii. D/A conversion circuit
I/O DECODING:
The IC’s 74LS138 and 74LS00 form the address decoding logic in this
interface board. The address lines A3, A4 and A5 are connected to pin
1, pin2 and pin3 of 74LS138 respectively.

The address lines A6 and A7 are Nanded together and the Nand gate
output is connected to pin 6 of 74LS138. Pin 4 is ground. Thus with

A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 0 0 X X X
=C0(hex)

DAC1 is selected.

D/A CONVERSION CIRCUIT:

The design comprised of the latch 74LS273, DAC 0800 and the
current to voltage converting circuitry using OPAMP-741. DAC 0800 is
configured for bipolar output operation.

Current to voltage conversion circuit is designed using OPAMP-741.

This circuit converts the current output of DAC 0800 into equivalent
analog voltage. Complimentary current outputs IOUT, IOUT are
connected to inverting and non-inverting output of OPAMP-741. In
order to have the output voltage variation from -5V to +5V, a 2.2
feedback resistor has been selected.
The DAC outputs are available at the 5 pin connector (P3). DAC output
is terminated at pin 10 of the connector P3.

ADC INTERFACE SECTION:

ADC-0809 is a monolithic CMOS device, with an 8-bit A/D converter,
8channel multiplexer and microprocessor compatible control logic.
The main features of ADC-0809 are,
1. 8-bit resolution
2. 100µs conversion time
3. 8-channel multiplexer with latched control logic
4. No need for external zero or full scale adjustment
5. Low power consumption – 15mw
6. Latched tristate output
I/O DECODING:
The device contains 2-channel single ended analog signal multiplexer.
A particular input channel is selected by using the address decoder.
Table shows the input states for the address lines to select any channel.
The address is latched into the decoder on the low to high transition of
the address latch enable signal (ALE).
The A/D converter’s successive approximation register is reset on the
positive edge of the start conversion pulse.
The conversion is begun on the falling edge of SOC. End of conversion
will go low between 0 to 8 clock pulses after the rising edge of start of
conversion.
Selected analog Address line
signal ADD C ADD B ADD A
IN0 0 0 0
IN1 0 0 1
IN2 0 1 0
IN3 0 1 1
IN4 1 0 0
IN5 1 0 1
IN6 1 1 0
IN7 1 1 1

A/D CONVERSION CIRCUIT:

The channel select address pins ADD A, ADD B, ADD C and ALE of
ADC0809 are connected to the Data bus through a latch 74LS174.
The eight data outputs of ADC-0809 are connected to D0-D7 through a
buffer 74LS244. Provision is also made to display the data output by
means of LEDs, using a latch 74LS374. This latch is allotted by the End
of conversion signal. Thus, after the conversion is completed, at the
rising edge of EOC, the 74LS374 latches the digital output of ADC0809.
The LEDs which are connected to output pins of the latch, display the
digital data automatically.
The EOC of ADC0809 can be connected to RST5.5 or RST6.5 or
RST7.5. So the EOC output can be used to interrupt the CPU in turn, can
input the digital data from ADC0809. Moreover the EOC output is
connected to D0 through a tristate buffer 74LS125. Thus the transfer of
data is also possible by means of polling.
Start of conversion can be given externally using the “SOC Switch”
available on board. SOC can also be controlled using the ‘D’ flip flop
74LS74. PCLK available at the VXT Bus is divided by 2 by the D flip
flop 74LS74 to provide a input clock of 750KHz to ADC.
The channel inputs (IN0-IN7) are terminated at a 12 pin header. A 1K
trimpot can be used for demonstration purposes. It is connected to
channel 0, however provision is also there onboard for connecting
channel 1 to 7.
A 3 to 8 decoder 74LS138 is employed to generate I/O decoding logic.
Pin-1, Pin-2 and Pin-3 of 74LS138 are connected to address lines A3,
A4 and A5 respectively.
Thus, the buffer 74LS244 which transfers the converted data outputs to
databus is selected when
A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 0 1 X X X

=C8(hex)
The I/O address for the latch 74LS174 which latches the databus to
ADD0, ADD1, ADD2 and ALE is
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 0 0 X X X

=E0(hex)
The start of conversion pulse can be given by means of software also.
The flip flop 74LS74 which transfers the D0 line status to the SOC pin
of the ADC0809 is selected, when
A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 1 0 X X X

=D0(hex)
The EOC output of ADC0809 is transferred to the data line D0, when
74LS125 is selected with address,
A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 1 1 X X X

=D8(hex)

PROGRAM-1:
AIM:
To obtain a output of 0 volts at DAC1.
Since DAC0800 is an 8-bit DAC and the output voltage variation is
between -5V to +5V. The digital data input and the corresponding output
voltages are presented in the following table.
Input Data in Hex Output Voltage
00 -5.00
01 -4.96
02 -4.92
. .
. .
7F 0.00
. .
. .
FD 4.92
FE 4.96
FF 5.00

Execute the following program and observe that the output voltage at
DAC1 is 0 volts.
 MEMORY
OP-CODE LABEL MNEMONICS
LOCATION
ORG 4100H
4100 3E,7F MVI A, 7F
4102 D3,C0 OUT C0H
4104 76 HLT

PROGRAM-2:
AIM:
To create a saw tooth wave at the output of DAC1.Output digital data
from 00 to FF in constant steps of 01 to DAC1. Repeat this sequence
again and again. As a result, a saw-tooth wave will be generated at
DAC1 output.
MEMORY
OP-CODE LABEL MNEMONICS
LOCATION
ORG 4100H
4100 3E, 00 START MVI A, 00
4102 D3, C0 L1 OUT C0H
4104 3C INR A
4105 C2, 02, 41 JNZ L1
4108 C3, 00, 41 JMP START

PROGRAM-3:
To generate a triangular waveform at DAC1 output.
The following program will generate a triangular wave at DAC1 output.
 MEMORY
OP-CODE LABEL MNEMONICS
LOCATION
ORG 4100H
4100 2E, 00 START MVI L, 00
4102 7D L1 MOV A, L
4103 D3, C0 OUT C0H
4105 2C INR L
4106 C2, 02, 41 JNZ L1
4109 2E, FF MVI L, FFH
410B 7D L2 MOV A, L
410C D3, C0 OUT C0H
410E 2D DCR L
410F C2, 0B, 41 JNZ L2
4112 C3, 00, 41 JMP START

PROGRAM-4:
AIM:
To generate a sine-wave at DAC1 output.
A lookup table is provided in the program for sine-wave generation.
Output data continuously to DAC1 from this lookup table. Verify, using
a CRO at DAC1 output, that the waveform is a sinewave. The data for
lookup table is arrived by experiment.
MEMORY
OP-CODE LABEL MNEMONICS
LOCATION
ORG 4100H
4100 21, 10, 41 START LXI H, 4110H
4103 0E, 46 MVI C, 46
4105 7E LOOP MOV A, M
4106 D3, C0 OUT C0H
4108 23 INX H
4109 0D DCR C
 410A C2, 05, 41 JNZ LOOP
410D C3, 00, 41 JMP START

LOOKUP:
MEMORY LOCATION DATA
4110 7F, 8A, 95, A0
4114 AA, B5, BF, C8
4118 D1, D9, E0, E7
411C ED, F2, F7, FA
4120 FC, FE, FF, FE
4124 FC, FA, F7, F2
4128 ED, E7, E0, D9
412C D1, C8, BF, B5
4130 AA, A0, 95, 8A
4134 7F, 74, 69, 5F
4138 53, 49, 3F, 36
413C 2D, 25, 1D, 17
4140 10, 0B, 07,04
4144 01, 00, 01, 04
4148 07, 0B, 10, 17
414C 1D, 25, 2D, 36
4150 3F, 49, 53, 5F
4154 69, 74

PROGRAM-5:
AIM:
In a real-time application, input of data and processing of data are
indispensable.
The following programs initiate the conversion process, checks the EOC
pin of ADC-0809 as to whether the conversion is over and then inputs
the data to the processor. It also instructs the processor to store the
converted data at RAM location 4150 (hex).
MEMORY
OP-CODE LABEL MNEMONICS
LOCATION

4100 3E, 00 START MVI A, 00

4102 D3, E0 OUT E0
4104 3E, 08 MVI A, 08
4106 D3, E0 OUT E0
4108 3E, 01 MVI A, 01
410A D3, D0 OUT D0
410C AF XRA A
410D AF XRA A
410E AF XRA A
410F 3E, 00 MVI A, 00
4111 D3, D0 OUT D0
4113 DB, D8 LOOP IN D8
4115 E6, 01 ANI 01
4117 FE, 01 CPI 01
4119 C2, 13, 41 JNZ LOOP
411C DB, C8 IN C8
411E 32, 50, 41 STA 4150H
4121 76 HLT

Execute this program. Compare the data displayed at the LEDs with that
stored at location 4150H.
 FREQUENCY MEASUREMENT
Aim: To measure the frequency of the sine waveform.

Apparatus required: Bread board, Connecting wires, resistors, Op-amp, CRO, Function
generator, CRO probes, Power supply, Microprocessor kit.

Theory: The sine wave whose frequency is to be measured can be applied to zero crossing
detector. Since the number of zero crossings for every cycle is two, the number of zero
crossing for a time interval of 0.5 seconds is equal to frequency. For this a square wave form
of frequency 1 Hz. is generated using 8253 operating it in mode 3 and rising edge of the
square wave form is checked. Once the raising edge is found the number of zero crossings is
counted until the falling edge of the square wave. This count is equal to frequency and can be
displayed on address field.

To generate a square wave of 1 Hz frequency the 8253 is kept in mode 3. Since the clock
frequency is 3 MHz, the count required to generate square wave of 1 Hz is

Count= The clock frequency/the desired frequency of square wave

= 300000/1=300000

Since the maximum count that can be loaded in a 16 bit counter is 65,535, we have to use two
counters for count value. 3,00,00. So we use the first counter with a count 3000 and second
counter with a count 1000. We use two counters counter 0 with count 3000 and the counter 1
with a count 1000.

Circuit Diagram
Algorithm
1. Initialize BC register to 0000.

2. Initialize port A and port B of 8255 as input ports

3. Initialize counter 0 in mode 3

4. Load the count 3000 in the counter

5. Initialize counter 1 in mode 3

6. Load the count 1000 in the counter

7. Read port B0 pin

8. Check for rising edge of the square wave form

9. If it is found read port A0, Otherwise go to step 7

10. Call subroutine synch that find falling edge of the output of ZCD

11. Find falling edge

12. Increment count.

13 .Call subroutine for finding rising edge

14. If rising edge is found increment the count

15. Read port B0. If it is high go to step 10, otherwise

16. Call subroutine conversion that convert the BC register contents in to single digits and
store from locations form 4600.

17 Call subroutine display that display the contents of data stored from locations 4600 to
4603 on address field

18.Stop th eprogram

Subroutine synch

1. Read Port A

2. And Immediate with 01

2. Check for zero, if it is not go to step1

3. Else return to main program

Subroutine REDGE

1. Read Port A

2. And Immediate with 01

2. Check for non-zero, if it is not go to step1

3. Else return to main program

Subroutine Conversion

1. Get the contents of C register and separate in to two digits.

2. Store the digits in locations 4602 and 4603.

3. Get the contents of B register and separate in to two digits.

4. Store the digits in locations 4600 and 4601

5. Return to main program

Subroutine Display

1. Push the contents of PSW and BC register pair to stack pointer

2. Initialize 8279 to display the contents on Address field

3. Initialize HL register pair with 4600

4.Call monitor program which display the contents of 4600 to 4603 on address field

5. Retrieve the contents of PSW and BC register from stack pointer.

6. Return to main program

PROGRAM:
MEMORY MACHINE LABEL NEMONICS
LOCATION CODE
4100 01,00,00 LXI B,0000
4103 3E,92 MVI A,92
4105 D3,0F OUT 0F
4107 3E,37 MVI A,37
4109 D3,CE OUT CE
410B 3E,00 MVI A,00
410D D3,C8 OUT C8
410F 3E,30 MVI A,30
4111 D3,C8 OUT C8
4113 3E,77 MVI A,77
4115 D3,CE OUT CE
4117 3E,00 MVI A,00
4119 D3,CA OUT CA
411B 3E,10 MVI A,10
411D D3,CA OUT CA
411F DB,0D LOOP IN 0D
4121 E6,01 ANI 01
4123 CA,1F,41 JZ LOOP
4126 CD,00,42 LOOP1 CALL SYNC
4129 03 INXB
412A CD,00,43 CALL REDGE
412D 03 INX B
412E DB,0D IN 0D
4130 E6,01 ANI 01
4132 C2,26,41 JNZ LOOP1
4135 CD,50,41 CALL CONVERSION
4138 CD,00,45 CALL DISPLAY
413B 76 HLT

CONVERSION:
MEMORY MACHINE LABEL NEMONICS
LOCATION CODE
4150 79 MOV A,C
4151 E6,0F ANI 0F
4153 32,03,46 STA 4603
4156 79 MOV A,C
4157 E6,F0 ANI F0
4159 0F RRC
415A 0F RRC
415B 0F RRC
415C 0F RRC
415D 32,02,46 STA 4602
4160 78 MOV A,B
4161 E6,0F ANI 0F
4163 32,01,46 STA 4601
4166 78 MOV A,B
4167 E6,F0 ANI F0
4169 0F RRC
416A 0F RRC
416B 0F RRC
416C 0F RRC
416D 32,00,46 STA 4600
4170 C9 RET

SYNC:
MEMORY MACHINE LABEL NEMONICS
LOCATION CODE
4200 DB,0C IN 0C
4202 E6,01 ANI 01
4204 C2,00,42 JNZ SYNC
4207 C9 RET

REDGE:
MEMORY MACHINE LABEL NEMONICS
LOCATION CODE
4300 DB,0C IN 0C
4302 E6,01 ANI 01
4304 CA,00,43 JZ REDGE
4307 C9 RET

DISPLAY:
MEMORY MACHINE LABEL NEMONICS
LOCATION CODE
4500 F5 PUSH PSW
4501 C5 PUSH B
4502 3E,03 MVI A,03
4504 0E,09 MVI C,09
4506 21,00,46 LXI H,4600
4509 CD,05,00 CALL 0005
450C C1 POP B
450D F1 POP PSW
450E C9 RET
 STEPPR MOTOR INTERFACE

AIM:
To interface the given stepper motor to 8085 Microprocessor kit and write an ALP to
run the motor in both clockwise and anticlockwise directions.

APPARATUS REQUIRED:
Stepper motor, microprocessor kit, stepper motor, interfacing unit

THEORY:

STEPPER MOTOR:
A motor in which the rotor is able to assume only discrete stationary angular
displacement is a stepper motor. The rotary motion occurs in a stepwise manner from one
equilibrium position to the next.

Stepper motor control is a very popular application of microprocessor in control area.

They are widely used in (simple position control systems in the open and closed loop mode) a
variety of application such as computer peripherals (printers, disk driver , etc..) and in the
areas of process control machine tools, medicine, numerically controlled machines and
robotics.

CONSTRUCTIONAL FEATURES:

3600

------------------------------

NS * Nr

where ,

Ns is the No. of the stator poles.

Nr is the No. of pairs of the rotor poles.

Generally step size of the stepper motor depends upon Nr. These stable positions can be
attained by simply energising the winding on any one of the stator poles with a DC. There are
three different schemes available for “stepping” a stepper motor. These are:

(a) Wave scheme

(b) 2-phase scheme and
(c) Half stepping or mixed scheme.

Here we are going to use 2-phase scheme for stepping a stepper motor.
 2-PHASE SCHEME:
In this scheme, any two adjacent stator windings are energised. There are two
magnetic fields active in quadrature and none of the rotor pole face can be in direct
alignment with the stator poles. A partial but symmetric alignment of the rotor poles
is of course possible.

Typical equilibrium conditions of the rotor when the windings on two

successive stator poles are excited are illustrated in the fig. In step (a), A1 and B1 are
energised. The pole-face S1 tries to align itself with the axis of A1 (N) and the pole
face S2 with B1 (N). The north pole N3 of the rotor finds itself in the neutral zone
between A1 (N) and B2 (N). S1 and S2 of the rotor, position themselves
symmetrically with respect to the two stator north pole.

Next, when B1 and A2 are energised. S2 tends to align with B1 (N) and S3
with A2 (N). Of course, again under equilibrium conditions, only partial alignment is
possible and N1 finds itself in the neutral region, midway between B1 (N) and A2 (N)
[step (b)]. In step (c), A2 and B2 are on. S3 and S1 tend to align with A2 (N) and B2
(N), respectively with N2 in the neutral zone. Step (d) illustrates the case when A1
and B2 are on.

The step angle is 300 as in the wave scheme. However, the rotor is offset by
150 in the 2-phase scheme with respect to the wave scheme. A total of 12 steps are
required to move the rotor by 3600 (mechanical). 2-phase drives produce more torque
than the wave drives.

The switching sequence for the 2-phase scheme is given in the below table:

ANTICLOCKWISE CLOCKWISE
STEP A1 A2 B1 B2 steps A1 A2 B1 B2
1 1 0 0 1 1 1 0 1 0
2 0 1 0 1 2 0 1 1 0
3 0 1 1 0 3 0 1 0 1
4 1 0 1 0 4 1 0 0 1

DRIVING CIRCUITRY:
Stepper motor requires logic signals of relatively high power. In these boars the
silicon Darlington pair (TIP 122) transistors are used to supply that required power. The
driving pulses are generated by the interface circuit. The input for the interface circuit is TTL
pulses generated under software control using the microprocessor kit. The TTL levels of
pulses sequence from the data bus is translated to high voltage output pulses using a buffer
7407 with open collector.

The darlington pair transistor (TIP 122) drive the stepper motor as they withstand
higher current. A 220 ohm resistor and an IN 4148 diode are connected between the power
supply and darlington pair collector for supporting fly back current.

The data lines D0-D3 and D4-D7 are used to drive the 8 TIP 122 available on this
board as shown in the appendix A. The four collector points of each TIP 122 are brought to
two 5 pin connectors P2 & P3 to connect two different stepper motors. With this board it is
possible to connect stepper motor of torque ranging from 2kg to 20kg wit operating voltages
of 12V, 24V, & 6V.

PROGRAM:
To run a stepper motor for required angle within 3600 which is equivalent to 256 steps.

Memory location Machine codes label Nemonics

4100 OE HEX DATA MVI C, HEX DATA

4102 21 20 41 START LXI H, LOOK UP
4105 06 04 MVI B,04
4107 7E REPT MOV A,M
4108 D3 C0 OUT CO
410A 0D DCR C
410B CA 24 41 JZ END
410E 11 03 03 LXI D,COUNT
4111 00 DELAY NOP
4112 1B DCX D
4113 7B MOV A,E
4114 B2 ORA D
4115 C2 11 41 JNZ DELAY

4118 23 INX H

4119 05 DCR B

411A C2 07 41 JNZ REPT

411D C3 02 41 JMP START

4120 09 05 06 0A LOOK DB 09 05 06 0A
UP
4124 76 END HLT
PROGRAM:
To run stepper motor in both forward and reverse directions with delay.

Memory location Machine codes label Nemonics

4100 ORG 4100H

4100 OE 20 START MVI C, 20H

4102 21 3F 41 FORWD LXI H, FORLOOK

4105 CD 21 41 CALL ROTATE

4108 OD DCR C

4109 C2 02 41 JNZ FORWD

410C CD 35 41 CALL STOP

410F OE 20 MVI C,20H

4111 21 43 41 REVES LXI H,REVLOOK

4114 CD 21 41 CALL ROTATE

4117 OD DCR C

4118 C2 11 41 JNZ REVES

411B CD 35 41 CALL STOP

411E C3 00 41 JMP START

4121 06 04 ROTATE MVI B,04H

4123 7E REPT MOV A,M

4124 D3 C0 OUT 0C0H

4126 11 03 03 LXI D,0303H

4129 1B LOOP 1 DCX D

412A 7B MOV A,E

412B B2 ORA D

412C C2 29 41 JNZ LOOP1

412F 23 INX H

4130 05 DCR B

4131 C2 23 41 JNZ REPT

4134 C9 RET

4135 11 FF FF STOP LXI D,FFFFH

4138 1B LOOP 2 DCX D

4139 7B MOV A,E

413A B2 ORA D
413B C2 38 41 JNZ LOOP 2

413E C9 RET

413F 09 05 06 0A FORLOOK DB 09H,05H,06H,0AH

4143 0A 06 05 09 REVLOOK DB 0AH,06H,05H,09H

4147 76 END HLT

 TRAFFIC LIGHT CONTROL INTERFACE
AIM:
To interface the traffic light control system board to 8085
microprocessor kit and write an assembly language program for the
given traffic conditions.
APPARATUS REQUIRED:
8085 microprocessor kit, traffic light control system board, 26 pin port
THEORY:
 Figure shows a simple arrangement and pin connections for
microprocessor based traffic control. All ports of 8255 have been
programmed as output ports. Three types of LED’s have been used, red,
yellow and green. Green light glows to allow crossing, yellow to make
alert and red does not allow crossing. Eight dual colour LED’s are
provided for pedestrian crossing. These LED’s change their colour to red
or to green. When the LED is ON it shows green colour and when it is
OFF it shows red colour.
The following traffic control states are for the experiment:
State1: Vehicles can go from South to North.
State2: Wait state.
State3: Vehicles can go from East to West.
State4: Wait state.
State5: Vehicles can go from North to South.
State6: Wait state.
State7: Vehicles can go from West to East.
State8: Wait state.
State9: All pedestrians can cross.
State10: Wait state.
Since the LED is an output device, all 8255 ports are assumed to
be output ports in mode 0. Therefore the control word is 80H. For
the state 1, the green LED connected to pin PA4 must glow and the
red LED’s connected to pins PA1, PB3, PA3 must glow. Also
pedestrians must be in OFF conditions. Therefore the data that is to
be sent to the ports A, B and C are 1A, F8, 00 respectively.
DIRECTIONS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DATA
South-North 0 0 0 1 1 0 1 0 1A
DIRECTIONS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DATA
South-North 1 1 1 1 1 0 0 0 F8
 The above data is sent to the respective port to allow the vehicle
from south to north. Similarly all the data’s are sent to the port for
the further process

Port A Data table:

DIRECTIONS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 DATA
South-North 0 0 0 1 1 0 1 0 1A
Wait-1 0 1 1 0 1 0 0 0 68
East-West 1 0 0 0 1 0 0 0 88
Wait-2 1 0 1 0 1 0 0 0 A8
North-South 1 0 0 0 1 0 1 0 8A
Wait-3 1 0 0 0 0 1 1 0 86
West-East 1 0 0 0 0 0 1 1 83
Wait-4 1 0 0 0 0 1 1 0 86
All pedestrians 1 0 0 0 1 0 1 0 8A
Wait-5 0 1 0 0 1 0 1 0 4A

Port B Data table:

DIRECTIONS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 DATA
South-North 1 1 1 1 1 0 0 0 F8
Wait-1 1 1 1 1 1 0 0 0 F8
East-West 1 1 1 1 1 0 1 0 FA
Wait-2 1 1 1 1 0 1 0 0 F4
North-South 1 1 1 1 0 0 0 1 F1
Wait-3 1 1 1 1 0 1 0 0 F4
West-East 1 1 1 1 1 0 0 0 F8
Wait-4 1 1 1 1 1 0 0 0 F8
All pedestrians 0 0 0 0 1 0 0 0 08
Wait-5 1 1 1 1 1 0 0 0 F8
Program
Memory code Label Mnemonics Comments
location
4100 3E,80 MVIA,80 Initialize all ports in
4102 D3,OF OUT OF Output port
4104 3E,1A START MVIA,1A
4106 D3,OC OUT OC Send port A and port B
4108 3E,F8 MVIA,F8 data of state 1 to
410A D3,OD OUT OD respective ports
410C CD,85,41 CALL DELAY1
410F 3E,68 MVIA,68
4111 D3,OC OUT OC Send port A and port B
4113 3E,F8 MVIA,F8 data of wait state to
4115 D3,OD OUT OD respective ports
4117 CD,75,41 CALL DELAY2
411A 3E,88 MVIA,88 Send port A and port B
411C D3,OC OUT OC data of state 2 to
411E 3E,FA MVIA,FA respective ports
4120 D3,OD OUT OD
4122 CD,85,41 CALL DELAY1
4125 3E,A8 MVIA,A8 Send port A and port B
4127 D3,OC OUT OC data of wait state to
4129 3E,F4 MVIA,F4 respective ports
412B D3,OD OUT OD
412D CD,75,41 CALL DELAY2
4130 3E,8A MVIA,8A
4132 D3,OC OUT OC Send port A and port B
4134 3E,F1 MVIA,F1 data of state 3 to
4136 D3,OD OUT OD respective ports
4138 CD,85,41 CALL DELAY1
413B 3E,86 MVIA,86
413D D3,OC OUT OC Send port A and port B
413F 3E,F4 MVIA,F4 data of wait state to
4141 D3,OD OUT OD respective ports
4143 CD,75,41 CALL DELAY2
4146 3E,83 MVIA,83
4148 D3,OC OUT OC Send port A and port B
414A 3E,F8 MVIA,F8 data of state 4 to
414C D3,OD OUT OD respective ports
414E CD,85,41 CALL DELAY1
4151 3E,86 MVIA,86 Send port A and port B
4153 D3,OC OUT OC data of wait state to
4155 3E,F8 MVIA,F8 respective ports
4157 D3,OC OUT OC
4159 CD,75,41 CALL DELAY2
415C 3E,8A MVIA,8A Send port A and port B
415E D3,OC OUT OC data of state 5 to
4160 3E,08 MVIA,08 respective ports
4162 D3,OD OUT OD
4164 CD,85,41 CALL DELAY1
4167 3E,4A MVIA,4A Send port A and port B
4169 D3,OC OUT OC data of wait state to
416B 3E,F8 MVIA,F8 respective ports
416D D3,OD OUT OD
416E CD,75,41 CALL DELAY2
4172 C3,04,41 JUMP START
4175 OE,14 DELAY 2 MVIC,14
4177 21,94,F6 LOOP 2 LXIH,F694
417A 2B LOOP 1 DCX,H Initialize count
417B 7D MOV A,L
417C B4 ORA,A
417D C2,7A,41 JNZ LOOP1
4180 OD DCR, C
4181 C2,77,41 JNZ LOOP2
4184 C9 RET
4185 OE,14 DELAY 1 MVIC,84
4187 21,94,F6 LOOP 4 LXIH,93F2
418A 2B LOOP 3 DCX,H Initialize count
418B 7D MOV A,L
418C B4 ORA,A
418D C2,8A,41 JNZ LOOP3
4190 OD DCR,C
4191 C2,87,41 JNZ LOOP4
4194 C9 RET