SRM UNIVERSITY

FACULTY OF ENGINEERING AND TECHNOLOGY

SCHOOL OF COMPUTING
DEPARTMENT OF CSE
COURSE PLAN

Course Code : CS0207

Course Title : Computer Organization and Architecture
Semester : III
Course Time : July – Nov 2012

D
Day
Hour Timing
Monday 2nd 9.35-10.25
Tuesday 4th 11.25-12.15
Wednesday
Thursday 3rd 10.35-11.25
Friday 1st 8.45-9.35

Location : S.R.M.E.C – Tech Park ( 8th floor )

Faculty Details
Sec. Name Office Office hour Mail id
B C.Malathy Tech Park 8.30-4.00 p.m [email protected]

Required Text Books:

1. Carl Hamacher,”Computer Organization”,Fifth Edition,McGrawHill
International Edition, 2002
2. P.Pal Chaudhuri, "Computer Organization and Design" , 2nd Edition, PHI ‘
2003
3. William Stallings , “Computer Organization and Architecture – Designing for
Performance”, PHI, 2004.
4. John P.Hayes, "Computer Architecture and Organization", III Edition,
McGraw Hill International Editions,1998.
Web resources
www.amazon.com
www.freebookcentre.com
Prerequisite : CS0102 – Digital computer fundamentals
CS0205—Microprocessor and System Interfacing

Objectives
1. Gives a knowledge of various architectures
2. CPU, Control unit, I/O Processing
3. Memory and its types
4. Design of the above components
Assessment Details
Attendance : 5 Marks
Cycle Test – I : 10 Marks
Surprise Test – I : 5 Marks
Cycle Test – II : 10 Marks
Model Exam : 20 Marks

Test Schedule

S.No. DATE TEST TOPICS DURATION

1 Cycle Test - I Unit I & II 2 periods
2 As per calendar Cycle Test - II Unit III & IV 2 periods
3 Model Exam All 5 units 3 Hrs

Outcomes
Students who have successfully completed this course will have full understanding
of the following concepts

Course outcome Program outcome

To learn An ability to understand the basic functioning

The basic functional units, operational of computer.
concepts and To understand the concepts of addressing
The basic memory operations, addressing modes a
modes. To solve various ALU operations.
Basic ALU functions (operations) To implement booth algorithm
Control unit design and memory and its types To understand various types of memory
Input and output processing – bus interface concepts I/O processing.
I/O interface

Detailed Session Plan

UNIT-I INTRODUCTION
Evolution of Computer Systems-Computer Types-Functional units-Basic operational concepts-
Bus structures-Memory location and addresses-memory operations- Addressing modes-Design of
a computer system-Instruction and instruction sequencing, RISC versus CISC
Sess Teachin
Time
ion Topics to be covered Ref g Testing Method
(min)
No. Method
Evolution of Computer Systems Group discussion
1 50 1,2 PPT
Quiz
Computer Types Objective type test
2 50 1,2 PPT
Quiz
3 Functional units 50 1 PPT Quiz
Basic operational concepts, Bus Quiz
4 structures 50 1 PPT

Memory location and addresses- Quiz

5 50 1,3 PPT
memory operations
Addressing modes Quiz
6 50 1,3 PPT
Objective type test
 7 Design of a computer system 50 2 PPT Quiz, Assignment
Instruction and instruction sequencing Group discussion
50 1,3 PPT
8
RISC versus CISC Group discussion
9 50 1,3 PPT
UNIT-II CENTRAL PROCESSING UNIT
Introduction-Arithmetic Logic Unit - Fixed point arithmetic, floating point arithmetic-Execution of a
complete instruction-Basic concepts of pipelining
10 Introduction-Arithmetic Logic Unit 50 1,2 PPT Quiz
Fixed point arithmetic Quiz
11 50 1,2 PPT
Brain storming
Fixed point arithmetic Quiz
12 50 1,2 PPT
Surprise Test
Floating point arithmetic Group discussion
13 50 1,2 PPT
Quiz
Floating point arithmetic Group discussion,
14 50 1,2 PPT
Quiz
15 Floating point arithmetic 50 1,2 PPT Quiz, Assignment
Execution of a complete Quiz
16 50 1,2 PPT
instruction
17 Basic concepts of pipelining 50 1,2 PPT Quiz
18 Basic concepts of pipelining 50 1,2 PPT Quiz
UNIT-III CONTROL UNIT DESIGN
Introduction-Control Transfer-Fetch cycle - Instruction Interpretation & Execution - Hardwired
control -
Microprogrammed control
Introduction-Control Transfer Quiz
19 50 2 BB,PPT Group discussion
Objective type test
Fetch cycle Quiz
20 50 2 BB,PPT
Group discussion
21 Fetch cycle 50 2 BB,PPT Quiz
Instruction Interpretation & Execution Quiz
22 50 1,2 BB,PPT
Surprise Test
Instruction Interpretation & Execution Quiz
23 50 1,2 BB,PPT
Group discussion
Hardwired control Quiz
24 50 1,2 BB,PPT
Hardwired control Quiz
25 50 1,2 BB,PPT
Group discussion
26 Micro programmed control 50 1,2 BB,PPT Quiz
Micro programmed control Quiz
27 50 1,2,3 BB,PPT
Brain storming
UNIT-IV MEMORIES AND SUBSYSTEMS
Semiconductor memory - Static and Dynamic -Associative memory- Cache memory- Virtual
memory-
Secondary memories-Optical magnetic tape & magnetic disks & controllers
Semiconductor memory- Static and Group discussion
28 50 1,2,3 BB
Dynamic memory Assignment
 Static and Dynamic memory Group discussion
29 50 1,2,3 BB
Quiz
Associative memory Group discussion
30 50 1,2,3 BB
Assignment
Associative memory Group discussion
31 50 1,2,3 BB
Assignment
Cache memory Objective type test
32 50 1,2,3 BB Quiz
Group discussion
Virtual memory Quiz
33 50 1,2,3 BB Group discussion

Secondary memories-Optical Objective type test

34 50 1,2,3 BB
magnetic tape
Magnetic disks & controllers Objective type test
35 50 1,2,3 BB
Magnetic disks & controllers Quiz
36 50 1,2,3 BB
Group discussion
UNIT-V I/O PROCESSING
Introduction-Data transfer techniques- Bus Interface- I/O Channel-I/O Processor, I/O devices -
Direct memory access.

Introduction-Data transfer techniques Group discussion

37 50 1,2 BB
Bus Interface Objective type test
38 50 1,2 BB
39 I/O Channel 50 1,2 BB Brain storming
40 I/O Processor 50 1,2 BB Brain storming
I/O Processor Surprise test
41 50 2,3 BB
Quiz
42 I/O devices 50 2,3 BB Assignment
43 I/O devices 50 2,3 BB Assignment
Direct memory access.
44 50 1,2 BB Brain storming
Direct memory access.
45 50 1,2 BB Brain storming

• BB-Black Board
• PPT-Power Point

Signature of Staff Signature of H.O.D