VHDL

Behavioral Modeling
 VHDL Design Styles
VHDL Design
Styles

dataflow structural behavioral

Sequential statements
Concurrent Components and
statements interconnects • Registers
• Shift registers
• Counters
synthesizable • State machines
 Behavioral Design/Modelling
• Functional performance is the goal of behavioral
• modeling Timing optionally included in the model
• Software engineering practices should be used to
develop behavioral models
• Sequential, inside a process
• Just like a sequential program
• The main character is ‘process(sensitivity list)’

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 Anatomy of a Process
• The process statement is a concurrent statement , which
delineates a part of an architecture where sequential statements
are executed.
• Syntax
[label:] process [(sensitivity list
)] declarations
begin
sequential statements
end process [label];
 PROCESS with a SENSITIVITY LIST
• List of signals to which
the process is sensitive.
• Whenever there is an event on
any of the signals in the
sensitivity list, the process fires.
• Every time the process fires, label: process (sensitivity lis
it will run in its entirety. declaration
• WAIT statements are NOT part begin
ALLOWED in a processes
with SENSITIVITY LIST. statement part
end process;
 Concurrent VS sequential
• Every statement inside the architecture body is
executed concurrently, except statements
enclosed by a process.
• Process
– Statements within a process are executed sequentially.
Result is known when the whole process is complete.
– You may treat a process as one concurrent statement in
the architecture body.
– Process(sensitivity list): when one or more signals in the
sensitivity list change state, the process executes once.
– Process should either have sensitivity list or an explicit
wait statement. Both should not be present in the
same process statement.

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 Process contd..
• The order of execution of statements is
the order in which the statements appear
in the process
• All the statements in the process are
executed continuously in a loop .
• The simulator runs a process when any
one of the signals in the sensitivity list
changes.
• For a wait statement, the simulator
executes the process after the wait is over.
 Example of Process with/without wait
process (clk,reset)
begin
if (reset = ‘1’) then
A <= ‘0’;
elsif (clk’event and clk = ‘1’)
then A <= ‘B’;
end if;
end process;
process
begin
if (reset = ‘1’) then
A <= ‘0’ ;
elsif (clk’event and clk = ‘1’) then
A <= ‘B’;
end if;
wait on reset,
clk; end process;
 Let’s Write a VHDL Model of Full
Adder using Behavioral Modeling

A ENTITY full_adder IS
PORT ( A, B, Cin : IN BIT;
Sum Sum, Cout : OUT BIT
);
B END full_adder;

Cout
Cin
 Full Adder Architecture
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1 for Cout (I.e. Carry Out):
Cin (I.e. Carry In)
AB 0 1
00 0 0
01 0 1
11 1 1
10 0 1
for Sum:
Cin (I.e. Carry In):
AB 0 1
00 0 1
01 1 0
11 0 1
10 1 0
 Two Full Adder Processes
Summation:
PROCESS( A, B, Cin)
BEGIN
Sum <= A XOR B XOR Cin;
END PROCESS Summation;

A
Sum
B
Cout
Cin
Carry:
PROCESS( A, B, Cin)
BEGIN
Cout <= (A AND B) OR
(A AND Cin) OR
(B AND Cin);
END PROCESS Carry;
 Complete Architecture
ARCHITECTURE example OF full_adder IS
-- Nothing needed in declarative block...
BEGIN

Summation: PROCESS( A, B, Cin)

BEGIN
Sum <= A XOR B XOR Cin;
END PROCESS Summation;

Carry: PROCESS( A, B, Cin)

BEGIN
Cout <= (A AND B) OR
(A AND Cin) OR
(B AND Cin);
END PROCESS Carry;

END example;
 VHDL Sequential Statements
• Assignments executed sequentially in processes
• Sequential statements
– {Signal, variable} assignments
– Flow control
• IF <condition> THEN <statements> [ELSIF <statements]
[ELSE <statements>] END IF;
• FOR <range> LOOP <statements> END LOOP;
• WHILE <condition> LOOP <statements> END LOOP;
• CASE <condition> IS WHEN <value> => <statements>
{WHEN <value> => <statements>}
[WHEN others => <statements>]
END CASE;
– WAIT [ON <signal>] [UNTIL <expression>] [FOR <time>] ;
– ASSERT <condition> [REPORT <string>] [SEVERITY <level>] ;
The if statement

• Syntax
if condition1 then
statements
[elsif condition2 then Priority
statements]

[else
statements]
end if;
• An if statement selects one or none of a sequence of
events to execute . The choice depends on one or more
conditions.
The if statement contd.
if (sel = “00”)
if sel = ‘1’ then then o <= a;
c <= a;
elsif sel = “01”
else then x <= b;
c <= b;
elsif (color = red)
end if; then y <= c;
else
o <= d;
end if;

• If statements can be nested.

• If statement generates a priority structure
• If corresponds to when else concurrent statement.
Alternate Carry Process

Carry: PROCESS( A, B, Cin)

BEGIN
IF ( A = ‘1’ AND B = ‘1’ )
THEN Cout <= ‘1’;
ELSIF ( A = ‘1’ AND Cin = ‘1’ )
THEN Cout < = ‘1’;
ELSIF ( B = ‘1’ AND Cin = ‘1’ ) THEN
Cout <= ‘1’;
ELSE
Cout <= ‘0’;
END IF;
END PROCESS Carry;
Priority Encoder

clk y
priority: PROCESS (clk) w
BEGIN a priorit
IF w(3) = '1' THEN y z
y <= "11" ; b
ELSIF w(2) = '1' c
THEN y <= "10" ;
ELSIF w(1) = c THEN • All signals which appear on the left
y <= a and b; of signal assignment statement (<=)
ELSE are outputs e.g. y, z
z <= "00" ; • All signals which appear on the right
END IF ; of signal assignment statement (<=) or
END PROCESS ; in logic expressions are inputs e.g. w,
a, b, c
• All signals which appear in the
sensitivity list are inputs e.g. clk
• Note that not all inputs need to
be included in the sensitivity list
BEHAVIORAL ( Processes using signals)

Sig1 = 2 + 3 = 5
Sig2 = 1
Sig3 = 2

Sum = 1 + 2 + 3 = 6
BEHAVIORAL ( Processes using Variables)

var1 = 2 + 3 = 5
var2 = 5
var3 = 5
Sum = 5 + 5 + 5 = 15