CAT522

Configured Digitally Programmable Potentiometer (DPP™):

Programmable Voltage Applications

FEATURES DESCRIPTION
„ Two 8-bit DPPs configured as programmable The CAT522 is a dual, 8-bit digitally-programmable
voltage sources in DAC-like applications potentiometer (DPP™) configured for programmable
„ Independent reference inputs voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
„ Non-volatile NVRAM memory wiper storage
machines and cellular telephones on automated high
„ Output voltage range includes both supply rails volume production lines, it is also well suited for self-
„ 2 independently addressable buffered calibrating systems and for applications where
output wipers equipment which requires periodic adjustment is either
„ 1 LSB accuracy, high resolution difficult to access or in a hazardous environment.
„ Serial Microwire-like interface
The CAT522 offers two independently programmable
„ Single supply operation: 2.7V - 5.5V DPPs each having its own reference inputs and each
„ Setting read-back without effecting outputs capable of rail to rail output swing. The wipers are
buffered by rail to rail opamps. Wiper settings, stored
in non-volatile NVRAM memory, are not lost when the
For Ordering Information details, see page 14. device is powered down and are automatically
reinstated when power is returned. Each wiper can
be dithered to test new output values without effecting
the stored settings and stored settings can be read
APPLICATIONS back without disturbing the DPP's output.
„ Automated product calibration.
The CAT522 is controlled with a simple 3-wire,
„ Remote control adjustment of equipment microwire-like serial interface. A Chip Select pin
„ Offset, gain and zero adjustments in self- allows several devices to share a common serial
calibrating and adaptive control systems. interface. Communication back to the host controller is
„ Tamper-proof calibrations. via a single serial data line thanks to the CAT522 Tri-
Stated Data Output pin. A RDY/BSY ¯¯¯¯ output working
„ DAC (with memory) substitute.
in concert with an internal low voltage detector signals
proper operation of the non-volatile NVRAM memory
Erase/Write cycle.

PIN CONFIGURATION The CAT522 is available in the 0°C to 70°C

PDIP 14-Lead (L) commercial and -40°C to 85°C industrial operating
SOIC 14-Lead (W) temperature ranges. Both 14-pin plastic DIP and
surface mount packages are available.
VDD 1 14 VREFH1
CLK 2 13 VREFH1

RDY/¯¯¯¯
BSY 3 12 VOUT1
CS 4 CAT522 11 VOUT2
DI 5 10 VREFL2
DO 6 8 VREFL1
PROG 7 8 GND

© Catalyst Semiconductor, Inc. 1 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

FUNCTIONAL DIAGRAM
VDD VREFH1 VREFH2

1 14 13

3
RDY/BSY

WIPER CONTROL REGISTERS

PROG 7 PROGRAM
CONTROL
24kΩ +
11

AND NVRAM
VOUT2
–
5
DI

2 SERIAL
CLK
CONTROL
24kΩ +
4 12
CS VOUT1
–

SERIAL
DATA 6
DO
OUTPUT
REGISTER
CAT522
8 9 10

GND VREFL1 VREFL2

Doc. No. MD-2004 Rev. G 2 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
 CAT522

ABSOLUTE MAXIMUM RATINGS (1)

Parameters Ratings Units Parameters Ratings Units
Supply Voltage Outputs
V -0.5 to VDD +0.5 V
VDD to GND -0.5 to +7 D0 to GND
Inputs VOUT 1– 4 to GND -0.5 to VDD +0.5 V
CLK to GND -0.5 to VDD +0.5 V Operating Ambient Temperature
CS to GND -0.5 to VDD +0.5 V Commercial
0 to +70 °C
DI to GND -0.5 to VDD +0.5 V (‘C’ or Blank suffix)
¯¯¯¯ to GND
RDY/BSY -0.5 to VDD +0.5 V Industrial (‘I’ suffix) -40 to +85 °C
PROG to GND -0.5 to VDD +0.5 V Junction Temperature +150 °C
VREFH to GND -0.5 to VDD +0.5 V Storage Temperature -65 to +150 °C
VREFL to GND -0.5 to VDD +0.5 V Lead Soldering (10s max) +300 °C

RELIABILITY CHARACTERISTICS
Symbol Parameter Test Method Min Max Units
VZAP(2) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V
ILTH(2) (3) Latch-Up JEDEC Standard 17 100 mA

POWER SUPPLY
Symbol Parameter Conditions Min Typ Max Units
IDD1 Supply Current (Read) Normal Operating — 400 600 µA
IDD2 Supply Current (Write) Programming, VDD = 5V — 1600 2500 µA
VDD = 3V — 1000 1600 µA
VDD Operating Voltage Range 2.7 — 5.5 V

LOGIC INPUTS
Symbol Parameter Conditions Min Typ Max Units
IIH Input Leakage Current VIN = VDD — — 10 µA
IIL Input Leakage Current VIN = 0V — — -10 µA
VIH High Level Input Voltage 2 — VDD V
VIL Low Level Input Voltage 0 — 0.8 V

LOGIC OUTPUTS
Symbol Parameter Conditions Min Typ Max Units
VOH High Level Output Voltage IOH = -40µA VDD -0.3 — — V
VIL Low Level Output Voltage IOL = 1mA, VDD = +5V — — 0.4 V
IOL = 0.4mA, VDD = +3V — — 0.4 V

Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.

© Catalyst Semiconductor, Inc. 3 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

RPOT Potentiometer Resistance 24 kΩ
RPOT to RPOT Match — ±0.5 ±1 %
Pot Resistance Tolerance ±20 %
Voltage on VREFH pin 2.7 VDD V
Voltage on VREFL pin 0 VDD - 2.7 V
Resolution 0.4 %
INL Integral Linearity Error 0.5 1 LSB
DNL Differential Linearity Error 0.25 0.5 LSB
ROUT Buffer Output Resistance 10 Ω
IOUT Buffer Output Current 3 mA
TCRPOT TC of Pot Resistance 300 ppm/ºC
CH/CL Potentiometer Capacitances 8/8 pF

AC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

Digital
tCSMIN Minimum CS Low Time 150 — — ns
tCSS CS Setup Time 100 — — ns
tCSH CS Hold Time 0 — — ns
tDIS DI Setup Time 50 — — ns
(1)
tDIH DI Hold Time CL = 100pF 50 — — ns
tDO1 Output Delay to 1 — — 150 ns
tDO0 Output Delay to 0 — — 150 ns
tHZ Output Delay to High-Z — 400 — ns
tLZ Output Delay to Low-Z — 400 — ns
tBUSY Erase/Write Cycle Time — 4 5 ms
tPS PROG Setup Time 150 — — ns
tPROG Minimum Pulse Width 700 — — ns
tCLKH Minimum CLK High Time 500 — — ns
tCLKL Minimum CLK Low Time 300 — — ns
fC Clock Frequency DC — 1 MHz
Analog
tDS DPP Settling Time to 1 LSB CLOAD = 10pF, VDD = +5V — 3 10 µs
CLOAD = 10pF, VDD = +3V — 6 10 µs

Notes:
(1) All timing measurements are defined at the point of signal crossing VDD / 2.
(2) These parameters are periodically sampled and are not 100% tested.

Doc. No. MD-2004 Rev. G 4 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
 CAT522

A.C. TIMING DIAGRAM

to 1 2 3 4 5

tCLK H

CLK

tCSS tCLK L t CSH

CS

tCSMIN

tDIS

DI

tDIH

t DO0
tLZ
DO

tHZ
tDO1

PROG
t PS

tPROG
RDY/BSY

tBUSY

to 1 2 3 4 5

© Catalyst Semiconductor, Inc. 5 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

PIN DESCRIPTION
Pin Name Function DPP addressing is as follows:
1 VDD Power supply positive
DPP OUTPUT A0 A1
2 CLK Clock input pin
¯¯¯¯ VOUT1 0 1
3 RDY/BSY Ready/Busy output
VOUT2 1 1
4 CS Chip select
5 DI Serial data input pin
6 DO Serial data output pin
EEPROM Programming Enable
7 PROG
Input
8 GND Power supply ground
9 VREFL1 Minimum DPP1 output voltage
10 VREFL2 Minimum DPP2 output voltage
11 VOUT2 DPP2 output
12 VOUT1 DPP1 output
13 VREFH2 Maximum DPP2 output voltage
14 VREFH1 Maximum DPP1 output voltage

DEVICE OPERATION
The CAT522 is a dual 8-bit configured digitally because the DO pin is Tri-Stated and returns to a high
programmable potentiometer (DPP) whose outputs impedance when not in use.
can be programmed to any one of 256 individual
voltage steps. Once programmed, these output CHIP SELECT
settings are retained in non-volatile memory and will Chip Select (CS) enables and disables the CAT522’s
not be lost when power is removed from the chip. read and write operations. When CS is high data may
Upon power up the DPPs return to the settings stored be read to or from the chip, and the Data Output (DO)
in non-volatile memory. Each DPP can be written to pin is active. Data loaded into the DPP control regis–
and read from independently without effecting the ters will remain in effect until CS goes low. Bringing
output voltage during the read or write cycle. Each CS to a logic low returns all DPP outputs to the
output can also be adjusted without altering the settings stored in non-volatile memory and switches
stored output setting, which is useful for testing new DO to its high impedance Tri-State mode.
output settings before storing them in memory.
Because CS functions like a reset the CS pin has
DIGITAL INTERFACE been desensitized with a 30 ns to 90 ns filter circuit to
The CAT522 employs a 3 wire serial, Microwire-like prevent noise spikes from causing unwanted resets
control interface consisting of Clock (CLK), Chip and the loss of volatile data.
Select (CS) and Data In (DI) inputs. For all
operations, address and data are shifted in LSB first. CLOCK
In addition, all digital data must be preceded by a logic The CAT522’s clock controls both data flow in and out
“1” as a start bit. The DPP address and data are of the IC and non-volatile memory cell programming.
clocked into the DI pin on the clock’s rising edge. Serial data is shifted into the DI pin and out of the DO
When sending multiple blocks of information a pin on the clock’s rising edge. While it is not neces–
minimum of two clock cycles is required between the sary for the clock to be running between data
last block sent and the next start bit. transfers, the clock must be operating in order to write
to non-volatile memory, even though the data being
Multiple devices may share a common input data line saved may already be resident in the DPP wiper
by selectively activating the CS control of the desired control register.
IC. Data Outputs (DO) can also share a common line

Doc. No. MD-2004 Rev. G 6 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
 CAT522

No clock is necessary upon system power-up. The ¯¯¯¯ will remain high following the program
RDY/BSY
CAT522’s internal power-on reset circuitry loads data command indicating a failure to record the desired
from non-volatile memory to the DPPs without using data in non-volatile memory.
the external clock.
DATA OUTPUT
As data transfers are edge triggered clean clock Data is output serially by the CAT522, LSB first, via
transitions are necessary to avoid falsely clocking the Data Out (DO) pin following the reception of a
data into the control registers. Standard CMOS and start bit and two address bits by the Data Input (DI).
TTL logic families work well in this regard and it is DO becomes active whenever CS goes high and
recommended that any mechanical switches used for resumes its high impedance Tri-State mode when CS
breadboarding or device evaluation purposes be returns low. Tri-Stating the DO pin allows several
debounced by a flip-flop or other suitable debouncing 522s to share a single serial data line and simplifies
circuit. interfacing multiple 522s to a microprocessor.

VREF WRITING TO MEMORY

VREF, the voltage applied between pins VREFH & VREFL, Programming the CAT522’s non-volatile memory is
sets the DPP’s Zero to Full Scale output range where accomplished through the control signals: Chip Select
VREFL = Zero and VREFH = Full Scale. VREF can span (CS) and Program (PROG). With CS high, a start bit
the full power supply range or just a fraction of it. In followed by a two bit DPP address and eight data bits
typical applications VREFH & VREFL are connected are clocked into the DPP wiper control register via the
across the power supply rails. When using less than DI pin. Data enters on the clock’s rising edge. The
the full supply voltage be mindfull of the limits placed DPP output changes to its new setting on the clock
on VREFH and VREFL as specified in the References cycle following D7, the last data bit.
section of DC Electrical Characteristics.
Programming is accomplished by bringing PROG high
¯¯¯¯¯
READY/BUSY sometime after the start bit and at least 150 ns prior to
When saving data to non-volatile memory, the the rising edge of the clock cycle immediately following
Ready/Busy ouput (RDY/BSY ¯¯¯¯) signals the start and the D7 bit. Two clock cycles after the D7 bit the DPP
duration of the erase/write cycle. Upon receiving a wiper control register will be ready to receive the next
command to store data (PROG goes high) RDY/BSY ¯¯¯¯ set of address and data bits. The clock must be kept
goes low and remains low until the programming cycle is running throughout the programming cycle. Internal
complete. During this time the CAT521 will ignore any control circuitry takes care of generating and ramping
data appearing at DI and no data will be output on DO. up the programming voltage for data transfer to the
non-volatile cells. The CAT522’s non-volatile memory
¯¯¯¯ is internally ANDed with a low voltage
RDY/BSY cells will endure over 1,000,000 write cycles and will
detector circuit monitoring VDD. If VDD is below the retain data for a minimum of 100 years without being
minimum value required for non-volatile programming, refreshed.

Figure 1. Writing to Memory

to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CS
NEW DPP DATA

DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7

CURRENT DPP DATA

DO D0 D1 D2 D3 D4 D5 D6 D7

PROG

RDY/BSY

DPP CURRENT NEW NEW

OUTPUT DPP VALUE DPP VALUE DPP VALUE
NON-VOL ATILE VOLATILE NON-VOL ATILE

© Catalyst Semiconductor, Inc. 7 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

READING DATA TEMPORARILY CHANGE OUTPUT

Each time data is transferred into a DPP control The CAT522 allows temporary changes in DPP’s
register currently held data is shifted out via the D0 output to be made without disturbing the settings
pin, thus in every data transaction a read cycle retained in non-volatile memory. This feature is parti–
occurs. Note, however, that the reading process is cularly useful when testing for a new output setting
destructive. Data must be removed from the register and allows for user adjustment of preset or default
in order to be read. Figure 2 depicts a Read Only values without losing the original factory settings.
cycle in which no change occurs in the DPP’s output.
This feature allows µPs to poll DPPs for their current Figure 3 shows the control and data signals needed
setting without disturbing the output voltage but it to effect a temporary output change. DPP wiper
assumes that the setting being read is also stored in settings may be changed as many times as required
non-volatile memory so that it can be restored at the and can be made to any of the two DPPs in any order
end of the read cycle. In Figure 2 CS returns low or sequence. The temporary setting(s) remain in
before the 13th clock cycle completes. In doing so the effect long as CS remains high. When CS returns low
non-volatile memory setting is reloaded into the DPP all two DPPs will return to the output values stored in
wiper control register. Since this value is the same as non-volatile memory.
that which had been there previously no change in the
DPP’s output is noticed. Had the value held in the When it is desired to save a new setting acquired
control register been different from that stored in non- using this feature, the new value must be reloaded
volatile memory then a change would occur at the into the DPP wiper control register prior to
read cycle’s conclusion. programming. This is because the CAT522’s internal
control circuitry discards from the programming
register the new data two clock cycles after receiving
it if no PROG signal is received.

Figure 2. Reading from Memory Figure 3. Temporary Change in Output

to 1 2 3 4 5 6 7 8 9 10 11 12 to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2

CS CS

NEW DPP DATA

DI 1 A0 A1
1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
DI
CURRENT DPP DATA
CURRENT DPP DATA
DO D0 D1 D2 D3 D4 D5 D6 D7

DO D0 D1 D2 D3 D4 D5 D6 D7

PROG
PROG

RDY/BSY
RDY/BSY

DPP CURRENT
OUTPUT DPP VALUE
DPP CURRENT NEW CURRENT
NON-VOL ATILE OUTPUT DPP VALUE DPP VALUE DPP VALUE
NON-VOL ATILE VOLATILE NON-VOL ATILE

Doc. No. MD-2004 Rev. G 8 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
 CAT522

APPLICATION CIRCUITS
+5V DPP INPUT DPP OUTPUT ANALOG OUTPUT
VI RI RF
CODE
VDPP = x (VFS - VZERO) + VZERO
255
+15V VFS = 0.99VREF VREF = 5V
MSB LSB
VDD VREFH – VOUT VZERO = 0.01VREF RI = RF

CONTROL VDPP + 255

× 0.98VREF + 0.01VREF = 0.990 VREF VOUT = +4.90V
& DATA CAT522 OP 07
1111 1111 255
128
1000 0000 × 0.98VREF + 0.01VREF = 0.502VREF VOUT = +0.02V
GND VREFL -15V 255
127
0111 1111 × 0.98VREF + 0.01VREF = 0.498 VREF VOUT = -0 .02V
VDPP ( RI + RF ) - VI R F 255
VOUT = 1
× 0.98VREF + 0.01VREF = 0.014 VREF VOUT = -4.86V
RI 0000 0001 255
For R I = RF 0
0000 0000 × 0.98VREF + 0.01VREF = 0.010 VREF VOUT = -4.90V
VOUT = 2VDPP - VI 255

Bipolar DPP Output

V+

+5V I > 2mA

RI RF

+15V
VDD VREFH – VREF = 5.00V
VOUT
VDD VREFH
CONTROL CAT522 +
& DATA OP 07
CONTROL CAT522 LT 1029
& DATA
GND VREFL -15V
GND VREFL
R
VOUT = (1 + F ) VDPP
RI

Amplified DPP Output Digitally Trimmed Voltage Reference

28 - 32V

15kΩ 10µF

1N5231B 10kΩ

VDD VREFH 5.1V

CONTROL CAT522
& DATA +
MPT3055EL
GND VREFL – LM 324

OUTPUT
4.02kΩ 10µF 0 - 25V
1.00kΩ
35V @ 1A

Digitally Controlled Voltage Reference

© Catalyst Semiconductor, Inc. 9 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

+5V VREF +5V +VREF

VDD VREFH VDD VREFH

127RC 127RC
FINE ADJUST FINE ADJUST
DPP DPP
(+VREF) - (VOFFSET+)
RC =
CAT522 CAT522 1µA

RC +V RC (-VREF) + (VOFFSET+)
VOFFSET R0 =
COARSE ADJUST COARSE ADJUST 1µA
DPP
+
DPP
–
GND VREFL GND VREFL
R0 +V
VOFFSET
+
VREF -VREF
RC = –
256 x 1µA

Fine adjust gives ±1 LSB change in VOFFSET -V

when VOFFSET = VREF/2

Coarse-Fine Offset Control by Averaging DPP Coarse-Fine Offset Control by Averaging DPP
Outputs for Single Power Supply Systems Outputs for Dual Power Supply Systems
+5V
2.2kΩ

4.7µF
VDD VREFH LM385-2.5
ISINK = 2 - 255mA

+15V

DPP1 + 1mA steps

2N7000
–
+5V

10kΩ 10kΩ 39Ω 1W

CONTROL CAT522
& DATA

39Ω 1W

DPP2 + 5µA steps

2N7000
–

GND VREFL
5MΩ 5MΩ 3.9kΩ

10kΩ 10kΩ

–
TIP30
+

-15V
Current Sink with 4 Decades of Resolution

Doc. No. MD-2004 Rev. G 10 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
 CAT522

+15V
51kΩ

+
TIP29
–

10kΩ 10kΩ
+5V

VDD VREFH

5MΩ 5MΩ 39Ω 1W

DPP1

39Ω 1W

–
CONTROL CAT522 BS170P
& DATA + 1mA steps

5MΩ 5MΩ 3.9kΩ

DPP2

–
GND VREFL
BS170P
+ 5µA steps

LM385-2.5

-15V ISOURCE = 2 ÷ 255mA

Current Source with 4 Decades of Resolution

© Catalyst Semiconductor, Inc. 11 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

PACKAGE OUTLINE DRAWING

PDIP 14-LEAD (L) (1)(2)

SYMBOL MIN NOM MAX

A 3.56 5.33
A1 0.38
A2 2.92 3.30 4.95
E1 b 0.36 0.45 0.55
b1 1.15 1.52 1.77
c 0.21 0.26 0.35
D 18.67 19.05 19.68
E 7.62 7.87 8.25
E1 6.10 6.35 7.11
D
e 2.54 BSC
eB 7.88 10.92
TOP VIEW
L 2.99 3.30 3.81

A2
A

A1 L

e b1 b eB

SIDE VIEW END VIEW

For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-001.

Doc. No. MD-2004 Rev. G 12 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
 CAT522

SOIC 14-LEAD (W) (1)(2)

SYMBOL MIN NOM MAX

A 1.35 1.75
A1 0.10 0.25
b 0.33 0.51
c 0.19 0.25
D 8.55 8.65 8.75
E1 E
E 5.80 6.00 6.20
E1 3.80 3.90 4.00
e 1.27 BSC
h 0.25 0.50
L 0.40 1.27
θ 0º 8º
PIN#1 IDENTIFICATION

TOP VIEW

D h

θ
A

c
e b L
A1

SIDE VIEW END VIEW

For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.

Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.

© Catalyst Semiconductor, Inc. 13 Doc. No. MD-2004 Rev. G

Characteristics subject to change without notice
CAT522

EXAMPLE OF ORDERING INFORMATION (1)

Prefix Device # Suffix

CAT 522 W I – T2

Optional Temperature Range Tape & Reel

Company ID I = Industrial (-40ºC to 85ºC) T: Tape & Reel
2: 2000/Reel
Product Package
Number L: PDIP
522 W: SOIC

ORDERING PART NUMBER

CAT522LI
CAT522WI

Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is Matte-Tin.
(3) The device used in the above example is a CAT522WI-T2 (SOIC, Industrial Temperature, Tape & Reel, 2000).

Doc. No. MD-2004 Rev. G 14 © Catalyst Semiconductor, Inc.

Characteristics subject to change without notice
REVISION HISTORY
Date Rev. Reason
3/16/2004 D Updated Potentiometer Characteristics
Updated Functional Diagram
7/12/2004 E
Updated Potentiometer Characteristics
Add Package Outline Drawings
Update Example of Ordering Information
07/26/2007 F
Updated Ordering Information
Added MD- to document number
10/31/2007 G Update Example of Ordering Information

Copyrights, Trademarks and Patents

© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000 Document No: MD-2004
Fax: 408.542.1200 Revision: G
www.catsemi.com Issue date: 10/31/07