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VHDL Code For 1 To 4 Demux

The document describes a 1 to 4 demultiplexer (demux) circuit. It includes the truth table and logic gate design for a 1 to 4 demux, as well as VHDL code and a testbench to implement the demux. The VHDL code uses a process with an if statement to output the input signal to one of the four output ports, depending on the values of the two selection lines. The testbench applies stimulus and verifies the output waveforms match the expected demux behavior.

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Sri Vidya
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3K views

VHDL Code For 1 To 4 Demux

The document describes a 1 to 4 demultiplexer (demux) circuit. It includes the truth table and logic gate design for a 1 to 4 demux, as well as VHDL code and a testbench to implement the demux. The VHDL code uses a process with an if statement to output the input signal to one of the four output ports, depending on the values of the two selection lines. The testbench applies stimulus and verifies the output waveforms match the expected demux behavior.

Uploaded by

Sri Vidya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL code for 1 to 4 Demux | 1

Contents

1 DeMultiplexer
2 1 to 4 Demux
3 Truth table for Demux 1 to 4
4 1 to 4 Demux design using Logic Gates
5 VHDL Code for 1 to 4 Demux
6 VHDL Testbench Code for 1 to 4 Demux
7 Testbench waveform for 1 to 4 Demux

DeMultiplexer

Demultiplexer (DEMUX) select one output from the multiple output line and fetch the single
input through selection line. It consist of 1 input and 2 power n output. The output data
lines are controlled by n selection lines. For Example, if n = 2 then the demux will be of 1 to
4 mux with 1 input, 2 selection line and 4 output as shown below. Also VHDL Code for 1 to 4
Demux described below.

1 to 4 Demux

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VHDL code for 1 to 4 Demux | 2

Truth table for Demux 1 to 4

1 to 4 Demux design using Logic Gates

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VHDL code for 1 to 4 Demux | 3

VHDL Code for 1 to 4 Demux

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity demux_1to4 is
port(

F : in STD_LOGIC;
S0,S1: in STD_LOGIC;

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VHDL code for 1 to 4 Demux | 4

A,B,C,D: out STD_LOGIC


);
end demux_1to4;

architecture bhv of demux_1to4 is


begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
elsif (S0 ='1' and S1 = '0') then
B <= F;
elsif (S0 ='0' and S1 = '1') then
C <= F;
else
D <= F;
end if;

end process;
end bhv;

VHDL Testbench Code for 1 to 4 Demux

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_demux IS
END tb_demux;

ARCHITECTURE behavior OF tb_demux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT demux_1to4
PORT(
F : IN std_logic;

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VHDL code for 1 to 4 Demux | 5

S0 : IN std_logic;
S1 : IN std_logic;
A : OUT std_logic;
B : OUT std_logic;
C : OUT std_logic;
D : OUT std_logic
);
END COMPONENT;

--Inputs
signal F : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';

--Outputs
signal A : std_logic;
signal B : std_logic;
signal C : std_logic;
signal D : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)


uut: demux_1to4 PORT MAP (
F => F,
S0 => S0,
S1 => S1,
A => A,
B => B,
C => C,
D => D
);

-- Stimulus process
stim_proc: process
begin

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VHDL code for 1 to 4 Demux | 6

-- hold reset state for 100 ns.


wait for 100 ns;

F <= '1';

S0 <= '0'; S1 <= '0';

wait for 100 ns;

S0 <= '1'; S1 <= '0';

wait for 100 ns;

S0 <= '0'; S1 <= '1';

wait for 100 ns;

S0 <= '1'; S1 <= '1';

wait for 100 ns;


-- insert stimulus here

wait;
end process;

END;

Testbench waveform for 1 to 4 Demux

The above waveform represent the result of VHDL Code for 1 to 4 Demux.

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