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D FlipFlop

Flip-flops are common in synchronous circuits and use a clock signal to time various elements. Setup time defines the period the data input must be stable before the clock samples it, while hold time is how long it must remain stable after. Propagation delay is the time it takes for the sampled data to appear at the output. Together, setup, hold and propagation delay define the timing requirements for valid data transfer through a flip-flop.

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0% found this document useful (0 votes)
196 views

D FlipFlop

Flip-flops are common in synchronous circuits and use a clock signal to time various elements. Setup time defines the period the data input must be stable before the clock samples it, while hold time is how long it must remain stable after. Propagation delay is the time it takes for the sampled data to appear at the output. Together, setup, hold and propagation delay define the timing requirements for valid data transfer through a flip-flop.

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nandams
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Definition of Set-up, Hold and Propagation in Flip-Flops

Figure 1 shows a basic diagram of a D Flip-Flop. Flip-Flops are very common elements
in synchronous designs where clock signal provides the timing to various elements and
clock domains.

SET
Data D Q Q
Clk

CLR
Q

Figure 1: D Flip-Flop

Setup time and hold time describe the timing requirements on the D input of a
Flip-Flop with respect to the Clk input. Setup and hold time define a window of
time which the D input must be valid and stable in order to assure valid data on
the Q output.

Setup Time (Tsu) – Setup time is the time that the D input must be valid before
the Flip-Flop samples.

Hold Time (Th) – Hold time is the time that D input must be maintained valid
after the Flip-Flop samples.

Propagation Delay (Tpd) – Propagation delay is the time that takes to the
sampled D input to propagate to the Q output.

t setup t hold

Data

Clk

Figure 2: Timing Diagram

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