Data Bus Size
Data Bus Size
address bus
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An internal channel from the CPU to memory across which the addresses of data (not the data)
are transmitted. The number of lines (wires) in the address bus determines the amount of
memory that can be directly addressed as each line carries one bit of the address. For example, a
20-line address bus represents the binary number 1,048,576 and reaches that number of memory
bytes (the size of the address bus in the IBM PC in 1981). A computer with a 32-bit address bus
can directly address 4GB of physical memory, while one with 36 bits can address 64GB.
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Wikipedia:
Address bus
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challenged and removed. (June 2009)
An address bus is a computer bus (a series of lines connecting two or more devices) that is used
to specify a physical address. When a processor or DMA-enabled device needs to read or write
to a memory location, it specifies that memory location on the address bus (the value to be read
or written is sent on the data bus). The width of the address bus determines the amount of
memory a system can address. For example, a system with a 32-bit address bus can address 232
(4,294,967,296) memory locations. If each memory address holds one byte, the addressable
memory space is 4 GB.
Implementation
Early processors used a wire for each bit of the address width. For example, a 16-bit address bus
had 16 physical wires making up the bus. As the buses became wider, this approach became
expensive in terms of the number of chip pins and board traces. Beginning with the Mostek 4096
DRAM, multiplexed addressing became common. In a multiplexed address scheme, the address
is sent in two equal parts. This halves the number of address bus signals required to connect to
the memory. For example a 32-bit address bus can be implemented by using 16 wires and
sending the first half of the memory address, immediately followed by the second half.
Interesting examples
Accessing an individual byte frequently requires reading or writing the full bus width (a word) at
once. In these instances the least significant bits of the address bus may not even be implemented
- it is instead the responsibility of the controlling device to isolate the individual byte required
from the complete word transmitted. This is the case, for instance, with the VESA Local Bus
which lacks the two least significant bits, limiting this bus to aligned 32-bit transfers.
Historically, there were also some examples of computers which were only able to address
words.
In 16bit microprocessor what are the size of data bus and address bus?
In: Computer Hardware, Intel 8085, Intel 8086 and 8088 [Edit categories]
A 16-bit uP operates on instructions and data in 16-bit quantities. Therefore the databus is 16-
bits. A 16-bit uP may also operate on larger quantities of data, however multiple CPU registers
must be concatenated in order to maintain the data element in the uP register space. The data is
always delivered to the processor 16 bits at a time.
The amount of memory which it can address is a separate issue---the address bus size is totally
distinct from the data bus size. The data bus determines how much memory may be delivered
to the uP per cycle. The address bus size determines how much physical memory may actually
be accessed by the uP. Therefore it is variable depending on how much memory is available.
Typical systems today have 32-bit address busses which limit addressable memory to
4Gigabytes. (2^32) = 4G.