MURDOCH RESEARCH REPOSITORY

This is the author’s final version of the work, as accepted for publication
following peer review but without the publisher’s layout or pagination.
The definitive version is available at :

http://dx.doi.org/10.1109/AUPEC.2014.6966533

Barbieri, F., Chandrasena, R.P.S., Shahnia, F., Rajakaruna, S. and Ghosh,

A. (2014) Application notes and recommendations on using TMS320F28335
digital Signal Processor to control voltage source converters. In: Australasian
Universities Power Engineering Conference (AUPEC) 2014, 28 Sept. - 1 Oct.
2014, Perth, W.A

http://researchrepository.murdoch.edu.a/32585/

Copyright: © 2014 IEEE

It is posted here for your personal use. No further distribution is permitted.
Copyright © 2014 IEEE. Personal use of this material is permitted.
Permission from IEEE must be obtained for all other uses, in any
current or future media, including reprinting/republishing this
material for advertising or promotional purposes, creating new
collective works, for resale or redistribution to servers or lists, or
reuse of any copyrighted component of this work in other works.
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 1

Application Notes and Recommendations on using

TMS320F28335 Digital Signal Processor to Control
Voltage Source Converters
Florian Barbieri, Ruwan P.S. Chandrasena, Farhad Shahnia, Sumedha Rajakaruna and Arindam Ghosh
Electrical and Computer Engineering Department
Curtin University
Perth, Australia
[email protected]

Abstract—This paper presents general recommendations on

utilizing TMS320F28335 Digital Signal Controller (DSC) as the
controller for Voltage Source Converters (VSC). First, a com-
parison is provided on different DSCs that can be used for such
applications and the reasons for selecting this specific Texas
Instrument device are discussed. Later, the strategy for real-
time algorithm developed in the DSC, also referred to as digital
Signal Processor (DSP) is explained and its main features that
Fig. 1. Schematic of a VSC: (a) Single-phase, (b) Three-phase.
are used for VSC control are described. Some new functions are
developed and their characteristics and specifications are sum- Output
marized. The paper also presents a discussion on the most prob- DC
Link VSC + Filter
able difficulties when programming the DSC/DSP for VSC con-
trol applications followed by some improvement methods pro-
posed for tackling these difficulties. Voltage and
Opto‐ coupler current
Index Terms—Digital Signal Processor (DSP), TMS320F28335, interface transducers
Voltage Source Converter (VSC).
I. INTRODUCTION DSP Board

Voltage Source Converters (VSC) are utilized in numerous

Signal
applications in electrical systems spanning across motor and conditioning
drive applications, energy harvesting from renewable energy
Fig. 2. Schematic of a VSC along with its closed-loop control system.
resources, power quality improvement purposes in the trans-
mission and distribution lines to HVDC systems [1]. The closed-loop control of a VSC, the desired voltage, current or
VSCs are composed of fully controlled semiconductor power parameters at the output of the VSC should be moni-
switches such as Insulated Gate Bipolar Transistors (IGBT) tored in real-time using proper sensors. The analogue outputs
or Metal Oxide Semiconductor Field Effect Transistors of the sensors should be first digitalized and then fed to the
(MOSFET) as their main building blocks. Each switch needs pre-designed controller. The controller should then define the
to have proper protection, driver and snubber circuits. Fig. 1 proper turning on and turning off times of the switches and
shows the schematics of a single-phase and three-phase VSC. should export that information as commands in digital format
It is to be noted that to prevent short-circuiting the DC link, to the driver circuits of the switches in the VSC through
the switches in each leg of the VSC must operate comple- proper electrical isolation (i.e. by using opto-couplers). Fig. 2
mentarily. shows a schematic diagram of a VSC along with its closed-
The turn on and turn off the switches in the VSC should be loop control system.
based on providing a desired voltage, current or power at the The performance of VSCs highly depends on their control-
output of the VSC. Therefore, the switchings in the VSC lers. This performance can significantly improve if digital
needs a pre-designed controller. For different objectives, the controllers are used. There are various options for implement-
VSC might have an open-loop or closed-loop control. Open- ing digital controls for VSCs. Microcontroller Units (MCU),
loop control systems are much easier to be developed and Digital Signal Controllers (DSC), Digital Signal Processors
hence are more popular. However, the closed-loop control (DSP) and Field Programmable Arrays (FPGA) are the most
systems provide a high improvement in the dynamic perfor- common options. DSCs can also be referred to as DSPs since
mance of VSCs. The closed-loop control systems can utilize their processor unit is a DSP. MCUs which their core is not a
different control strategies such as state-space, predictive, DSP, but a microprocessor, are not designed to operate in
adaptive, non-linear, robust and optimal controls [2-3]. For a real-time applications [4]. Although they can be used for con
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 2

Table 1.Comparison of different TI C2000 series, TMS320F28xxDSPs

DSP Frequency RAM Flash ADC DAC Price (US$) in
Type
Model (MHz) (kB) (kB) No. Resolution (bit) Speed (ns) No. 2014
377D 200 204 1024 4 12/16 286 3 18.18
376D 200 172 512 4 12/16 286 3 15.93
Floating
335 150 68 512 1 12 80 0 14.25
point
334 150 68 256 1 12 80 0 14.05
332 100 52 128 1 12 80 0 13.20
Fixed point 12 150 36 256 1 12 80 0 14.25

Trolling VSCs, they will not result in very fast dynamic per-
formances. FPGAs are slightly cheaper and can process data
faster than DSPs. However, they need a much lower pro-
gramming level compared to them. A comparison between
DSP and FPGA for VSCs is presented in [5] and concludes
that the FPGAs cost more than DSPs in terms of development
time while resulting in almost similar dynamic results by the
VSCs.
Nowadays, there are plenty of DSPs available in the mar-
ket from different manufacturers with various specifications.
Hence, the possible options should be carefully analyzed be-
fore choosing a DSP. Among various DSP manufacturers, in Fig. 3. (a) Packaged DSP, (b) TI DSP Experimenter’s Kit, (c) eZdspTM board,
(d) Schematic of the DSP docking station.
2006 it was reported that Texas Instruments® (TI) dominates
the market by 59% [4]. Table 1 summarizes some of the TI II. DSP KITS AND DEVELOPMENT SOFTWARE
processors in C2000 family, which are used for real-time ap-
TMS320F28335 DSP comes either in a packaged chip or
plications [6-7].It is to be noted that their ARM, C5000 and
on a control card. In either of the above cases, the DSP needs
C6000 series are also applicable for real-time applications but
to be mounted on a board. TI provides cheaper boards, re-
are more commonly used for control applications requiring
ferred to as Experimenter’s Kit [9] where the control cards
higher computations and data processing like multimedia or
can be mounted on. More professional and expensive boards
communication applications [4].
are also available for the packaged chips such as the Spec-
Depending on the application of the VSCs to be controlled,
trum Digital® eZdspTM board [10], which is one the most
the DSP should have a specific number of Analogue-to-
popular boards used for power electronic applications. Fig. 3
Digital Converters (ADC) and Digital-to-Analogue Conver-
shows the TMS320F28335 DSP package chip along with its
ters (DAC). In addition, depending on the number of calcula-
Experimenter’s Kit and eZdspTM board.
tions to be carried out by the controller, the DSP should have
In general, a DSP docking station can be represented with
a reasonable clock speed. It is to be noted that some DSPs
the main modules shown in Fig. 3(d). The signals applied to
have floating point support to provide high precision calcula-
the docking station are transmitted to and processed by the
tions, whereas fixed point DSPs have a lower precision [4].
DSP processor and then retrieved from it. Input signals are
Among the C2000 series of TI, TMS320F28335 DSC/DSP
applied on pins present on the docking station. These pins are
is a better trade-off between price, performance and features
internally connected to the General Purpose Input/Outputs
[6, 7]. Hence, this specific DSP is one of the most popular
(GPIO) of the DSP [6]. GPIOs can be set up by the user ei-
DSPs used to control the VSCs. Unlike FPGAs and like other
ther as inputs or outputs. TMS320F28335 has 88 GPIOs that
DSCs/DSPs, TMS320F28335 is a software based processor,
are connected to multiplexers. These multiplexers transmit
built on a modified Harvard architecture. In addition, it can
multiplexed signals to sample-and-hold registers where the
be programmed for real-time applications using C/C++ lan-
signals are held until the next conversion of the integrated
guage. It is to be noted that this DSP lacks DACs; however,
ADC. The ADC outputs are then transferred to the processor
this is not normally required in VSC applications. In case a
of the DSP through the result registers of the ADC. In order
digital signal inside the DSP needs to be exported out in ana-
to process the data, the code with which the DSP runs, can be
logue format, some auxiliary DAC chips are available to be
loaded from the Flash memory or from the Static Random
interconnected with the DSP. Alternatively, to export internal
Access Memory (SRAM). The flash memory is utilized in
data in digital format to an external display, the data can be
stand-alone applications of the DSP while SRAM is utilized
retrieved through a serial peripheral interface [8].
when the DSP is connected to its dedicated software on a
As a matter of comparison, the TMS320F2812 is also a
computer. The outputs of the program are then exported via
popular DSC/DSP of the TI C2000 series. However, as an
output GPIOs.
older fixed point unit model, its capability for numerical cal-
There are two possibilities to program the DSP. It can be
culations of floating point data is more limited than that of the
programmed in C/C++language using Code Composer Studio
floating point DSC/DSPs [4, 6-7]. Additionally, for the same
(CCS) which is a dedicated software, developed by the manu-
price of TMS320F28335, the TMS320F2812 offers slightly
facturer [11]. This process requires a good level of C lan-
less interesting hardware resources, as listed in Table 1.
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 3

guage knowledge as well as familiarity with the architecture

of the DSP (e.g. its ADCs, Timers and GPIOs). Alternatively,
the DSP can be programmed using MATLAB/SIMULINK®
toolboxes. For this process, three extra toolboxes of MAT-
LAB coder, SIMULINK coder and Embedded coder are re-
quired to be utilized. However, this method provides an op-
tion of utilizing majority of the built-in functions of MAT-
LAB and programming the DSP with minimum knowledge of
its architecture and the C language. Therefore, the latter is a
better solution for users without a sound knowledge of C.
CCS is a tool to create real-time C projects, load them on
the DSP. CCS also executes and debugs projects [12]. It con-
tains an editor, a compiler and a debugger. The editor is used
to compose the program, the compiler converts the C lan-
guage-based code into assembly language and then to load Fig. 4. Structure schematic of the real-time program in the DSP.
the generated assembly code into the DSP. Then, the debug-
ger is used to monitor the state of the parameters in the pro- ant values for indexing the arrays or by using constant values
gram during the execution period. The program can be ex- in calculations instead of variables the execution time of the
ecuted on stand-alone mode in the DSP; however, the DSP program can be reduced significantly. Furthermore, calling an
docking station should be connected to CCS in order to use external function slows down the execution and should be
the features of the debugger. It is to be noted that CCS cannot avoided within the ISR. This is highly important regarding
simulate any program and contains neither simulators nor executing short and simple codes. It is to be noted that using
models. CCS has a variety of built-in, structure-based, func- macro definitions is useful when structures or built-in func-
tions suitable for data/signal processing. However, all these tions are used within the program
functions may not be easy to be utilized nor optimized in Finally, it must be noted that the main function needs to
terms of execution times, when compared with the needed end with an infinite loop of type while(1);that does nothing
functionality. The best solution in such cases is to develop but waits indefinitely until an interruption happens. After an
custom functions. This can be very helpful when program- interruption, the program leaves the main function and jumps
ming DSPs for VSCs. It is also to be noted that some of the to the ISR function related to the interruption. After the ISR
built-in functions are specifically designed for fixed-point or is fully executed, the program goes back to the infinite loop
particular DSPs. Hence, when utilizing such built-in functions within the main function and resumes the infinite cycle until
proper modifications should be carried out to adapt them for the next interruption [9]. This structure is shown in Figure 4.
the TMS320F28335 DSPs. It is to be highlighted that all the real-time functionality of the
program is executed in the ISR of Timer0 and not in the main
III. REAL-TIME ALGORITHM IN THE DSP function. An example is provided at the end of Section IV to
For real-time application, the developed algorithm inside demonstrate the operation of the ISR.
the DSP is based on the principle of interruptions. IV. UTILIZED DSP PERIPHERALS
TMS320F28335 DSP includes a set of three timers. However,
only one timer, Timer0, can be utilized in the program. The The analogue data from the sensors output is fed into the
Interruption Service Request (ISR) of Timer0 is used as the DSP program through the GPIOs in the DSP [6]. When run-
main clock for the program. The ISR is a C function, inde- ning the program in the DSP, the GPIOs should be set up as
pendent of the main function in the DSP algorithm. It needs inputs or outputs by the help of an internal function. Then, the
to be declared and defined separately and is executed on the Analogue to Digital Converter (ADC) in the DSP is used to
basis of regular interruptions of Timer0. The periods of the retrieve data. It is to be noted that the sample-and-hold circuit
interruptions for Timer0 can be defined by the user for any passes the data from the GPIOs to the ADC at specific inter-
value greater than 1 µs. The period of interruptions is utilized vals (e.g. in 12.5 MHz) in a fast sequential mode, with con-
as the sampling period of the DSP program. As an example, version performed at every ADC interruption. It is to be noted
considering the maximum switching frequency of the IGBTs that the ADC has its own ISR. The period of interruptions
as 20 kHz, the sampling period of the DSP program must be depends on the ADC conversion frequency. Since the ADC
between 50 and 100 µs. conversion frequency is faster than the interruption frequency
In order to ensure the real-time operation of the program, of Timer0, the ADC interruptions have a higher priority than
the total execution time of the ISR must be shorter than the Timer0. It is important to make sure that the ADC ISR has
sampling period. Therefore, variable definition, array initiali- been executed at least once before starting the execution of
zations as well as any calculations that do not need any real Timer0 ISR. There are 16 ADC channels in TMS320F28335,
time input should be executed in the main function. Doing so which read input voltages in the range of 0 to 3 V. Its resolu-
helps to make the ISR very fast. Additionally, by using const- tion is 12 bits which can represent 4096 values. From this,
each step of an ADC channel is 0.732 mV. If a more accurate
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 4

ADC is required, an external ADC chip with higher resolu-

tion can be utilized.
Since the ADC cannot read any input voltage greater than Fig. 5. The sampled signal before and after the ADC and within the ISR.
3 V and does not support any negative voltages, the input
signal needs to be adjusted before being applied to the ADC. time, the local variable ‘TIME’ is used as the time variable in
This is done by adding an offset and then scaling the input the form of
signal in the range of 3 V. An operational amplifier-based for(TIME= 0;TIME< array_ size;TIME+ +)
circuit is used for this purpose. This data processing is shown Generated_ sine _ wave [TIME] = M.sin(2πf ×TIME×Ts )
as “Signal Processing” block in Fig. 2. Any offset or scaling
where M is the desired magnitude for the generated sine
carried out before the ADC should be converted back within
wave, f is its frequency and Ts is the sampling period of the
the program to represent the original input voltage. As an
DSP program. The math.h header requires to be included in
example, considering a sinusoidal voltage with a magnitude
the pre-processing section of the program. The size ar-
of 10 V at the output of the sensor, the signal fed to the ADC
ray_size is fixed according to f and Ts from
and the signal within the DSP program are as shown in Fig. 5.
The ADC should be initialized by using built-in functions, 1
array_ size = (2)
available in TI Control Suite. It is necessary to define on what f .Ts
GPIOs the input signal is connected to. The ADC output data As an example, to generate a reference voltage with f = 50 Hz
can be retrieved from the register AdcMirror. It must be re- and a sampling time of Ts = 80µs, the size of array_size is
minded that the result of the conversion is a code which for- calculated as 20ms / 80µs = 250 elements.
mat depends on the resolution of the ADC. A further conver- Even though it is strongly recommended not to use any
sion using an appropriate ratio is thus necessary if the user ‘for loop’ or to make complex calculations in real-time pro-
wants to process in the program the real value of the physical grams, the ‘for loop’ utilized in this function does not lead to
quantity that was measured. Considering D as the decimal any delay in the real-time execution of the program. This is
output of the ADC, the input voltage is equal to because this function is developed outside the TIMER0 ISR.
Vref + − Vref − It is to be noted that if a sine wave generating block is re-
V =D + Vref − (1)
212 −1 quired to be built within the ISR, a lookup table option is
in the DSP program where Vref+ = 3 V and Vref– = 0 V. definitely better from time execution point of view.
V. DEVELOPED & UTILIZED FUNCTIONS IN DSP PROGRAM B. High Pass Filter
As discussed earlier, the signals digitally converted by the
A limited number of functions are required to program a ADC have a DC offset value. To eliminate this DC offset of
DSP for VSC applications. TI has a list of different built-in the input signals or to extract the high frequency components
functions. However, as discussed earlier, to optimize the ex- from any desired signal, a High Pass Filter (HPF) needs to be
ecution time of the program, some functions need to be de- developed and utilized within the ISR. Even though TI Con-
veloped and tested independently within single independent trol Suite has some built-in Infinite Impulse Response (IIR)
projects. This approach can be beneficial in a very early stage and Finite Impulse Response (FIR) digital filters available in
of discovery to get familiar with the development environ- its libraries, such functions can be too complex to use as well
ment and comparing them with the built-in functions. as too much time-consuming to run. It is simpler to develop a
To make the programming simpler and more time- more optimized digital IIR filter based on the conversion of
efficient, it is recommended to develop a project by using the the transfer function of the filter. A first order HPF in z-
following method: domain is expressed as
1- First, a flow chart of the complete algorithm of the pro-
gram should be drawn with a description of each function. a + a .z −1
H ( z) = 0 1 (3)
2- Only one single function should be implemented and tested 1 + b1.z −1
at each stage. Ts Ts − 2ω
3- Once the first version of the project is tested successfully, where a0 = a1 = and b1 = and ω is the desired cut-
Ts + 2ω Ts + 2ω
the main .c file may be duplicated and renamed within the
same project. off angular frequency of the filter.
4- The old file needs to be excluded from the project and re- From (3), the output of the HPF developed in ISR is ex-
placed by its duplicate in which an additional function pressed based on its inputs as
will be added and tested. y(TIME) = a0 .x(TIME) + a1.x(TIME − Ts ) − b1. y(TIME − Ts ) (4)
A. Sine Wave Generating Function where x and y are respective the input and output of the HPF.
A sine wave generating function is developed and imple- The equation (4) needs to be implemented with two sets of
mented in the main function, in order to relieve the Timer0 circular buffers, each consisted of two-element– one set for
ISR. This function consists of a ‘for loop’ filling in each ele- the input values and one set for the output values. The circu-
ment of an array with its sine function value. In order to as- lar buffer operates as discussed below:
sign time-respective sine values in the array at each sampling At the first execution of the ISR (i.e. TIME = 0), the input
V1 is saved as the first element of the buffer. At the second
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 5

execution of the ISR (i.e. TIME = Ts), the input is saved as Table 2. Comparison of execution times [clock cycles].
the second element of the buffer. From the third execution of Input Signal FFT DFT Sine Analyzer + PLL
the ISR onwards (e.g. TIME = 2Ts, 3Ts, …), the first element 1-freq. Signal 17622 2063 375
of the buffer is overwritten by the second element while a 2-freq. Signal 17622 2062 376
3-freq. Signal 17622 2056 376
new input is saved as its second element. This is shown
schematically in Fig. 6.
A similar methodology can be applied when implementing v1 v2 v3 v4
a low pass filter. v2 v3
C. Sine Wave Analyzer v1 v1 v 2 v2 v2 v 2 v3 v3 v3 v 3 v4
x0 x 1 x0 x 1 x0 x 1 x0 x 1 x0 x 1 x0 x 1
Different methods can be utilized to define the magnitude Fig. 6. Schematic operation of a 2-element circular buffer.
and phase angle of a given signal, as discussed below:
1- Using the Fast Fourier Transform (FFT) the magnitude and bigger, the process differs slightly though, as discussed be-
phase angle for different frequency components can be low:
calculated. However, due to high number of calculations it 1-During the N first executions of the ISR, the buffers A and
is not really suitable for real-time control of VSCs. B are filled in with the calculated values.
2- If only the magnitude and phase angle of one specific fre- 2- At the end of the Nth execution of the ISR, the buffers are
quency (e.g. 50 Hz) is required to be utilized in ISR, then full and the input RMS and angle are calculated.
the Sine Analyzer and Digital Phase Locked Loop (PLL) 3- At the beginning of the (N+1)th execution of the ISR and
built-in functions of TI Control Suite are more time- onwards, the values of the oldest real element within the
efficient. current input signal period is subtracted from A and the
3- If the input signals have frequencies other than constant 50 oldest imaginary element within the current input signal
Hz (which is more probable in off-grid applications of period is subtracted from B
VSCs), then a Discrete Fourier Transform (DFT) can be 4- Within the same execution cycle of the ISR, a new real
developed by the user and operate fast enough to be uti- element and a new imaginary element of the input signal
lized for real-time purposes. The DFT first detects the are calculated and respectively added to A and B.
fundamental frequency of the input signal and then calcu- 5- Within the same execution cycle of the ISR, the RMS am-
lates its magnitude and phase angle. plitude and phase angle are calculated and updated.
The developed DFT calculates the root mean square Comparing the above three methods, FFT has the longest
(RMS) and phase angle of the fundamental frequency of its computational delay while the Sine Analyzer and PLL com-
input signal, regardless of the signal frequency from bination has the least computational delay. As an example,
2 Table 2 lists a comparison of the execution times, expressed
RMS = A2 + B2 in number of clock cycles, to process several different input
N (5) signals.
Angle= tan−1(B / A)
D. Deadband and Hysteresis Function
where N is the number of samples within a period of the sig-
nal (e.g. N=250 for a 50 Hz input signal), A is the sum of the To provide an acceptable level of tracking for the VSC cur-
real components of the input signal over one period, calcu- rent and voltage, the difference between the desired output
lated as and the actual output should be calculated. This is referred to
N N
as the VSC output tracking error, which should be kept close
⎛ 2π i ⎞
A= ∑Re(xi ) = ∑x[i].cos ⎜⎝ N ⎠
⎟ (6) to zero. Hence, a hysteresis controller can be developed and
utilized to properly turn on and turn off the switches in the
i =0 i =0
VSC to keep the tracking error within a very small bandwidth
and B is the sum of the imaginary components of the input
around zero. This can be achieved by developing ‘if state-
signal over one period
ments’ in the ISR. ‘If statements’ are very fast to execute and
N N
⎛ 2π i ⎞ only creates a negligible delay. Depending on the output of
B= ∑Im(xi ) = ∑x[i].sin ⎜⎝ N ⎟⎠ (6)
the ‘if statements’ a couple of predefined output GPIOs are
i=0 i=0
set to logic High or Low. The GPIOs being set as High or
It is to be noted that the angle needs to be in the range of [0-
Low activates or deactivates the driver circuits of a switch to
2π]. Hence, mathematical function of atan2 should be utilized which the GPIO is connected.
when developing (5) in ISR. The number of samples N is As discussed earlier, the switches in each leg of the VSC
calculated by measuring the period of the input signal. To do should operate in a complimentary fashion to prevent short-
so, the DC component of the input signal is filtered out and at circuiting the DC bus. Hence, it is necessary to implement a
least two periods of the filtered signal need to be stored in a dead-band between the assignments of the complementary
large array. N is given by the number of elements in the large output GPIOs to guarantee the prevention of any probable
array between two zero-crossings of the signal. short-circuits. The dead-band is created by using a ‘while
Circular buffers containing N elements are used to calcu- loop’ and by incrementing a counter until a certain value cor-
late A and B. The principle of this method is similar to the responding to the desired delay. The desired delay should be
procedure explained in the HPF section. Since the buffers are defined based on the recommended deadband of the switches.
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 6

As an illustration, the flowchart of the hysteresis and dead-

band control of the ISR is as shown in Fig. 7.
E. An Example
An example is provided below to summarize an algorithm
developed in the ISR. To provide a better explanation, let us
consider the control for the VSC presented in [13]. The con-
trol algorithm presented in [13] is not of the focus of this pa-
per and hence is not discussed here. Only the development of
the control presented in [13] is discussed in this paper. In
[13], 2 voltages, namely vt and vcf, and two currents namely it
and ish are required to be used as the feedback signals to the
VSC controller. All these signals have a fundamental fre-
quency of 50 Hz. These four signals are hence measured at
the output of the VSC and its filter by the help of sensors and
digitalized by the ADC. The four signals at the output of the
ADC are the inputs for the ISR. The algorithm used for Ti-
mer0 ISR is shown in Fig. 8.
First, a proper signal processing and filtering is carried out
Fig. 7. Flowchart of the hysteresis and dead-band control of the ISR.
on these four signals. Three of them (i.e. vt, vcf and it) are
passed through a developed low frequency high-pass filter v t i t v cf i sh
(HPF) with a cut-off frequency of 1 Hz. The high frequency
component of the fourth signal (ish) is extracted through
K2
another developed HPF, with a cut-off frequency of 2.4 kHz,
v′t i t′
and then multiplied by of constant positive gain K2 and con- ′
v cf
out
sidered as one of the errors in VSC control. Two signals of vt vt
and it are then passed through the built-in Sine Analyzer and it
PLL functions to calculate their respective RMS and phase out
angles. A voltage reference vcf,ref is then generated from the θv t
θi t

calculated RMS and angles which is compared with vcf. The vcf ,ref
K1
result of this comparison is then multiplied by of constant
positive gain K1 and considered as the second error in VSC
control. These two errors are added together and their sum is Fig. 8: Algorithm of the real-time application happening in Timer0 ISR.
compared with a reference by the developed hysteresis func- reached, the program cannot be compiled. Another memory
tion. The hysteresis and deadband controller function gene- slot of 8kB (L7) is used for constant values whereas the 2
rates an output out and its complementary തതതതത
‫ ݐݑ݋‬by the desired other remaining slots of 8kB (L5 and L6) are not used.
deadband limit. These two output commands are then fed to Hence, modifications were needed in the default Linker
the driver circuits of the IGBT switches in the VSC, through Command file to merge the slots L4, L5 and L6 to dedicate
opto-couplers. the new big memory block for global variables.
VI. DSP HARDWARE AND SOFTWARE LIMITATIONS The execution time is another important limitation; TI pro-
vides a good collection of library files for various operations,
A major limitation of embedded systems is the size of their such as digital filtering, waveform analyzing, etc. Although
memory. The TMS320F28355 DSP only contains a 68kB highly optimized, many of these functions take too many
SRAM and a 512kB flash memory. Code, variables and con- clock cycles to execute and may contain features that are not
stant values are managed in the memory through the com- required for the desired VSC application. Hence, developing
mand .cmd file. user defined functions to perform the exact required operation
Although the size of the flash memory is reasonable, using is often more time-efficient.
the flash memory can be delicate and problems may occur Some common issues may occur when programming and
frequently for example when intending to run the ADC with a compiling the program for TMS320F28355 DSP. For exam-
flash-based memory mapping. It is therefore advised to de- ple, in the case of an input signal with a varying frequency, it
velop the program by using SRAM only for simplification. is advised to use only the right amount of memory with dy-
Even though the SRAM is relatively fast but it is small and namic allocation, with respect to the signal frequency. How-
mostly protected, preventing the user from using it to store ever, compilation problems may be encountered when using
data. Maximum of 32kB can be used by the user to store the the most common way to create dynamically sized arrays, i.e.
global variable (referred to as .ebss) [4-6]. By default, this using the malloc and calloc commands. Using only fixed
total available memory of 32kB space is divided into 4 small- sized arrays for the program helps to tackle this issue, even
er spaces of 8kB. Only one small space of 8kB (the memory though it does not optimize the memory usage.
space L4) is used for global variables and once that limit is
 Australasian Universities Power Engineering Conference, AUPEC 2014, Curtin University, Perth, Australia, 28 September – 1 October 2014 7

Another common problem is the loss of connection be- a0 a1 a2 a3 ak an

tween the CCS and DSP docking station when high voltages
are used in the surrounding environment [14]. This is due to
the fact that a direct Joint Test Action Group (JTAG) connec- Fig. 9. Dynamic use of a fixed-size array
tion cannot cope with a too high amount of electrical noise. In
For the program to perform in real-time, the execution time of
such a case, the Future Technology Devices (FTDI) chip
the Timer0 ISR function needs to be measured and limited to
driver will crash and disrupt the communication. This prob-
less than the sampling period.
lem can be solved by using an isolated adapter for JTAG
emulator such as TI TMDSADP1414-ISO [15] or Spectrum VIII. CONCLUSION
digital SPI110LV [16].
DSPs and in particular TI TMS320F28335 are powerful
VII. MONITORING AND DEBUGGING DSP PROGRAM tools to implement digital control systems for a VSC. How-
ever, the user must be experienced in C language program-
TI CCS enables the user to optimize automatically a
ming and must understand the architecture of the DSP in or-
project during its compilation in terms of execution speed or
der to be able to achieve the implementation of the control
the code size. Additionally, CCS provides real-time access to
with CCS. Moreover, although TI has conveniently devel-
the DSP memory to monitor any variables during the execu-
oped a series of built-in functions, the user may need to modi-
tion of the program, provided that CCS is in debugging mode
fy them or develop new custom functions to improve the ex-
and the host computer is connected to the target.
ecution time of the program.
To display one full period of the waveform of a periodic
signal generated internally or acquired through ADC in CCS, REFERENCES
an array needs to be created. For a signal with a constant fre- [1] R. Feldman, M. Tomasini, E. Amankwah, et al. “A Hybrid Modular
quency, the created array Array[N] contains N elements so Multilevel Voltage Source Converter for HVDC Power Transmission,”
that it stores all the samples over one period. The calculation IEEE Trans. on Industry Applications, Vol. 49, No. 4, pp. 1577–1588,
of the size of the array is as discussed in (2). For example, for July/August 2013
[2] F. Huerta, S. Cóbreces, F. J. Rodríguez, et al. “State-Space Model Iden-
a signal with a frequency of 50 Hz, N = 250. Then, an index tification of an LCL Filter used as interface between a Voltage Source
pointer is created in order to point at the element of the array Converter and the electrical grid,” in Proc. of IEEE Energy Conversion
where the corresponding sample of the waveform needs to be Congress and Exposition (ECCE), 2009
saved. The index is an integer that is initialized to 0 and in- [3] R.M. Milasi, A.F. Lynch and Y.W. Li, “Adaptive vector control for
voltage source converters,” IET Control Theory Appl., 2013, Vol. 7, Iss.
cremented during each interruption until it reaches the value 8, pp. 1110–1119
N–1. It is then reset to 0 in order to start a new cycle such that [4] F. Bormann, C2000™ Teaching CDROM– 3rd Rev. 2010 (available at:
each element of the array is overwritten by the same sample. http://www.ti.com/europe/docs/univ/)
For example, for a 50 Hz signal, the rest happens when the [5] C.A. Sepúlveda, J.A. Muñoz, J.R. Espinoza, et al. “FPGA v/s DSP Per-
formance Comparison for a VSC-Based STATCOM Control Applica-
index pointer reaches 249. Now, if the program runs and the tion,” IEEE Trans. on Industrial Informatics, Vol. 7, No. 2, pp. 1351–
real-time debugger of CCS is enabled, the graph tool can be 1360, May 2011
used to display the values of Array[N] which is stored in the [6] TMS320F28335 Digital Signal Controllers (DSCs), Data Manual, Lite-
memory from the address &Array[0] and onwards. rature Number: SPRS439M, June 2007–Revised August 2012,
http://www.ti.com/lit/ds/sprs439m/sprs439m.pdf
However, if the frequency of the signal is varying, the size [7] TMS320F2837xD, Dual-Core Delfino™ Microcontrollers, Literature
of the array should also vary accordingly, or alternatively, the Number: SPRS880A, December 2013–Rev. March 2014, Texas Instru-
space used in the array should change in consequence, pro- ments http://www.ti.com/lit/ds/symlink/tms320f28376d.pdf
[8] TMS320x2833x, 2823x Serial Communications Interface (SCI), Litera-
vided the array is large enough to contain all the samples of ture Number: SPRUFZ5A August 2008–Revised July 2009 Texas In-
the longest expected period. In this case, in an array of size struments http://www.ti.com/lit/ug/sprufz5a/sprufz5a.pdf
n+1 (e.g. 400) containing the elements [a0 - an], only the ele- [9] Quick Start Guide, TMS320C2000™ Experimenter’s Kit Overview,
ments from [a0, a1, …, ak] are considered while the remaining Literature Number: SPRUFR5F, June 2008–Revised Feb. 2011, Texas
Instruments, available at http://www.ti.com/lit/ml/sprufr5f/sprufr5f.pdf
elements [ak, ak+1, …, an] are ignored. k is determined from
[10] eZdspTM, F28335, Technical Reference 510195-0001, Nov. 2007, De-
the signal period similar to (2). This measurement is updated velopment Systems, Spectrum Digital Inc., available at
at every Timer0 ISR interruption. The illustration of this http://c2000.spectrumdigital.com/ezf28335/docs/ezdspf28335c_techref.pdf
strategy is shown on Fig. 9. Even though resource consum- [11] Code Composer Studio (CCS) Website, http://www.ti.com/tool/ccstudio
[12] C2000 Getting Started with Code Composer Studio v.5 Manual
ing, this method performs well and is simple to implement. http://processors.wiki.ti.com/index.php/C2000_Getting_Started_with_Code_Comp
It must be noted that a mismatch between the number of oser_Studio_v5
elements displayed in the graph and the period of the wave- [13] F. Shahnia, R.P.S. Chandrasena, S. Rajakaruna, et al. “Primary control
level of parallel distributed energy resources converters in system of
form may cause the waveform to look as if it was moving multiple interconnected autonomous microgrids within self-healing net-
inside the graph, making the observations difficult. works,” IET Gen., Trans. & Dist., Vol. 8, Issue 2, pp. 203-222, 2014.
Furthermore, setting break points within the program is a [14] JTAG Emulator Adapter Board Kit 14e-60t Quick Start Guide, 2004,
versatile tool provided by TI CCS to measure the execution Texas Instruments http://www.ti.com/lit/ug/spru814/spru814.pdf
[15] Emulation and Trace Headers, Technical Reference Manual, Literature
time of certain instructions or sets of instructions, in terms of Number: SPRU655I. Feb. 2003–Revised Aug. 2012, Texas Instruments,
number of clock cycles. This function is available only when available at http://www.ti.com/lit/ug/spru655i/spru655i.pdf
CCS is running in debugging mode with enabled clock tool. [16] http://www.spectrumdigital.com/product_info.php?products_id=33