COMPUTER ARCHITECTURE

AND ASSEMBLY LANGUAGE

14:332:333

PROJECT NUMBER :3

PROJECT NAME : 32 BIT MULTI CYCLE DATAPATH

NAME : DAIYAN ALAMGIR

STUDENT ID : 118001253

REPORT DUE DATE : 11/30/2009

T.A. : JOHN PAUL VARKEY

TABLE OF CONTENTS PAGE

01. Project Description 01

02. Diagrammatic Representation of the Datapath 01

03. Instructions 01

04. Format of the Instruction Set 02

05. Module alu 05

06. Module register 05

07. Module shifter 06

08. Module control 06

09. Module mux 06

10. Module processor 07

11. Module testBench 07

12. Module connection 07

13. Table of Inputs to the Machine 08

14. Textual Translation of the Inputs 10

15. Appendix (All Codes) 11

PROJECT DESCRIPTION

The project involves the use of Verilog to construct a 32 Bit datapath and control that
implements a set of specific instructions. The instruction set that the 32 Bit datapath is required
to implement is given in the following sections along with the format of the instruction set. The
processor that is required to be designed is not pipelined and hence involves multicycles. The
first cycle will involve instruction decode, which will be responsible for determining what the
instruction is and how the instruction is required to be executed. The second cycle involves
instruction execution and writeback. Instruction execution executes the instruction according to
the way in which it was decoded and the writeback function writes the output data to a register
file as specfied by the instruction. The project is designed to incorporate five different modules
(Control Unit, Register File, ALU, Shifter and Multiplexor) which will all be later used by
another model called the processor. In the following sections, each of these modules are
explained in detail. Finally, a testbench was required to be design that will test the functionality
of all the modules designed to implement the 32 Bit datapath.

DIAGRAMMATIC REPRESENTATION OF THE DATAPATH

INSTRUCTIONS

The 32 Bit multicycle datapath and control is required to implement the following instructions:

INSTRUCTION TYPE INSTRUCTION

Arithmetic (Unsigned) add
Logical and, nand, or, xor, xnor
Shift sll, srl
FORMAT OF THE INSTRUCTION SET

Each instruction that is fed to the datapath is required to be 18 bits long. The following table
shows how the 18 bit instruction is required to be decoded by the datapath:

OPCODE DESTINATION SOURCE SOURCE

REGISTER REGISTER1 REGISTER2 /
SHIFT AMOUNT

3 BITS 5 BITS 5 BITS 5 BITS

The datapath determines the type of the instruction and the operation it is supposed to perform by
decoding the opcode. The following table shows the list of opcodes that the datapath recognizes
and the instruction type that each opcode is decoded to:

OPCODE INSTRUCTION TYPE

000 ADD
001 AND
010 NAND
011 OR
100 XOR
101 XNOR
110 SLL – SHIFT LEFT LOGICAL
111 SRL – SHIFT RIGHT LOGICAL
MODULES

In order for the 32 Bit multicycle datapath to be functional, its construction involved the
designing of several modules that each performed the instructions specified by the given table of
instructions. The instruction modules were separated into three basic categories:

 Arithmetic (Unsigned) – Conducted the addition of two inputs

 Logical – Performed the logical operations on the inputs
 Shift – Performed the sll and srl operations on the given inputs

Module alu

The alu module contains the specifications required to control the logic and arithmetic
instructions. A mux is programmed inside the alu which selects the required output depending on
the decoding of the opcode which specifies a certain type of instruction. The alu takes two inputs
from the two source register files and produces one output after conducting certain arithmetic or
logical operations on the inputs. The output of the alu is routed to another mux which also
receives the input from the shifter. Overall, the alu consists of objects created from the logic,
adder and mux modules, each of which are required to either perform some arithmetic or logic
operation or control which operation needs to be performed. The alu design code is provided in
the appendix at the end of the report.

Adder

The adder module represents the arithmetic instruction type and was responsible for the addition
of two inputs. The verilog code for the adder module is given in the Appendix section. The
function adder takes two arguments and returns one result. Depending on the suitable opcode, the
adder will be called upon and it will take the two inputs specified by the source registers and will
display their computer sum. The adder is implemented by the ALU which contains an object of
the adder module and is controlled by the control signals provided by the control unit.

Logic

The logic module consists of all the logical operations that is required to be conducted on given
inputs. The logic module contains five different logic operations that is required to be performed
on the given inputs. These instructions are decoded by the datapath using the appropriate opcode.
The logic module takes two inputs (which are obtained by reading the two source registers) and
assigns five different outputs to five different logic operations conduction on the two inputs that
it receives. An instance of the logic module is constructed in the ALU module, which will be
later described, and the logic module operates based on the signals supplied by the control unit.
The Verilog code for the logic module is supplied in the appendix section.

Module register

The register module consists of the construction of the 32 bit register files. The register files are
read or written depending on the signals passed from the control. In the decode stage, the register
files are read and the output of the register file provides the two inputs for the alu. These two
registers are connected to the alu. The first clock edge will indicate the decode state. The decode
state will give the read signal and the output of the register file will provide the output of the two
registers. The execution stage will be enabled at the next clock cycle and it will compute the
action of the instruction. Finally, the registers are written back at the negative edge of the clock
cycle. The register files therefore perform their necessary operations depending on the signals
sent to them from the control. The register file is also responsible to supply an input to the shifter
depending upon the instructions that it receives. The full construction of the register file is given
in the appendix section containing the verilog codes.

Module shifter

The shifter module is responsible for shifting a certain value either to the left or to the right
depending on the instruction provided. The opcode is decoded into the sll or srl instruction and
the shifter module responds to the opcode by performing the specified task. The shifter takes a
value named sel. The sel value is the signal received from the control unit and is checked in the
decode stage. If sel value is set to 0, then it is recognized as a left shift and if sel is set to 1, it is
recognized as a right shift. After a left shift or a right shift is recognized, the input is shifted by
the shift amount specified by the value of shamt. An instance of the shifter module is created in
the processor module and is controlled by signals from the controller. The code written in
Verilog that describes the operation of the shifter is provided in the appendix section.

Module mux

The mux module controls the multiplexor that is connected to the ALU and the shifter and is
controlled by signals from the controller. The mux takes three values, aluSel, shifterSel and
controlSig which are the alu selection, the shifter selection and the control signal respectively. If
the control signal is 0, then the ALU selection is active and the mux takes the input from the
ALU output. If the control signal is 1, the mux selects the shifter input and acts accordingly. The
output from the mux is written back to the register file at the negative edge of the clock cycle
after the execution stage is complete. The verilog code for the design of the multiplexor that
controls the alu and the shifter is given in the appendix section as mux1.

Module control

The control module represents the control unit that is responsible for sending the appropriate
signals which enable the components of the datapath to complete the process described by the
instructions that are fed into the datapath. The control unit acts according to the successful
decoding of the instructions and the module is implemented as a state machine. The controller
depends on three states: reset, decode and execute. The controller will go to the reset state
whenever the reset signal equals 0. In the reset state, the instructions will neither be decoded nor
executed. When the signal reset = 1, the control unit will either be in the decode state or the
execute state. The decode state involves only the decoding of the instructions and the setting of
the appropriate control signals. All other modules of the machine have no function during this
state. The next clock cycle introduces the execute state. In this state, the instructions are executed
according to the way in which they were decoded and written back to the register file in the
negative edge of the clock cycle. First, the register file will read the values from the source
registers and send out the operands to be operated on. Depending on the type of instruction that
was passed, the ALU or the Shifter will be active and will act accordingly. Finally, the mux will
select the appropriate output from either the ALU or the Shifter and send it back to the register
for write back. In this way, each instruction takes two clock cycles and the whole operation
described above is controlled by the control unit which is implemented as a state machine. The
verilog design codes for the control module is provided in the appendix section.

Module processor

The processor module culminates all the other modules that have been constructed and consists
of the final wiring that connects all other modules. Instants of the alu, register file, shifter, and
mux modules are all created in the processor module. The processor module however is
instantiated in the testbench (which is described below). The processor module uses wires to
denote the interconnections between the several modules that have been constructed and hence
the processor module provides the successful operation of the datapath. The verilog code which
shows the construction of the processor module is provided at the end of the report in the
appendix section.

Module testbench

The module testbench consists of the instructions that are used to test the successful operation of
the datapath and so see if all the modules constructed are fully functional. An instance of the
processor module is created in the testbench which contains all the instructions used to test the
32 bit multicycle datapath. The code written to construct the testbench module is provided at the
end of the report in the appendix section.

Module connection

The module connection is the last module created that connects the testbench and the processor.
Instances of the testbench and the processor modules are created in this module and the
connection module acts as the bridge connecting the processor which is required to carry out the
process and the testbench which provides the instructions required to test the datapath. The code
written in verilog to construct the connection module is provided at the end of the report in the
appendix section.
 TABLE OF INPUTS TO THE MACHINE

MODULE INSTRUCTION SIZE NAME DESCRIPTION

TYPE (BITS)
Opcode received from the control which tells
Input 3 op the alu what type of instruction it is and what
function has to be performed.
Contents of the source register 1 which is
Input 32 rs read into the alu and this is used as the first
ALU input.
Contents of the source register 2 which is
Input 32 rt read into the alu and this is used as the
second input.
The final output from the alu after the
Output 32 aluOut arithmetic and locial operations have been
performed on the inputs.
Selection bit which indicates if the bits that
Input 1 sel have been input need to be shifted right or
left.
The contents of a source register is read into
Input 32 rt the shifter since it only uses one register
SHIFTER input for its operation.
The instruction is an input to the shifter since
Input 18 ins the instruction contains the amount to be
shifted by.
The output from the shifter is the final value
Output 32 shifterOut after the srl or sll operations have been
conducted on the data.
Readwrite bit represents the control signal
Input 1 readwrite which decides if the registers will be read or
written to.
Clk is the clock cycles. Registers are read in
Input 1 clk the positive edge of the cycle and are written
in the negative edge.
The instruction is an input to the register file
Input 18 ins since it contains the values of the source
REGISTER registers and the destination.
The ouput from the multiplexor is the 32 bit
Input 32 muxOut output from the ALU or the shifter which is
written back to the register file.
The contents from source register 1 which is
Output 32 rs fed into the alu on the positive edge of the
clock.
The contents from source register 2 which is
Output 32 rt fed into the alu or shifter on the positive edge
of the clock.
 Clk is the clock cycles. Registers are read in
Input 1 clk the positive edge of the cycle and are written
in the negative edge.
This represents the reset bit which can either
be 0 or 1. When the reset signal is 0, no
Input 1 reset decoding or execution is done. When reset is
1, the machine is either in decode or execute
state.
The total instruction that is fed into the
Input 18 ins control where the instruction is decoded and
appropriate signals are obtained.
After decoding the instruction, the opcode is
CONTROL Output 3 op sent by the control to the alu to determine
what type of instruction it is.
Selection bit that is sent to the shifter to
Output 1 sel make the shifter active and hence perform its
tasks.
The mux selection bit that is fed to the mux
Output 1 muxIn to either select the writeback from the alu
data or writeback from the shifter data.
The control signal that is passed to the
Output 1 readwrite register file to read from register file or write
to register file.
Bits that indicate the present state of the
Output 2 present machine since the control is implemented as
a state machine.
Bits that indicate the next state of the
Output 2 next machine since the control is implemented as
a state machine.
Input 1 muxIn Control signal that is passed from the control
MUX unit that controls the activation of the alu
output or the shifter output.
Input 32 aluOut The data from the alu that is passed through
to the mux if the alu output is selected by the
control signal.
Input 32 shifterOut The data from the shifter that is passed
through to the mux if the alu output is
selected by the control signal.
Output 32 muxOut The data that is written back to the register
file once the appropriate control signals are
received from the control unit.
TEXTUAL TRANSLATION OF THE INPUTS

The following inputs were used in the testbench to test the performance and behavior of the 32
bit multicycle datapath. The inputs and their textual translations are as follows:

INTRUCTION IN BINARY VALUE OF INSTRUCTION TEXTUAL

TESTBENCH INSTRUCTION TYPE TRANSLATION
Add the contents of register
#20 ins = 1091; 000000010001000011 ADD $2 and register $3 and store
the final value in register $1.
Perform the logical operation
#20 ins = 37030; 001001000010100110 AND AND on the contents of
register $5 and register $6 and
store the value in register $4.
Perform the logical operation
#20 ins = 72969; 010001110100001001 NAND NAND on the contents of
register $8 and register $9 and
store the value in register $7.
Perform the logical operation
#20 ins = 108908; 011010100101101100 OR OR on the contents of register
$11 and register $12 and store
the value in register $10.
Perform the logical operation
#20 ins = 144847; XOR XOR on the contents of
100011010111001111 register $14 and register $15
and store the value in register
$13.
Perform the logical operation
#20 ins = 180786; XNOR XNOR on the contents of
101100001000110010 register $17 and register $18
and store the value in register
$16.
Perform the shift left logical
#20 ins = 216706; 110100111010000010 SLL on the contents of register $20
by 2 and store the value in
register $19.
Perform the shift right logical
#20 ins = 251585; 111101011011000010 SRL on the contents of register $22
by 2 and store the value in
register $22.
$finish Instruction to end the
simulation
VERILOG CODES:

Module Alu:
module alu(op, rs, rt, aluOut);

input [2:0] op;

input [31:0] rs, rt;

output [31:0] aluOut;

reg [31:0] aluOut;

always @ (op or rs or rt)

begin

// ADD OPERATION
if (op == 3'b000)
begin
aluOut <= (rs + rt);
end

// AND OPERATION
else if (op == 3'b001)
begin
aluOut <= (rs & rt);
end

// NAND OPERATION
else if (op == 3'b010)
begin
aluOut <= ~(rs & rt);
end

// OR OPERATION
else if (op == 3'b011)
begin
aluOut <= (rs | rt);
end

// XOR OPERATION
else if (op == 3'b100)
begin
aluOut <= (rs ^ rt);
end

// XNOR OPERATION
else if (op == 3'b101)
begin
aluOut <= (rs ~^ rt);
end

end
endmodule
Module Register:
module register(readwrite, ins, clk, muxOut, rs, rt);

input readwrite, clk;

input [17:0] ins;
input [31:0] muxOut;

output reg [31:0] rs, rt;

reg [31:0] myRegFile [31:0];

always @ (posedge clk)

begin
if (readwrite == 1)
begin
rs <= myRegFile[ins[9:5]];
rt <= myRegFile[ins[4:0]];
end
end

always @ (negedge clk)

begin
if (readwrite == 1)
begin
myRegFile[ins[14:10]] <= muxOut;
end
end

initial
begin

myRegFile[0] = 1;
myRegFile[1] = 2;
myRegFile[2] = 3;
myRegFile[3] = 4;
myRegFile[4] = 5;
myRegFile[5] = 6;
myRegFile[6] = 7;
myRegFile[7] = 8;
myRegFile[8] = 9;
myRegFile[9] = 1;
myRegFile[10]= 2;
myRegFile[11]= 3;
myRegFile[12]= 4;
myRegFile[13]= 5;
myRegFile[14]= 6;
myRegFile[15]= 7;
myRegFile[16]= 8;
myRegFile[17]= 9;
myRegFile[18]= 1;
myRegFile[19]= 2;
myRegFile[20]= 3;
myRegFile[21]= 4;
myRegFile[22]= 5;
myRegFile[23]= 6;
myRegFile[24]= 7;
myRegFile[25]= 8;
myRegFile[26]= 9;
myRegFile[27]= 1;
myRegFile[28]= 2;
myRegFile[29]= 3;
myRegFile[30]= 4;
myRegFile[31]= 5;

end
endmodule
Module Shifter:
module shifter(sel, rt, ins, shifterOut);

input sel;
input [31:0] rt;
input [17:0] ins;

output [31:0] shifterOut;

reg [31:0] shifterOut;

always @ (sel or rt or ins)

begin
if (ins[4:0] == 5'b00000)
begin
shifterOut = rt;
end
else if (!sel)
begin
shifterOut = rt << ins[4:0];
end
else if(sel)
begin
shifterOut = rt >> ins[4:0];
end

end
endmodule
Module Control:
module control(clk, reset, ins, op, sel, muxIn, readwrite, present, next);

input clk, reset;

input [17:0] ins;

output reg [2:0] op;

output reg sel;
output reg muxIn;
output reg readwrite;
output reg [1:0] present, next;

parameter A=0, B=1, C=2;

always @ (posedge clk or negedge reset)

begin
if(reset == 0)
present <= A;
else
present <= next;
end

always @ (present)
begin
case(present)

A:
begin
op = 3'b000;
sel = 0;
muxIn = 0;
readwrite = 0;
next<=B;
end

B:
begin
op = ins[17:15];
sel = ins[15];
if (ins[17:16] == 2'b11)
begin
muxIn <= 1;
end
else
begin
muxIn <= 0;
end
readwrite = 0;
next<=C;
end
 C:
begin
op = ins[17:15];
sel = ins[15];
if (ins[17:16]==2'b11)
begin
muxIn=1;
end
else
begin
muxIn=0;
end
readwrite=1;
next<=B;
end

endcase

end
endmodule
Module Mux:

module mux(muxIn, aluOut, shifterOut, muxOut);

input muxIn;
input [31:0] aluOut, shifterOut;

output [31:0] muxOut;

reg [31:0] muxOut;

always @ (muxIn or aluOut or shifterOut)

begin
if(muxIn == 0)
muxOut = aluOut;
else
muxOut = shifterOut;
end

endmodule
Module Processor:

module processor(ins, clk, reset);

input [17:0] ins;

input clk, reset;

wire sel, muxIn, readwrite;

wire [31:0] shifterOut, muxOut, aluOut, rs, rt;
wire [2:0] op;

control controlUnit (clk, reset, ins, op, sel, muxIn, readwrite, present, next);

alu myAlu(op, rs, rt, aluOut);

register myReg(readwrite, ins, clk, muxOut, rs, rt);

shifter mySht(sel, rt, ins, shifterOut);

mux myMux(muxIn, aluOut, shifterOut, muxOut);

endmodule
Module TestBench

module testBench(ins, clk, reset);

output [17:0] ins;

output clk, reset;
reg [17:0] ins;
reg clk, reset;

initial
begin

clk = 1; reset = 0; ins = 0;

#20 reset = 1;
#20 ins = 1091;
#20 ins = 37030;
#20 ins = 72969;
#20 ins = 108908;
#20 ins = 144847;
#20 ins = 180786;
#20 ins = 216706;
#20 ins = 251586;
#20 $finish;

end

always
#15 clk = ~clk;

Endmodule
Module Connection

module connection;

wire clk, reset;

wire [17:0] ins;

processor myprocessor(ins, clk, reset);

testBench mytestBench(ins, clk, reset);

endmodule