Unit 7: A/D and D/A Converter: Lesson 1: Interfacing With The Analog World
Unit 7: A/D and D/A Converter: Lesson 1: Interfacing With The Analog World
0V to 0.8V = logic 0
2V to 5V = logic 1
Any voltage falling in the range 0 to 0.8 V is given the digital value 0,
and any voltage in the range 2 to 5 V is assigned the digital value 1. The
digital circuits respond accordingly to all voltage values within a given
range.
Most physical variables are analog in nature and can take on any value
Most physical variables within a continuous range of values. Examples include temperature,
are analog in nature and pressure, light intensity, audio signals, position, rotational speed, and
can take on any value flow rate. Digital systems perform all of their internal operations using
within a continuous range digital circuitry and digital operations. Any information that has to be
of values. inputted to a digital system must first be put into digital form. Similarly,
the outputs from a digital system are always in digital form.
1.2.1. Transducer
Digital Digital
inputs outputs
1.2.4. Actuator
The analog signal from the
DAC is often connected to The analog signal from the DAC is often connected to some device or
some device or circuit that circuit that serves as an actuator to control the physical variable. For our
serves as an actuator to water temperature example, the actuator might be an electrically
control the physical controlled valve that regulates the flow of hot water into the tank in
variable. accordance with the analog voltage from the DAC. The flow rate would
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MSB
The digital inputs D,C,B, and A are usually derived from the output
register of a digital system. The 24 = 16 different binary numbers
represented by these 4 bits for each input number, the D/A converter
output voltage is a unique value. In fact, for this case, the analog output
voltage Vout is equal in volts to the binary number.
In general,
Analog output = K × digital input
We can use this to calculate VOUT for any value of digital input. For
example, with a digital input of 11002 = 1210, we obtain
VOUT = 1V × 12 = 12V
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Problem 1
Solution
The digital input 101002 is equal to decimal 20. Since IOUT = 10 mA for
this case, the proportionality factor as 0.5 mA. Thus, we can find for a
digital input such as 111012 = 2910 as follows :
IOUT = (0.5mA) × 29
= 14.5 mA
Problem 2
What is the largest value of output voltage from an 8-bit DAC that
produces 1.0V for a digital input of 00110010?
Solution
001100102 = 5010
1.0 V = K× 50
Therefore,
K = 20 mV
VOUT(max) = 20mV×255
= 5.10 V
Analog Output
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Input Weights
For the DAC of it should be noted that each digital input contributes a
different amount to the analog output. This is easily seen if we examine
the cases where only one input is HIGH Table 7.1. The contributions of
each digital input are weighted according to their position in the binary
number.
D C B A VOUT (V)
0 0 0 1 → 1
0 0 1 0 → 2
0 1 0 0 → 4
1 0 0 0 → 8
Table 7.1
Thus, A, which is the LSB, has a weight of 1V, B has a weight of 2V, C
has a weight of 4 V, and D, the MSB, has the largest weight 8V. The
weights are successively doubled for each bit, beginning with the LSB.
Thus, we can consider VOUT to be the weighted sum of the digital inputs.
For instance, to find VOUT for the digital input 0111 we can add the
weights of the C, B, and A bits to obtain 4 V + 2V + 1V=7V.
Problem 3
A 5-bit D/A converter produces VOUT = 0.2 V for a digital input of 0001.
Input Weights Find the value of Vout for an input of 11111.
Problem 3 and Solution
Solution
Obviously, 0.2 V is the weight of the LSB. Thus, the weights of the
other bits must be 0.4 V, 0.8 V, 1.6 V, and 3.2 V respectively. For a
digital input of 11111, then, the value of VOUT will be 3.2 V + 1.6 V+
0.8V + 0.4V + 0.2 V = 6.2 V.
1.4. Resolution
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0000, the DAC output returns to 0V. The resolution or step size of the
jumps in the staircase waveform; in this case, each step is 1 V.
Full-scale
(input = 1111) 15 V
4-bit
counter
10V
D
D/A
converter
C
V OUT 5V
B 4V Input
3V
Resolution 2V recycled to
A =1V 1V 0000
0V Time
Clock
Resolution = step size = 1 V
Note that the staircase has 16 levels corresponding to the 16 input states,
but there are only 15 steps or jumps between the 0-V level and full-scale,
In general, for an N-bit DAC the number of different levels will be 2N,
and the number of steps will be 2N - 1.
You may have already figured out the resolution (step size) is the same
as the proportionality factor in the DAC input/output relationship :
Problem 4
For the DAC of Example 3 determine VOUT for a digital input of 10001.
Solution
The step size is 0.2 V, which is the proportionality factor K. The digital
input is 10001 = 1710. Thus we have :
VOUT = (0.2 V) × 17
= 3.4V
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step size
% resolution = × 100%
full scale ( F . S . )
1V
= × 100% = 6.67%
15 V
Percentage Resolution
Problem 5 and Solution Problem 5
A 10-bit DAC has a step size of 10 mV. Determine the full-scale output
voltage and the percentage resolution.
Solution
With 10 bits, there will be 210 - 1 = 1023 steps of 10mV each. The full-
scale output will therefore be 10mV × 1023 = 10.23 V and
10 mV
% resolution = × 100% ≈ 01%
.
10.23 V
1
% resolution = × 100%
total number of steps
For an N-bit binary input code the total number of steps is 2N-1. Thus,
for the previous example,
1
% resolution = 10 × 100%
2 −1
1
= × 100%
1023
≈ 01%
.
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This means that it is only the number of bits which determines the
percentage resolution. Increase of the number of bits increases the
number of steps to reach full scale.
1.6. Exercise
i) binary number
ii) decimal number
iii) hexa- decimal number
iv) octal number.
i) input
ii) output
iii) number
iv) all of the above.
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A/D and D/A Converter
Several different binary codes such as straight binary, BCD and offset
binary are commonly used as inputs to D/A converters.
D/A-Converter Circuitry There are several methods and circuits for producing the D/A operation. We
shall examine several of the basic schemes, to gain an insight into the ideas
used.
1K Rt = 1 K
MSB D
2K
C +Vs
- OP VOUT
4K amp
B +
-Vs
8K
LSB A
Digital inputs :
0 V or 5 V
Fig. 7.4 : DAC circuitry using op-amp with binary weighted resistors.
Fig. 7.4 shows the basic circuit of 4-bit DAC. The inputs A,B,C, and D are
binary inputs which are assumed to have values of either 0 V or 5 V. The
operational amplifier is employed as a summing amplifier, which produces
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the weighted sum of these input voltages. the summing amplifier multiplies
each input voltage by the ratio of the feedback resistor RF to the
corresponding input resistor RIN. In this circuit RF RIN 1kΩ and the input
resistors range from 1 to 8 kΩ . The D input has RIN = 1KΩ, so the summing
amplifier passes the voltage at D with no attenuation. The C input has RIN =
2 kΩ, so that it will be attenuated by. Similarly, the B input will be
attenuated by ¼ and the A input by 1/8. The amplifier output can thus be
expressed as
The resolution of this D/A converter is equal to the weighting of the lSB,
which is 1/8 × 5V = 0.625 V. The analog output increases by 0.625 V as the
binary input number advances one step.
Problem 6
Problem 6 Assume VREF = 10 V and R = R = 10 kΩ. Determine the resolution and full-
Solution scale output for this DAC. Assume that RL is much smaller than R.
Solution
I0 = VREE/R = 1 mA. This is the weight of the MSB. The other three currents
will be 0.5, 0.25, and 0.125 mA. The LSB is 0.125 mA, which is also the
resolution.
The full-scale output will occur when the binary inputs are all HIGH so that
each current switch is closed and
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The DAC circuits we have looked at, has some practical limitations. The
biggest problem is the large difference in resistor values between the LSB
and MSB, especially in high-resolution DACs. One of the most widely used
DAC circuits that uses resistance’s fairly close in value is the R/2R ladder
R/2R Ladder
network. Here the resistance values span a range of only 2 to 1.
Note, how the resistors are arranged, and only two different values are used,
R and 2R. The current IOUT depends on the positions of the four switches,
and the binary inputs B3B2B1B0 control the states of the switches. This
current is allowed to flow through an op-amp current-to-voltage converter to
develop VOUT. It can be shown that the value of VOUT is given by the
expression.
− VREF
VOUT = × B.
8
where B is the value of the binary input, which can range from 000 (0) to
1111 (15).
+ VREF
2R
2R 2R 2R 2R
2R R R R
- VOUT
lOUT +
Bo B1 B2 B3
(LSB) (MSB)
2.4.1. Resolution
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2.4.2. Accuracy
There are several ways of specifying accuracy. The two most common
are called full-scale error and linearity error. which are normally
expressed as a percentage of the converter’s full-scale output (%F.S.)
Full-scale error is the maximum deviation of the DAC’s output from its
expected (ideal) value, expressed as a percentage of full scale. For
example, assume that the DCA has an accuracy of ± 0.01% F.S. Since
this converter has a full-scale output of 9.375 V, this percentage converts
to
This means that the output of this DAC can, at any time, be off by as
much as 0.9375mV from its expected value.
Linearity error is the maximum deviation in step size from the ideal step
size. For example, the DAC has an expected step size of 0.625 V. If this
converter has a linearity error of ± 0.01F.S,, this would mean that the
actual step size could be off by as much as 0.9375 mV.
Problem 7
Example 7 and
A certain 8-bit DAC has a full-scale output of 2mA and a full-scale error
Solution
of ± 0.5% F.S. What is the range of possible outputs for an input of
10000000?
Solution
The step size is 2mA/255 = 7.84 µA. Since 10000000 = 12810, the ideal
output should be 128 × 7.84 µA. The error can be as much as
Thus, the actual output can deviate by this amount from the ideal
1004µA , so the actual output can be anywhere from 994 to 1014 µA.
Ideally, the output of a DAC will be zero volts when the binary input is
all 0’s. In practice, however, there will be a very small output voltage for
Offset Error
this situation; this is called offset error. This offset error, if not
corrected, will be added to the expected DAC output for all input cases.
Offset error can be negative as well as positive.
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Many DACs will have an external offset adjustment that allows you to
zero the offset. This is usually accomplished by applying all 0s to the
DAC input and monitoring the output while an offset adjustment
potentiometer is adjusted until the output is as close to 0 V as required.
2.4.5. Monotonicity
DACs are used whenever the output of a digital circuit has to provide an
analog voltage or current to drive an analog device. Some of the most
common applications are described in the following paragraphs.
2.5.1. Control
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2.6. Exercise
i) LSB
ii) MSB
iii) full scale output
iv) 1 volt.
b) When the binary input is all 0.s, ideally the output of a DAC will
be?
i) Zero volt
ii) Full scale output voltage
iii) 1 volt
iv) One step voltage.
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A/D and D/A Converter
The basic operation of ADCs of this type consists of the following steps:
The basic operation of
ADC. 1. The START COMMAND pulse initiates the operation.
2. At a rate determined by the clock, the control unit continually
modifies the binary number that is stored in the register.
3. The binary number in the register is converted to an analog voltage,
VAX, by the DAC.
VA 1
+ 0 Start command
Countrol
Op amp
-
unit Clock
Comparator EOC
(end of conversion)
D/A .
Register
VAX converter .
.
.
Digital result
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4. The comparator compares VAX with the analog input VA. As long as
VAX < VA1 the comparator output stays HIGH. When VAX exceeds VA
by at least an amount = VT ( threshold voltage), the comparator
output goes LOW and stops the process of modifying the register
number. At this point, VAX is a close approximation to VA. The digital
number in the register, which is the digital equivalent of VAX, is also
the approximate digital equivalent of VA1 within the resolution and
accuracy of the system.
5. The control logic activates the end-of-conversion signal, EOC, when
the conversion is complete.
One of the simplest versions of the general ADC of Fig. 7.7 uses a
Operation procedure of a binary counter as the register and allows the clock to increment the
digital-ramp ADC.
counter one step at a time until VAX ≥ VA. It is called a digital-ramp
ADC because the wave form at VAX is a step-by-step ramp (actually a
staircase) like the one shown in Fig. 7.7. It is also referred to as a
counter-type ADC. Fig. 7.7 is the diagram for a digital-ramp ADC. It
contains a counter, a DAC, an analog comparator, and a control AND
gate. The comparator output serves as the active-LOW end-of-
conversion signal, EOC . If we assume that VA, the analog voltage to be
converted, is positive, the operation proceeds as follows :
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Clock
VA +
EOC
OP amp
-
Comparator START
VA
RESET
VAX
Conversion
complete.
VAX CLOCK counter stops
D/A .
Counter counting
converter
.
.
.
.
EOC
Digital
result tc
Start
Time
(a) (b)
Problem 8
Assume the following values for the ADC clock frequency = 1 MHz; VT
= 0.1 mV; DAC has F.S. output = 10.23 V and a 10-bit input. Determine
the following values.
Solution
a. The DAC has a 10-bit input and a 10.23-V F.S. output. Thus, the
number of total possible steps is 210 - 1 = 1023, and so the step size is
10.23V
= 10mV
1023
3.7281V
= 372.81 = 373 steps
10mV
At the end of the conversion, then, the counter will bold the binary
equivalent of 373, which is 0101110101. This is the desired digital
equivalent of VA = 3.728 V, as produced by this ADC.
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Problem 9
Solution
Table 7.2 shows the ideal DAC output voltage, VAX, for several of the
steps on and around the 373rd. If VA is slightly smaller than 3.72 V (by
an amount < VT),
Then EOC won’t go LOW when VAX reaches the 3.72-V step, but will
go LOW on the 3.73-V step. If VA is slightly smaller than 3.73 V (by an
amount < VT), then EOC won’t go LOW until VAX reaches the 3.74-V
step. Thus, as long as VA is between approximately 3.72 V and 3.73-V,
EOC will go LOW when VAX reaches the 3.73-V step. The exact range
of VA values is
3.72 V - VT to 3.73 V - VT
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Problem 10
Solution
The step size is 2.55 V/ (28 - 1), which is exactly 10 mV. This means that
even if the DAC has no inaccuracies, the VAX output could be off by as
much as 10 mV because VAX. can change only in 10-mV steps; this is the
quantization error. The specified error of 0.1% F.S. is 0.1% × 2.55 V =
2.55 mV. This means that the VAX value can be off by as much as 2.55
mV because of component inaccuracies. Thus, the total possible error
could be as much as 10 mV + 2.55 mV = 12.55 mV.
The conversion time is the time interval between the end of the START
pulse and the activation of the EOC output. The counter starts
counting from zero and counts up until VAX exceeds VA, at which point
Conversion Time, TC EOC goes LOW to end the conversion process. It should be clear that
the value of conversion time, to, depends on VA. A larger value will
require more steps before the staircase voltage exceeds VA.
The maximum conversion time will occur when VA is just below full
scale so that VAX has to go to the last step to activate EOC . For an N-bit
converter this will be
tc (max)
tc ( avg ) = ≈ 2 N − 1 clock cyles
2
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3.6. Applications
3.7. Exercise
i) 255
ii) 256
iii) 511
iv) 512.
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