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VHDL Code For Counter

This VHDL code defines an n-bit counter with a behavioral architecture. The counter uses a process sensitive to clock, count, and clear signals to increment or reset an internal signal Pre_Q on each clock edge if count is high. The Pre_Q signal is assigned concurrently to the output port Q.

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mnpaliwal020
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© Attribution Non-Commercial (BY-NC)
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366 views

VHDL Code For Counter

This VHDL code defines an n-bit counter with a behavioral architecture. The counter uses a process sensitive to clock, count, and clear signals to increment or reset an internal signal Pre_Q on each clock edge if count is high. The Pre_Q signal is assigned concurrently to the output port Q.

Uploaded by

mnpaliwal020
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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----------------------------------------------------

-- VHDL code for n-bit counter (ESD figure 2.6)


-- by Weijun Zhang, 04/2001
--
-- this is the behavior description of n-bit counter
-- another way can be used is FSM model.
----------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

----------------------------------------------------

entity counter is

generic(n: natural :=2);


port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;

----------------------------------------------------

architecture behv of counter is

signal Pre_Q: std_logic_vector(n-1 downto 0);

begin

-- behavior describe the counter

process(clock, count, clear)


begin
if clear = '1' then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;

-- concurrent assignment statement


Q <= Pre_Q;

end behv;

-----------------------------------------------------

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