Now you have a net list & constraints.

Next comes the physical design part of it; making your

design into a representation of the actual geometries you will manufacture. You will do a bunch
of stuff here, like

Floor planning,

Placement,

CTS,

Routing,

Timing closure,

Physical verification,

Formal verification etc.

The major stages are explained below

The FD-SOI innovation

Fully Depleted Silicon On Insulator, or FD-SOI, is a planar process technology that relies on two
primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top
of the base silicon.

Then, a very thin silicon film implements the transistor channel. Thanks to its thinness, there is no
need to dope the channel, thus making the transistor Fully Depleted.

The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted
SOI” or UTBB-FD-SOI.

By construction, FD-SOI enables much better transistor electrostatic characteristics versus

conventional bulk technology. The buried oxide layer lowers the parasitic capacitance between the
source and the drain. It also efficiently confines the electrons flowing from the source to the drain,
dramatically reducing performance-degrading leakage currents.
FD-SOI allows efficient transistor control
FD-SOI technology enables control of the behavior of transistors not only through the gate, but also
by polarizing the substrate underneath the device, similarly to the body bias available in Bulk
technology.

In bulk technology, body biasing is very limited, due to parasitic current leakage and inefficiency at
reduced transistor geometry.

Thanks to the transistor construction in FD-SOI and its ultra-thin insulator layer, biasing is much
more efficient. Also, the presence of the buried oxide allows the application of higher biasing
voltages, resulting in breakthrough dynamic control of the transistor

The FBB advantage

When polarization of the substrate is positive-- “Forward Body Biasing” or FBB-- the transistor can
be switched faster.

This provides an extremely powerful technique to optimize performance and power consumption.
Easy to implement, FBB can be modulated dynamically during the transistor operation, bringing a
great flexibility for designers and letting them design their circuits to be faster when required and
more energy efficient when performance isn’t as critical.
After 28/20 nm technology node the CMOS bulk technology is replaced by FDSOI &
FinFET.Recently there are few semiconductor companies which are using these technology.They
are Intel,Global foundaries,ST Microelectronics,samsung,IBM,TSMC.

In Older Technology,The leakage /Power consumption problems which are:

L1- Reverse bias p-n junction leakage.

L2- Sub threshold/Weak inversion current.

L3- Gate leakage,tunnneling through oxide

L4- Gate current due to HOT Carrier Injection.

L5- Gate induced drain leakage.

L6- Channel punch Through Carrier.

L1.L2 & L4 are present in both ON and OFF states.

The other limitation of the bulk planar transistor is:

Channel area underneath the gate is too deep and too much of the channel is too far away from the
gate to be well-controlled. The result is higher leakage power static or stand by power. Gate is never
truly turn OFF.

So that solution of these limitation is to make the channel thinner so that it is well controlled by the
gate. Possible solutions are: FinFET and FDSOI.

Fully Depleted Silicon On Insulator, or FD-SOI, is a planar process technology that relies on two
primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top
of the base silicon.

Then, a very thin silicon film implements the transistor channel. Thanks to its thinness, there is no
need to dope the channel, thus making the transistor Fully Depleted.

The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted
SOI” or UTBB-FD-SOI.

By construction, FD-SOI enables much better transistor electrostatic characteristics versus

conventional bulk technology. The buried oxide layer lowers the parasitic capacitance between the
source and the drain. It also efficiently confines the electrons flowing from the source to the drain,
dramatically reducing performance-degrading leakage currents.

FDSOI Advantage over Bulk CMOS:

Excellent electrostatic control of the channel

No channel doping required
Back bias ability if BOX is also thin
Excellent VT variability
Low DIBL (Drain Induced Barrier Lowering) – especially at low VDD
Limited Short Channel Effects
Very good Sub-threshold Slope
Minimum junction capacitance and diode leakage

FinFET is Fin(shaped) field effect transistor.It is non planar structure.It improve the
computational density over traditional design. As we know that in higher node technology that
mean in long channnel MOS ,there are some problem they are:

Threshold Voltage remains same

Subthreshold slope remains same

ON & OFF current increases with Drain v/g in same proportion.

And secondly in short channel MOSFET:

At very low voltage says vd =10mV, things are same as for long channel. Barrier height lowers with gate
v/g only.

But at for high vd=1V, barrier also lowers with the applied vd and this induces drain induced barrier
lowering (DIBL) effect.

It means barrier for electron to flow from source to drain is not only affected by gate v/g but also by drain
v/g .

So, if we summarize that we have mainly three short channel effect in MOSFETs:

DIBL

Subthreshold v/g changes

OFF current increases

Hence all these short channel effects are bad for the devices and circuits.Because all these effects are
lowering the gate control over current flow.

So,if we add more gate one above and on below or also put gate at the side also or put gate all around then
control over current flow can be increased.

So, here in the picture come of FinFET & FDSOI.

FinFET construction:
Transistor with 2-3 gates which are wrapped around a Silicon fin

Trigate has 3 gates [2 sidewall vertical gates and one planar/top gate]
A version of a Trigate finFET is Double-Gate FinFET with only the 2 sidewall vertical gates
with top gate being non-functional due to thicker gate oxide.

Channel width is quantized.

As with most prominent technology in FinFET is also classified in Bulk FinFETs and SOI
FinFETs:

When we operate FinFETs device like microprocessor at very high frequency, heat will generate
in this fins. Since Si is a decent conductor of heat and oxide has 100 times less thermal
conductivity .so bulk FinFET provide better heat dissipation.

In FinFETs device gate is wrapping around fins and controls the current effectively but in Bulk
FinFET source and drain are connected through Bulk Si underneath and form parasitic npn BJT
and some parasitic current can still flow underneath,which is not possible in case of SOI-FinFET.
This problem can be reduced in BULK FinFET by adding doping of bulk area, which helps in
removing parasitic BJT of Ioff but it adds process complexity.

Delay means a period of time by which something is late or postponed. So basically in VLSI
domain, delay is a function of (i/p transition time, logic net delay logic, pin delay).Delay and
their effect important role play in the VLSI domain.

So as design perspective Delays may be caused intentionally or unintentionally. During clock

tree synthesis, buffers may be added in the clock path so that the clock signal reaches all the
sequential elements at almost the same time which are intentionally delay and the other hand
unintentionally net delay i.e. wire delay which come due to the parasitic capacitances and
resistances in the SoC. Hence unintentionally delay could change the performances of the chip.

Gate Delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a
Gate takes a finite time to cause a change on the output. Cell delay is also same as gate delay.

Gate delay =function of ( i/p transition time, Cnet+Cpin).

Net Delay

The difference between the times a signal is first applied to the net and the time it reaches other
Devices connected to that net.
It is due to the finite resistance and capacitance of the net. It is also known as wire delay.
Wire delay =function (Rnet, Cnet+Cpin)
IR Drop is the voltage drop in the metal wires constituting the power grid before it reaches the
VDD pins of the standard cells.

Speed of standard cell is directly proportional to VDD.Hence vdd increases then speed of std.
cell is fast and propagation delay is lower.

V(static Drop)=I(avg)*R(wire)

V(dynamic)=L(di/dt)

Remove IR drop:

Split the long wire by placing appropriate power bumps

space the standard cells.

Latch-up is the generation of a low-impedance path in CMOS chips between the power supply
and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. These BJTs
for a silicon-controlled rectifier with positive feedback and virtually short circuit the power and
the ground rail. This causes excessive current flows and potential permanent damage to the
devices.

Prevention:

1. Adding a layer of insulating oxide (called a trench) that surrounds both the NMOS and
the PMOS transistors.
2. Latch-up Protection Technology circuit which shuts off the device when latchup is
detected.
3. A separate tap connection is put for each transistor
4. Reduce the gain product of the parasitic transistors