Microprocessor8085 Best
Microprocessor8085 Best
Arithmetic/Logic Unit: This is the area of the microprocessor where various computing
functions are performed on data. The ALU unit performs such arithmetic operations as
addition and subtraction, and such logic operations as AND, OR, and exclusive OR.
Register Array: This area of the microprocessor consists of various registers identified
by letters such as B, C, D, E, H, and L. These registers are primarily used to store data
temporarily during the execution of a program and are accessible to the user through
instructions.
Control Unit: The control unit provides the necessary timing and control signals to all
the operations in the microcomputer. It controls the flow of data between the
microprocessor and memory and peripherals.
Memory: Memory stores such binary information as instructions and data, and provides
that information to the microprocessor whenever necessary. To execute programs, the
microprocessor reads instructions and data from memory and performs the computing
operations in its ALU section. Results are either transferred to the output section for
display or stored in memory for later use. Read-Only memory (ROM) and Read/Write
memory (R/WM), popularly known as Random- Access memory (RAM).
1. The ROM is used to store programs that do not need alterations. The monitor
program of a single-board microcomputer is generally stored in the ROM. This
program interprets the information entered through a keyboard and provides
equivalent binary digits to the microprocessor. Programs stored in the ROM can
only be read; they cannot be altered.
2. The Read/Write memory (RIWM) is also known as user memory It is used to
store user programs and data. In single-board microcomputers, the monitor
program monitors the Hex keys and stores those instructions and data in the R/W
memory. The information stored in this memory can be easily read and altered.
I/O (Input/Output): It communicates with the outside world. I/O includes two types of
devices: input and output; these I/O devices are also known as peripherals.
System Bus: The system bus is a communication path between the microprocessor and
peripherals: it is nothing but a group of wires to carry bits.
Microprocessor is a multi-use device which finds applications in almost all the fields. Here is
some sample applications given in variety of fields.
Electronics:
Mechanical:
Automobiles
Lathes
All remote machines
Electrical:
Motors
Lighting controls
Power stations
Medical:
Patient monitoring
Most of the Medical equipments
Data loggers
Computer:
Domestic:
Microwave Ovens
Television/CD/DVD players
Washing Machines
Address Bus:
The data bus is a group of eight lines used for data flow.
These lines are bi-directional - data flow in both directions between the MPU and
memory and peripheral devices.
The MPU uses the data bus to perform the second function: transferring binary
information.
The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 =
256 numbers).
The largest number that can appear on the data bus is 11111111.
Control Bus:
The control bus carries synchronization signals and providing timing signals.
The MPU generates specific control signals for every operation it performs. These signals
are used to identify a device type with which the MPU wants to communicate.
Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data during program
execution.
These registers are identified as B, C, D, E, H, and L.
They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.
Accumulator (A):
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator.
Flags:
The ALU includes five flip-flops that are set or reset according to the result of an
operation.
The microprocessor uses the flags for testing the data conditions.
They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
The most commonly used flags are Sign, Zero, and Carry.
It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The function of the program counter is to point to the memory address of the next
instruction to be executed.
The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).
Temporary Register: It is used to hold the data during the arithmetic and logical operations.
Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.
Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.
It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.
ALE is used for provide control signal to synchronize the components of microprocessor
and timing for instruction to perform the operation.
RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data into memory respectively.
IO/M(Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.
If,
Interrupt Control Unit:
It receives hardware interrupt signals and sends an acknowledgement for receiving the
interrupt signal.
In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.
The microprocessor is in many ways similar to the CPU, but includes the logic circuitry,
including the control unit, on one chip.
The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
2. Address bus
3. Data bus
2. Address Bus:
5. Status Signals:
They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
There are five hardware interrupts called,
3 output states are high & low states and additionally a high impedance state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is
1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters
into a high impedance state.
Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.
For both high and low states, the output Q draws a current from the input of the OR gate.
When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does not
draw any current from the OR gate's input.
When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the
one that is communicating at a given instant.
The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and an
I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer
of data.
READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
TIMING DIAGRAM
Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called machine cycle.
T-State:
The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.
MACHINE CYCLES OF 8085:
The 8085 microprocessor has 5 (seven) basic machine cycles. They are
Each instruction of the 8085 processor consists of one to five machine cycles, i.e.,
when the 8085 processor executes an instruction, it will execute some of the machine
cycles in a specific order.
The processor takes a definite time to execute the machine cycles. The time taken by
the processor to execute a machine cycle is expressed in T-states.
One T-state is equal to the time period of the internal clock signal of the processor.
The memory read machine cycle is executed by the processor to read a data byte
from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine
cycle after the opcode fetch machine cycle.
The memory write machine cycle is executed by the processor to write a data byte in
a memory location.
The processor takes, 3T states to execute this machine cycle.
The I/O Read cycle is executed by the processor to read a data byte from I/O port or
from the peripheral, which is I/O, mapped in the system.
The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution.
The I/O write machine cycle is executed by the processor to write a data byte in the
I/O port or to a peripheral, which is I/O, mapped in the system.
The processor takes, 3T states to execute this machine cycle.
STA means Store Accumulator -The contents of the accumulator is stored in the
specified address(526A).
The opcode of the STA instruction is said to be 32H. It is fetched from the memory
41FFH(see fig). - OF machine cycle
Then the lower order memory address is read(6A). - Memory Read Machine Cycle
Read the higher order memory address (52).- Memory Read Machine Cycle
The combination of both the addresses are considered and the content from
accumulator is written in 526A. - Memory Write Machine Cycle
Assume the memory address for the instruction and let the content of accumulator
is C7H. So, C7H from accumulator is now stored in 526A.
Timing diagram for IN C0H.
Fetching the Opcode 34H from the memory 4105H. (OF cycle)
Let the memory address (M) be 4250H. (MR cycle -To read Memory address and
data)
Let the content of that memory is 12H.
Increment the memory content from 12H to 13H. (MW machine cycle)
Timing diagram for MVI B, 43H.
Fetching the Opcode 06H from the memory 2000H. (OF machine cycle)
Read (move) the data 43H from memory 2001H. (memory read)
INTERRUPT STRUCTURE
Types of Interrupts:
Software interrupts:
The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
Interrupt number * 8 = vector address
For RST 5,5 * 8 = 40 = 28H
Vector address for interrupt RST 5 is 0028H
If the interrupt is accepted then the processor executes an interrupt service routine.
(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR
TRAP:
This interrupt is a non-maskable interrupt. It is unaffected by any mask or
interrupt enable.
TRAP interrupt is edge and level triggered. This means hat the TRAP must go high
and remain high until it is acknowledged.
In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor
receives HOLD and TRAP at the same time then HOLD is recognized first and then
TRAP is recognized).
It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.
1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay
high until it recognized.
Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:
Enabled by EI instruction.
Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply
the address of ISR.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends
active low interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction
OPCODE on the data bus. In the case of multibyte instruction, additional interrupt
acknowledge machine cycles are generated by the 8085 to transfer the additional
bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on
stack and execute received instruction.
The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5
using SIM instruction.
The status of these interrupts can be read by executing RIM instruction.
The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be
performed by moving an 8-bit data to accumulator and then executing SIM
instruction.
The format of the 8-bit data is shown below.
The status of pending interrupts can be read from accumulator after executing RIM
instruction.
When RIM instruction is executed an 8-bit data is loaded in accumulator, which can
be interpreted as shown in fig.
8085 INSTRUCTION SET CLASSIFICATION
The 8085 instruction set can be classified into the following five functional headings.
It includes the instructions that move (copies) data between registers or between
memory locations and registers. In all data transfer operations the content of source
register is not altered. Hence the data transfer is copying operation.
2. ARITHMETIC INSTRUCTIONS:
3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR, EXCLUSIVE-
OR, complement, compare and rotate instructions are grouped under this heading. The
flag conditions are altered after execution of an instruction in this group.
4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one memory
location to another memory location are grouped under this heading.
It includes the instructions related to interrupts and the instruction used to stop the
program execution.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
1. Immediate Addressing:
In immediate addressing mode, the data is specified in the instruction itself. The
data will be a part of the program instruction.
EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI
SP, 2700H.
2. Direct Addressing:
In direct addressing mode, the address of the data is specified in the instruction. The
data will be in memory. In this addressing mode, the program instructions and data
can be stored in different memory.
EX. LDA 1050H - Load the data available in memory location 1050H in to
accumulator; SHLD 3000H
3. Register Addressing:
In register addressing mode, the instruction specifies the name of the register in
which the data is available.
EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.
In register indirect addressing mode, the instruction specifies the name of the
register in which the address of the data is available. Here the data will be in
memory and the address will be in the register pair.
EX. MOV A, M - The memory data addressed by H L pair is moved to A register.
LDAX B.
5. Implied Addressing:
In implied addressing mode, the instruction itself specifies the data to be operated.
EX. CMA - Complement the content of accumulator; RAL
8085 - Instruction set list
8085 Instructions - Datatransfer
Explanation of
Opcode Operand Description
Instruction
This instruction copies the contents of the source
Rd, Rs register into the destination register; the contents of the
Copy from source register are not altered. If one of the operands is
MOV M, Rs source(Rs) to a memory location, its location is specified by the
destination(Rd) contents of the HL registers.
Rd, M
Example: MOV B, C or MOV B, M
The 8-bit data is stored in the destination register or
memory. If the operand is a memory location, its
Rd, data
Move immediate 8- location is specified by the contents of the HL
MVI
bit registers.
M, data
Example: MVI B, 57H or MVI M, 57H
The contents of a memory location, specified by a 16-
bit address in the operand, are copied to the
16-bit
LDA Load accumulator accumulator. The contents of the source are not altered.
address
Example: LDA 2034H
The contents of the designated register pair point to a
memory location. This instruction copies the contents
of that memory location into the accumulator. The
B/D Reg. Load accumulator
LDAX contents of either the register pair or the memory
pair indirect
location are not altered.
Example: LDAX B
The instruction loads 16-bit data in the register pair
Reg. pair, Load register pair designated in the operand.
LXI
16-bit data immediate
Example: LXI H, 2034H or LXI H, XYZ
The instruction copies the contents of the memory
location pointed out by the 16-bit address into register
L and copies the contents of the next memory location
16-bit Load H and L
LHLD into register H. The contents of source memory
address registers direct
locations are not altered.
Example: STAX B
The contents of register L are stored into the memory
location specified by the 16-bit address in the operand
and the contents of H register are stored into the next
memory location by incrementing the operand. The
16-bit Store H and L contents of registers HL are not altered. This is a 3-
SHLD
address registers direct byte instruction, the second byte specifies the low-
order address and the third byte specifies the high-
order address.
Example: SPHL
The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
Exchange H and L
XTHL none exchanged with the next stack location (SP+1);
with top of stack
however, the contents of the stack pointer register are
not altered.
Example: XTHL
The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the highorder register (B, D, H, A)
Push register pair
PUSH Reg. pair are copied into that location. The stack pointer register
onto stack
is decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location.
Example: DAD H
The contents of the operand (register or memory ) are
subtracted from the contents of the accumulator, and the
result is stored in the accumulator. If the operand is a
R Subtract register
memory location, its location is specified by the contents
SUB or memory from
of the HL registers. All flags are modified to reflect the
M accumulator
result of the subtraction.
Example: DAA
Example: RET
Flag
Opcode Description
Status
RC Return on Carry CY = 1
Return on no The program sequence is
RNC CY = 0 transferred from the subroutine to
Carry
the calling program based on the
Return on specified flag of the PSW as
RP S=0
positive Return from described below. The two bytes
RM Return on minus S = 1 none subroutine from the top of the stack are copied
RZ Return on zero Z=1 conditionally into the program counter, and
program execution begins at the
Return on no new address.
RNZ Z=0
zero
Return on parity Example: RZ
RPE P=1
even
Return on parity
RPO P=0
odd
The contents of registers H and L
are copied into the program
counter. The contents of H are
Load program
placed as the high-order byte and
PCHL none counter with HL
the contents of L as the low-order
contents
byte.
Example: PCHL
The RST instruction is equivalent
to a 1-byte call instruction to one of
eight memory locations depending
upon the number. The instructions
are generally used in conjunction
with interrupts and inserted using
external hardware. However these
can be used as software instructions
in a program to transfer program
execution to one of the eight
locations. The addresses are:
Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST RST 4 0020H
0-7 Restart
RST 5 0028H
RST 6 0030H
RST 7 0038H
Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
LOGICAL INSTRUCTIONS
Explanation of
Opcode Operand Description
Instruction
The contents of the operand (register or memory) are M
compared with the contents of the accumulator. Both
contents are preserved . The result of the comparison is
shown by setting the flags of the PSW as follows:
R Compare register
CMP or memory with
if (A) < (reg/mem): carry flag is set
M accumulator
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: RLC
Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
Rotate the Carry flag. CY is modified according to bit D0. S, Z, P,
RRC none
accumulator right AC are not affected.
Example: RRC
Each binary bit of the accumulator is rotated left by one
position through the Carry flag. Bit D7 is placed in the
Rotate Carry flag, and the Carry flag is placed in the least
RAL none accumulator left significant position D0. CY is modified according to bit
through carry D7. S, Z, P, AC are not affected.
Example: RAL
Rotate Each binary bit of the accumulator is rotated right by one
RAR none
accumulator right position through the Carry flag. Bit D0 is placed in the
through carry Carry flag, and the Carry flag is placed in the most
significant position D7. CY is modified according to bit
D0. S, Z, P, AC are not affected.
Example: RAR
The contents of the accumulator are complemented. No
Complement flags are affected.
CMA none
accumulator
Example: CMA
The Carry flag is complemented. No other flags are
Complement affected.
CMC none
carry
Example: CMC
Set Carry
STC none Set Carry
Example: STC
CONTROL INSTRUCTIONS
Explanation
Opcode Operand of Description
Instruction
No operation is performed. The instruction is fetched and decoded.
No However no operation is executed.
NOP none
operation
Example: NOP
The CPU finishes executing the current instruction and halts any further
Halt and
execution. An interrupt or reset is necessary to exit from the halt state.
HLT none enter wait
state
Example: HLT
The interrupt enable flip-flop is reset and all the interrupts except the
Disable TRAP are disabled. No flags are affected.
DI none
interrupts
Example: DI
The interrupt enable flip-flop is set and all interrupts are enabled. No flags
are affected. After a system reset or the acknowledgement of an interrupt,
the interrupt enable flipflop is reset, thus disabling the interrupts. This
Enable
EI none instruction is
interrupts
necessary to reenable the interrupts (except TRAP).
Example: EI
This is a multipurpose instruction used to read the status of interrupts 7.5,
6.5, 5.5 and read serial data input bit. The instruction loads eight bits in
the accumulator with the following interpretations.
Example: RIM
Read
RIM none interrupt
mas
Example: SIM
Set interrupt
SIM none
mask
Opcode Sheet of 8085 Microprocessor with
description
What is OPCODE? OPCODE is the machine language. ie, while we talk or write, we do it in english;
because we understand english. But a machine cannot understand direct english. So, we translate english
into its level to make a machine to understand. For example, there is a translator inside all computers
which translate our english into Binary language for a computer to understand and perform the required
operations. Similarly, a machine language which a Microprocessor can understand is the HEXA language.
These hex codes are called OPCODES which makes a microprocessor to work. As there is no translator
inside a Microprocessor, we directly fnd the OPCODES for each and every instruction and we feed it
alone inside a trainer kit. Those opcodes with its description are given below. The OPCODE sheet
without description is also given in the main page.
Calculate the sum of series of numbers
Multiply two 8-bit numbers
Divide a 16 bit number by a 8-bit number
Find the negative numbers in a block of data.
Find the largest of given numbers
Count number of one's in a number
Arrange in ascending order
Calculate the sum of series of even numbers
Calculate the sum of series of odd numbers
Find the square of given number
Search a byte in a given number
Add two decimal numbers of 6 digit each
Add each element of array with the elements of another array
Separate even numbers from given numbers
Transfer contents to overlapping memory blocks
Add parity bit to 7-bit ASCII characters
Find the number of negative, zero and positive numbers
Inserting string in a given array of characters
Deleting string in a given array of characters
Multiply two eight bit numbers with shift and add method
Divide 16-bit number with 8-bit number using shifting technique
Sub routine to perform the task of DAA
Program to test RAM
Program to generate Fibonacci number
Generate a delay of 0.4 seconds
Arrange in Descending Order
Data transfer from one memory block to other memory block.
Find the factorial of a number
Find the Square Root of a given number
Split a HEX data into two nibbles and store it
Add two 4-digit BCD numbers
Subtraction of two BCD numbers
Multiply two 2-digit BCD numbers
Generate and display binary up counter
Generate and display BCD up counter with frequency 1Hz
Generate and display BCD down counter
Generate and display the contents of decimal counter
Debug the delay routine
2-Digit BCD to binary conversion.
Binary to BCD conversion
Find the 7-segment codes for given numbers
Find the ASCII character
ASCII to Decimal Conversion
HEX to Decimal conversion
HEX to binary conversion
Store 8-bit data in memory
Statement: Store the data byte 32H into memory location 4000H.
Program 1:
Program 2:
Note: The result of both programs will be the same. In program 1 direct addressing
instruction is used, whereas in program 2 indirect addressing instruction is used.
Program 1:
LDA 2000H : Get the contents of memory location 2000H into accumulator
Statement: Add the contents of memory locations 4000H and 4001H and place the result in
memory location 4002H.
Sample problem
(4000H) = 14H
(4001H) = 89H
Source program
Flowchart
Statement: Add the 16-bit number in memory locations 4000H and 4001H to the 16-bit
number in memory locations 4002H and 4003H. The most significant eight bits of the two
numbers to be added are in memory locations 4001H and 4003H. Store the result in
memory locations 4004H and 4005H with the most significant byte in memory location
4005H.
Sample problem:
(4000H) = 15H
(4001H) = 1CH
(4002H) = B7H
(4003H) = 5AH
(4004H) = CCH
(4005H) = 76H
Source Program 1:
SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H.
Flowchart
Program - 5b: Add two 16-bit numbers - Source Program 2
Source program 2:
SHLD 4004H : Store I6-bit result in memory locations 4004H and 4005H.
NOTE: In program 1, eight bit addition instructions are used (ADD and ADC) and addition is
performed in two steps. First lower byte addition using ADD instruction and then higher byte
addition using ADC instruction.In program 2, 16-bit addition instruction (DAD) is used.
Statement: Subtract the contents of memory location 4001H from the memory location
2000H and place the result in memory location 4002H.
Sample problem:
(4000H) = 51H
(4001H) = 19H
Source program:
Flowchart
Statement: Add the contents of memory locations 40001H and 4001H and place the result
in the memory locations 4002Hand 4003H.
Sample problem:
(4000H) = 7FH
(400lH) = 89H
(4002H) = 08H
(4003H) = 0lH
Source program:
Flowchart
Statement: Subtract the 16-bit number in memory locations 4002H and 4003H from the
16-bit number in memory locations 4000H and 4001H. The most significant eight bits of the
two numbers are in memory locations 4001H and 4003H. Store the result in memory
locations 4004H and 4005H with the most significant byte in memory location 4005H.
Sample problem:
(4000H) = 19H
(400IH) = 6AH
(4004H) = 04H
(4005H) = OEH
Source program:
SHLD 4004H : Store l6-bit result in memory locations 4004H and 4005H.
Flowchart
Statement: Find the l's complement of the number stored at memory location 4400H and
store the complemented number at memory location 4300H.
Sample problem:
(4400H) = 55H
Source program:
Statement: Find the 2's complement of the number stored at memory location 4200H and
store the complemented number at memory location 4300H.
Sample problem:
(4200H) = 55H
Source program:
Flowchart
Statement: Pack the two unpacked BCD numbers stored in memory locations 4200H and 4201H
and store result in memory location 4300H. Assume the least significant digit is stored at 4200H.
Sample problem:
(4200H) = 04
(4201H) = 09
Result = (4300H) = 94
Source program:
Flowchart
Statement: Two digit BCD number is stored in memory location 4200H. Unpack the BCD
number and store the two digits in memory locations 4300H and 4301H such that memory
location 4300H will have lower BCD digit.
Sample problem:
(4200H) = 58
(4301H) = 05
Source program:
RRC
RRC
RRC
Flowchart
Statement: Read the program given below and state the contents of all registers after the
execution of each instruction in sequence.
Main program:
400CH HLT
Subroutine program:
4101H PUSH H
4109H DAD B
410CH POP H
410DH POP B
410EH RET
Note:
The table given gives the instruction sequence and the contents of all registers and stack
after execution of each instruction.
TABLE
Statement: Write a program to shift an eight bit data four bits right. Assume data is in
register C.
Sample problem:
(4200H) = 58
(4301H) = 05
Statement: Program to shift a 16-bit data 1 bit left. Assume data is in the HL register
Source Program
Statement: Write a set of instructions to alter the contents of flag register in 8085.
PUSH PSW: Save flags on stack
POP H: Retrieve flags in 'L'
MOV A, L :Flags in accumulator
CMA:Complement accumulator
MOV L, A:Accumulator in 'L'
PUSH H:Save on stack
POP PSW:Back to flag register
HLT:Terminate program execution
Statement: Calculate the sum of series of numbers. The length of the series is in memory
location 4200H and the series begins from memory location 4201H.
a. Consider the sum to be 8 bit number. So, ignore carries. Store the sum at memory
location 4300H.
b. Consider the sum to be 16 bit number. Store the sum at memory locations 4300H and
4301H.
Sample problem 1:
4200H = 04H
4201H = 10H
4202H = 45H
4203H = 33H
4204H = 22H
Result = 10 +41 + 30 + 12 = H
4300H = H
LDA 4200H
SUB A : sum = 0
Sample problem 2:
4200H = 04H
420lH = 9AH
4202H = 52H
4203H = 89H
4204H = 3EH
Source program 2
LDA 4200H
JNC SKIP
MOV A, B
Statement: Multiply two 8-bit numbers stored in memory locations 2200H and 2201H by
repetitive addition and store the result in memory locations 2300H and 2301H.
Sample problem 1:
(2200H) = 03H
(2201H) = B2H
= 216H
(2300H) = 16H
(2301H) = 02H
LDA 2200H
MOV E, A
MVI D, 00 : Get the first number in DE
register pair
LDA 2201H
MOV C, A : Initialize counter
LX I H, 0000 H : Result = 0
BACK: DAD D : Result = result + first
number
DCR C : Decrement count
JNZ BACK : If count 0 repeat
SHLD 2300H : Store result
HLT : Terminate program execution
Statement: Divide 16 bit number stored in memory locations 2200H and 2201H by the 8 bit
number stored at memory location 2202H. Store the quotient in memory locations 2300H and
2301H and remainder in memory locations 2302H and 2303H.
Sample problem 1:
(2200H) = 60H
(2201H) = A0H
(2202H) = l2H
(2300H) = E8H
(2301H) = 08H
(2302H= 10H
(2303H) 00H
Statement: Find the number of negative elements (most significant bit 1) in a block of data. The
length of the block is in memory location 2200H and the block itself begins in memory location
2201H. Store the number of negative elements in memory location 2300H
Sample problem 1:
(2200H) = 04H
(2201H) = 56H
(2202H) = A9H
(2203H) = 73H
(2204H) = 82H
Statement: Find the largest number in a block of data. The length of the block is in
memory location 2200H and the block itself starts from memory location 2201H.Store the
maximum number in memory location 2300H. Assume that the numbers in the block are
all 8 bit unsigned binary numbers.
Sample problem 1:
(2200H) = 04
(2201H) = 34H
(2202H) = A9H
(2203H) = 78H
(2204H) =56H
Result = (2202H) = A9H
LDA 2200H
MOV C, A : Initialize counter
XRA A : Maximum = Minimum possible
value = 0
LXI H, 2201H : Initialize pointer
BACK: CMP M : Is number> maximum
JNC SKIP : Yes, replace maximum
MOV A, M
SKIP: INX H
DCR C
JNZ BACK
STA 2300H : Store maximum number
HLT : Terminate program execution
Statement: Write a program to count number of l's in the contents of D register and store the
count in the B register.
Sample problem 1:
(2200H) = 04
(2201H) = 34H
(2202H) = A9H
(2203H) = 78H
(2204H) =56H
MVI B, 00H
MVI C, 08H
MOV A, D
BACK: RAR
JNC SKIP
INR B
SKIP: DCR C
JNZ BACK
HLT
Statement: Write a program to sort given 10 numbers from memory location 2200H in the
ascending order.
Source program :
Statement: Calculate the sum of series of even numbers from the list of numbers. The
length of the list is in memory location 2200H and the series itself begins from memory
location 2201H. Assume the sum to be 8 bit number so you can ignore carries and store the
sum at memory location 2210H.
Sample problem 1:
2200H= 4H
2201H= 20H
2202H= l5H
2203H= l3H
2204H= 22H
LDA 2200H
MOV C, A : Initialize counter
MVI B, 00H : sum = 0
LXI H, 2201H : Initialize pointer
BACK: MOV A, M : Get the number
ANI 0lH : Mask Bit l to Bit7
JNZ SKIP : Don't add if number is
ODD
MOV A, B : Get the sum
ADD M : SUM = SUM + data
MOV B, A : Store result in B register
SKIP: INX H : increment pointer
DCR C : Decrement counter
JNZ BACK : if counter 0 repeat
STA 2210H : store sum
HLT : Terminate program execution
Statement: Calculate the sum of series of odd numbers from the list of numbers. The
length of the list is in memory location 2200H and the series itself begins from memory
location 2201H. Assume the sum to be 16-bit. Store the sum at memory locations 2300H
and 2301H.
Sample problem 1:
2200H = 4H
2201H= 9AH
2202H= 52H
2203H= 89H
2204H= 3FH
LDA 2200H
MOV C, A : Initialize counter
LXI H, 2201H : Initialize pointer
MVI E, 00 : Sum low = 0
MOV D, E : Sum high = 0
BACK: MOV A, M : Get the number
ANI 0lH : Mask Bit 1 to Bit7
JZ SKIP : Don't add if number is
even
MOV A, E : Get the lower byte of sum
ADD M : Sum = sum + data
MOV E, A : Store result in E register
JNC SKIP
INR D : Add carry to MSB of SUM
SKIP: INX H : Increment pointer
Statement: Find the square of the given numbers from memory location 6100H and store
the result from memory location 7000H.
Sample problem 1:
2200H = 4H
2201H= 9AH
2202H= 52H
2203H= 89H
2204H= 3FH
Source program :
Statement: Search the given byte in the list of 50 numbers stored in the consecutive
memory locations and store the address of memory location in the memory locations 2200H
and 2201H. Assume byte is in the C register and starting address of the list is 2000H. If
byte is not found store 00 at 2200H and 2201H.
Source program :
Statement: Two decimal numbers six digits each, are stored in BCD package form. Each
number occupies a sequence of byte in the memory. The starting address of first number is
6000H Write an assembly language program that adds these two numbers and stores the
sum in the same format starting from memory location 6200H.
Source program :
Statement: Two decimal numbers six digits each, are stored in BCD package form. Each
number occupies a sequence of byte in the memory. The starting address of first number is
6000H Write an assembly language program that adds these two numbers and stores the
sum in the same format starting from memory location 6200H.
Source program :
Statement: Write an assembly language program to separate even numbers from the given
list of 50 numbers and store them in the another list starting from 2300H. Assume starting
address of 50 number list is 2200H.
Source program :
Statement: Write assembly language program with proper comments for the following:
A block of data consisting of 256 bytes is stored in memory starting at 3000H. This block is
to be shifted (relocated) in memory from 3050H onwards. Do not shift the block or part of
the block anywhere else in the memory.
Two blocks (3000 - 30FF and 3050 - 314F) are overlapping. Therefore it is necessary to
transfer last byte first and first byte last.
Source Program:
Statement: Add even parity to a string of 7-bit ASCII characters. The length of the string
is in memory location 2040H and the string itself begins in memory location 2041H. Place
even parity in the most significant bit of each character.
Source program :
LXI H, 2040H
MOV C ,M : Counter for character
REPEAT:INX H : Memory pointer to character
MOV A,M : Character in accumulator
ORA A : ORing with itself to check parity.
JPO PAREVEN : If odd parity place
ORI 80H even parity in D7 (80).
PAREVEN:MOV M , A : Store converted even parity character.
DCR C : Decrement counter.
JNZ REPEAT : If not zero go for next character.
HLT : Terminate program execution
Source program :
Statement: Write an 8085 assembly language program to insert a string of four characters
from the tenth location in the given array of 50 characters.
Solution:
Step 1: Move bytes from location 10 till the end of array by four bytes downwards.
Step 2: Insert four bytes at locations 10, 11, 12 and 13.
Source program :
Solution:
Shift bytes from location 14 till the end of array upwards by 4 characters i.e. from location 10
onwards.
Source program :
LXI H, 2l0DH :Initialize source memory pointer at the 14thlocation of the array.
LXI D, 2l09H : Initialize destination memory pointer at the 10th location of the array.
MOV A, M : Get the character
STAX D : Store character at new location
INX D : Increment destination pointer
INX H : Increment source pointer
MOV A, L : [check whether desired
CPI 32H bytes are shifted or not]
JNZ REPE : if not repeat the process
HLT : stop
Statement: Multiply the 8-bit unsigned number in memory location 2200H by the 8-bit
unsigned number in memory location 2201H. Store the 8 least significant bits of the result
in memory location 2300H and the 8 most significant bits in memory location 2301H.
Sample problem:
Result = 12 x 5 = (6010)
Statement: Divide the 16-bit unsigned number in memory locations 2200H and 2201H
(most significant bits in 2201H) by the B-bit unsigned number in memory location 2300H
store the quotient in memory location 2400H and remainder in 2401H.
Assumption: The most significant bits of both the divisor and dividend are zero.
Source program : Flowchart for program
MVI E, 00 : Quotient = 0
LHLD 2200H : Get dividend
LDA 2300 : Get divisor
MOV B, A : Store divisor
MVI C, 08 : Count = 8
NEXT: DAD H : Dividend = Dividend x 2
MOV A, E
RLC
MOV E, A : Quotient = Quotient x 2
MOV A, H
SUB B : Is most significant byte of Dividend > divisor
JC SKIP : No, go to Next step
MOV H, A : Yes, subtract divisor
INR E : and Quotient = Quotient + 1
SKIP:DCR C : Count = Count - 1
JNZ NEXT : Is count =0 repeat
MOV A, E
STA 2401H : Store Quotient
Mov A, H
STA 2410H : Store remainder
HLT : End of program.
Statement: Assume the DAA instruction is not present. Write a sub routine which will
perform the same task as DAA.
Sample Problem:
1. If the value of the low order four bits (03-00) in the accumulator is greater than 9 or if
auxiliary carry flag is set, the instruction adds 6 '(06) to the low-order four bits.
2. If the value of the high-order four bits (07-04) in the accumulator is greater than 9 or if
carry flag is set, the instruction adds 6(06) to the high-order four bits.
Statement: To test RAM by writing '1' and reading it back and later writing '0' (zero) and
reading it back. RAM addresses to be checked are 40FFH to 40FFH. In case of any error, it
is indicated by writing 01H at port 10H.
Source program :
Source program :
Statement: Write a program to generate a delay of 0.4 sec if the crystal frequency is 5
MHz.
Source program :
START:MVI B, 00 ; Flag = 0
LXI H, 4150 ; Count = length of array
MOV C, M
DCR C ; No. of pair = count -1
INX H ; Point to start of array
LOOP:MOV A, M ; Get kth element
INX H
CMP M ; Compare to (K+1) th element
JNC LOOP 1 ; No interchange if kth >= (k+1) th
MOV D, M ; Interchange if out of order
MOV M, A ;
DCR H
MOV M, D
INX H
MVI B, 01H ; Flag=1
LOOP 1:DCR C ; count down
JNZ LOOP ;
DCR B ; is flag = 1?
JZ START ; do another sort, if yes
HLT ; If flag = 0, step execution
Statement: Transfer ten bytes of data from one memory to another memory block. Source
memory block starts from memory location 2200H where as destination memory block
starts from memory location 2300H.
Source program :
Subroutine Program:
FACTO:LXI H, 0000H
MOV B, C ; Load counter
BACK: DAD D
DCR B
JNZ BACK ; Multiply by successive addition
XCHG ; Store result in DE
DCR C ; Decrement counter
CNZ FACTO ; Call subroutine FACTO
RET ; Return to main program
Subroutine Program:
Note: The square root can be taken by an iterative technique. First, an initial value is
assumed. Here, the initial value of square root is taken as half the value of given number.
The new value of square root is computed by using an expression XNEW = (X + Y/X)/2
where, X is the initial value of square root and Y is the given number. Then, XNEW is
compared with initial value. If they are not equal then the above process is repeated until X
is equal to XNEW after taking XNEW as initial value. (i.e., X ←XNEW)
Statement: Write a simple program to Split a HEX data into two nibbles and store it in
memory
Source program :
Sample Problem:
(HL) =3629
(DE) =4738
:.add 06
61 + 06 = 67
7D + 06 = 83
Result = 8367
Source program :
Source Program:
MVI A,99H
The 10's complement of a decimal number is equal to the 99's complement plus 1. The 99's
complement of a number can be found by subtracting the number from 99.
Source Program:
Statement:
Write a program for displaying binary up counter. Counter should count numbers from 00
to FFH and it should increment after every 0.5 sec.Assume operating frequency of 8085
equal to 2MHz. Display routine is available.
Source program:
Delay Routine:
Source program:
Delay Routine:
Source program 1:
Source Program 2:
Statement: Write assembly language program to with proper comments for the following:
To display decimal decrementing counter (99 to 00) at port 05 H with delay of half seconds
between .each count. Write as well the delay routine giving delay of half seconds. Operating
frequency of microprocessor is 3.072 MHz. Neglect delay for the main program.
Source Program:
MVI C, 99H : Initialize counter
BACK: MOV A, C
ANI OF : Mask higher nibble
CPI OF
JNZ SKIP
MOV A, C
SUI 06 : Subtract 6 to adjust decimal count
MOV D, A
SKIP: MOV A, C
OUT 05 : send count on output port
CALL Delay : Wait for 0.5 seconds
DCR C : decrement count
MOV A, C
CPI FF
JNZ BACK : If not zero, repeat
HLT : Stop execution
Delay subroutine:
Statement:The delay routine given below is in infinite loop, identify the error and correct the
program.
Sol.: 1) The fault in the above program is at instruction JNZ L1. This condition always
evaluates to be true hence loops keep on executing and hence infinite loop.
2) Reason for infinite looping: - The instruction DCX H decrease the HL pair count one by
one but it does not affect the zero flag. So when count reaches to OOOOH in HL pair zero flag
is not affected and JNZ L1 evaluates to be true and loop continues. Now HL again decrements
below OOOOH and HL becomes FFFFH and thus execution continues.
Statement: Convert a 2-digit BCD number stored at memory address 2200H into its
binary equivalent number and store the result in a memory location 2300H.
Sample problem 1:
(2200H) = 67H
Statement: Convert a 2-digit BCD number stored at memory address 2200H into its
binary equivalent number and store the result in a memory location 2300H.
Sample problem 1:
(2200H) = 67H
Statement: Write a main program and a conversion subroutine to convert the binary
number stored at 6000H into its equivalent BCD number. Store the result from memory
location 6100H.
Sample problem :
(6000) H = 8AH
Statement: Write an assembly language program to convert the contents of the five
memory locations starting from 2000H into an ASCII character. Place the result in another
five memory locations starting from 2200H.
Sample Problem
(2000H) = 1
(2001H) = 2
(2002H) = 9
(2003H) = A
(2004H) = B
Result:(2200H) = 31
(2201H) = 32
(2202H) = 39
(2203H) = 41
(2204H) = 42
Source program:
Subroutine:
Note: The ASCII Code (American Standard Code for Information Interchange) is
commonly used for communication. In such cases we need to convert binary number to its
ASCII equivalent. It is a seven bit code. In this code number 0 through 9 are represented as
30 through 39 respectively and letters A through Z are represented as 41H through 5AH.
Therefore, by adding 30H we can convert number into its ASCII equivalent and by adding
37H we can convert letter to its ASCII equivalent.
Statement: Convert the ASCII number in memory to its equivalent decimal number
Source program :
Note: The ASCII Code (American Standard Code for Information Interchange) is
commonly used for communication. It is a seven bit code. In this code number 0 through 9
are represented as 30 through 39 respectively and letters A through Z are represented as
41H through 5AH. Therefore, by subtracting 30H we can convert an ASCII number into its
decimal equivalent.
Statement: Convert the HEX number in memory to its equivalent decimal number
Source program :
Converting A9 we get:
A9 /64=45 Hundreds = 01
Since 64(100 decimal) cannot be subtracted from 45 no. of hundreds = 01. Now count tens
45/0A=3B Tens = 01 Now from 09, 0A cannot be subtracted. Hence tens = 06 the decimal
equivalent of A9 is 169.
Source Program:
Statement: Write a program to output contents of B register LSB to MSB on the SOD pin.
Source program :
Delay subroutine:
Source program :
Delay subroutine:
Source program :
Delay subroutine:
Solution Description:
INTERFACING DIAGRAM
Statement:Write a assembly program to receive 25 bytes from an CRT terminal to 8085
for the following requirements.
i) Baud rate x 16
Status Word:
Note: Reading of status word is necessary for checking the status of RxD line of 8085 that
whether receiver is ready to give data or not.
Sample 1:
Solution:
Source Program 1:
Sample 2:
Source Program 2:
Delay subroutine:
Delay: LXI D, Count
Back: DCX D
MOV A, D
ORA E
JNZ Back
RET
Statement: Design a system (both Software and Hardware) that will cause 4 LEDs to flash
10 times when a push button switch is pressed. Use 8255. Assume persistence of vision to be
0.1 seconds.
Source Program 1:
INTERFACING SCHEME
Statement: Design a microprocessor system to control traffic lights. The traffic light
arrangement is as shown in Fig. The traffic should be controlled in the following manner.
1) Allow traffic from W to E and E to W transition for 20 seconds. 2) Give transition period
of 5 seconds (Yellow bulbs ON) 3) Allow traffic from N to 5 and 5 to N for 20 seconds 4)
Give transition period of 5 seconds (Yellow bulbs ON) 5) Repeat the process.
The electric bulbs are controlled by relays. The 8255 pins are used to control relay on-off
action with the help of relay driver circuits. The driver circuit includes 12 transistors to
drive 12 relays. Fig. also shows the interfacing of 8255 to the system.
INTERFACING DIAGRAM
SOFTWARE FOR TRAFFIC LIGHT CONTROL
Source Program 1:
Delay Subroutine:
Statement: Interface a Stepper Motor to the 8085 microprocessor system and write an
8085 assembly language program to control the Stepper Motor.
A stepper motor is a digital motor. It can be driven by digital signal. Fig. shows the typical
2 phase motor rated 12V /0.67 A/ph interfaced with the 8085 microprocessor system using
8255. Motor shown in the circuit has two phases, with center-tap winding. The center taps
of these windings are connected to the 12V supply. Due to this, motor can be excited by
grounding four terminals of the two windings. Motor can be rotated in steps by giving
proper excitation sequence to these windings. The lower nibble of port A of the 8255 is used
to generate excitation signals in the proper sequence. These excitation signals are buffered
using driver transistors. The transistors are selected such that they can source rated
current for the windings. Motor is rotated by 1.80 per excitation.
Fig. shows the interfacing diagram to control 12 electric bulbs. Port A is used to control
lights on N-S road and Port B is used to control lights on W-E road. Actual pin connections
are listed in Table 1 below.
SOFTWARE FOR STEPPER MOTOR CONTROL
6000H Excite code DB 03H, 06H, 09H, OCH : This is the code sequence for clockwise rotation
Delay Subroutine:
FLOWCHARTS
Statement: Interface a 64-key matrix keyboard to the 8085 microprocessor using 8255.
Write an 8085 assembly language program to initialize 8255 and to read the key code.
INTERFACING SCHEME
Delay Subroutine:
Statement: Interface an 8-digit 7 segment LED display using 8255 to the 8085
microprocessor system and write an 8085 assembly language routine to display message on
the display.
HARDWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY
INTERFACE
Fig. shows the multiplexed eight 7-segment display connected in the 8085 system using
8255. In this circuit port A and port B are used as simple latched output ports. Port A
provides the segment data inputs to the display and port B provides a means of selecting a
display position at a time for multiplexing the displays. A0-A7 lines are used to decode the
addresses for 8255. For this circuit different addresses are:
PA = 00H PB = 01H
PC = 02H CR = 03H.
The register values are chosen in Fig. such that the segment current is 80 mA. This current
is required to produce an average of 10 mA per segment as the displays are multiplexed. In
this type of display system, only one of the eight display position is 'ON' at any given
instant. Only one digit is selected at a time by giving low signal on the corresponding
control line. Maximum anode current is 560 mA (7-segments x 80 mA = 560 mA), but the
average anode current is 70 mA.
INTERFACING SCHEME
SOFTWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY
For 8255, Port A and B are used as output ports. The control word format of 8255
according to hardware connections is:
Source program:
DISPLAY MESSAGE:
Note: This "display message subroutine" must be called continuously to display the 7-segment
coded message stored in the memory from address 6000H.
Delay Subroutine:
Fig. shows the interfacing of 8 x 8 matrix keyboard in interrupt driven keyboard mode. In
the interrupt driven mode interrupt line from 8279 is connected to the one of the interrupt
input of 8085 except INTR. Here, INT line from 8279 is connected to the interrupt RST 7.5
of 8085. Other signal connections are same as in the non interrupt mode.
SOFTWARE FOR 8 x 8 MATRIX KEYBOARD INTERFACE
Interrupt Subroutine:
Fig. shows the interfacing of 8 x 8 matrix keyboard in interrupt driven keyboard mode. In
the interrupt driven mode interrupt line from 8279 is connected to the one of the interrupt
input of 8085 except INTR. Here, INT line from 8279 is connected to the interrupt RST 7.5
of 8085. Other signal connections are same as in the non interrupt mode.
NOTE: As keyboard is having 8
rows and 4 columns, only 4 scan lines are required and we can avoid external decoder to
generate scan lines by selecting decoded scan keyboard mode.
Source program:
Interrupt Subroutine:
Fig. shows the interfacing of eight 7-segment digits to 8085 through 8279. As shown in the
figure eight display lines (Bo-B3 and Ao-A3) are buffered with the help of transistor and
used to drive display digits. These buffered lines are connected in parallel to all display
digits. So, Sl and S2 lines are decoded and decoded lines are used for selection of one of the
eight digits.
To display 1 to 8 numbers on the eight 7-segment digits we have to load 7-segment codes
for 1 to 8 numbers in the corresponding display locations.
The three steps needed to
write the software are:
Statement: Interface 4 x 4 matrix keyboard and 4 digit 7-segment display and write an
tssembly language program to read keycode of the pressed key and display same key on the
7 segment display.
Fig. shows interfacing diagram. Here, 4 scan lines are sufficient to scan matrix keyboard
and to select display digits. Hence decoded mode is used.
SOFTWARE FOR 4x4 MATRIX KEYBOARD & 4 DIGIT 7 SEGMENT
DISPLAY INTERFACE
To display 1 to 8 numbers on the eight 7-segment digits we have to load 7-segment codes
for 1 to 8 numbers in the corresponding display locations.
To roll the above message we have to load 7-segment codes for characters within the
message and it is necessary to configure 8279 in right entry mode
Step 1: Find keyboard/display command word.
Statement: Write an assembly language program to roll a name – 'J.BINU' from right to
left
To roll the above message we have to load 7-segment codes for characters within the
message and it is necessary to configure 8279 in right entry mode