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CMOS Solution

The document provides solutions to drawing minimum CMOS transistor networks that implement various Boolean equations. For each equation provided, a schematic diagram is drawn showing the connections between transistors to represent the logic. The equations range in complexity from a single OR gate to combinations of AND, OR, and NOT gates. Transistor networks are designed to directly map the logic structures implied by the Boolean expressions.

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Mahmoud Salama
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0% found this document useful (0 votes)
336 views

CMOS Solution

The document provides solutions to drawing minimum CMOS transistor networks that implement various Boolean equations. For each equation provided, a schematic diagram is drawn showing the connections between transistors to represent the logic. The equations range in complexity from a single OR gate to combinations of AND, OR, and NOT gates. Transistor networks are designed to directly map the logic structures implied by the Boolean expressions.

Uploaded by

Mahmoud Salama
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CMOS Logic Design Solution

1. Please draw the minimum CMOS transistor network that implements the functionality of Boolean equation
F= ((A+B) C + D)'. You can assume both the original and complemented versions of each literal are available
as gate inputs.

B
C
A

D
F

A B

D
C

2. Please draw the minimum CMOS transistor network that implements the functionality of Boolean equation
F= (A (B C + D))'. You can assume both the original and complemented versions of each literal are available as
gate inputs.

D
A
B C

B
D
C

A
3. Please draw the minimum CMOS transistor network that implements the functionality of Boolean equation
F= (A +(B' + CD)')'. You can assume both the original and complemented versions of each literal are available
as gate inputs.

F= (A +(B' + CD)')' = (A + B(CD)')' = (A + B (C' + D'))'

C
B
D

A
F

C D

A
B

4. Please draw the minimum CMOS transistor network that implements the functionality of Boolean equation
F= (A' + B'C). You can assume both the original and complemented versions of each literal are available as
gate inputs.

F = (A' + B'C) = ((A' + B'C)')'= (A (B'C)')' = (A (B + C'))'

C
A
B

B C

A
5. F= [((CD) +B) A]'

6. F=(AB)' since F= [AB(A+B)]' on simplification results in F=(AB)'

7. F= ((C'+D')B)+A

8. F= (A+D+C)(B+E)

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