MAHARASHTRA INSTITUE OF TECHNOLOGY PUNE

Certificate
This is to certify that
1. 31057
2. 30069
3. 30037

Studying in year T.E. branch E&TC have satisfactorily

completed the project work of SERIAL DATA RECEPTION USING
VHDL topic in fulfillment of mini project in Electronic System
Design & Mini Project during the academic year 2009-10.

Acknowledgement
 We feel profound pleasure in bringing out this projects report for
which we have to go from pillar to post to make it a reality. This project work reflects
contributions of many people with whom we had long discussions and without which it
would not have been possible. We must first of all, express our heartiest gratitude to
respected Prof. (Dept. of E&TC) for providing us all guidance to complete project.

1.Introduction

The aim of the project is to receive the data serially from the computer. The data is
received by means of RS-232 cable which is connected to the serial port of the
computer. The serial data is converted into parallel form with the help of VHDL
coding and the code is downloaded on the SPARTAN-3 kit.
VHDL (VHSIC: very-high-speed integrated circuit) is a hardware description
language used in electronic design automation to describe digital and mixed signal
systems such as field programmable gate array and integrated circuits.
 The VHDL code can be synthesized differently by making use of logic synthesis
tool, logic simulators and logic compilers.
VHDL compilers can read and write files on the host computer, so a VHDL
program can be written that generates another VHDL program to be incorporated in
the design being developed. Because of this general-purpose nature, it is possible to
use VHDL to write a testbench-that verifies the functionality of the design using
files on the host computer-to define stimuli, interacts with the user, and compares
results with those expected.
The purpose of converting serial data into parallel form is that several bits of
data can be transmitted simultaneously down parallel wires. Parallel ports, over
which parallel data is received, are typically used as printer ports on a personal
computer.

SYSTEM BLOCK DIAGRAM

MONITOR P SPARTAN
RS-232 PARALLEL
U KIT
C CABLE DATA

KKKKKKK
SERIAL DATA-KEYBOARD

2. Literature survey

 Difference between a serial port and parallel port

A serial port is a serial communication physical interface through which information
transfers in or out one bit at a time. Whereas parallel port can transfer data 8 times faster
 than serial port.Thus, parallel ports are easy to program and faster compared to the serial
ports.
Serial port is a 9-pin male connector while parallel port is a 25-pin female connector.
Parallel ports are usually purple in color and serial port come in light-green as a part of
ISO-standards when found on PCs.

 What is FPGA?

FPGAs are high performance data processing devices. FPGA performance is derived
from the ability they provide to construct highly parallel architectures for processing
data. An FPGA provides the user with a two-dimensional array of configurable
resources that can implement a wide range of arithmetic and logic functions.
Advantages of using an FPGA include significantly lower non-recurring engineering
costs than those associated with a custom IC (FPGAs are commercial off-the-shelf
devices), shorter time to market, and the configurability of an FPGA, which allows a
design to be modified, even after deployment in an end application.

 Features of VHDL:

 Supports the whole design process:

1. system level
2. RT level
3. logic level

 Suitable for specification in

1. behavioral domain
2. structural domain

 Precise simulation semantics is associated with the language constructs

Kris

 The basic building block of a VHDL model is the entity

 An entity is described as a set of design units

:
  entity declaration
 architecture body
 package declaration
 package body
 configuration declaration

The internal working of an entity can be defined using different modeling styles inside
architcture body. They are

1.      Dataflow modeling: In this style of modeling, the internal working of an entity can
be implemented using concurrent signal assignment.

2.      Behavioral modeling: In this style of modeling, the internal working of an entity can be
implemented using set of statements.

      It contains:

    Process statements
    Sequential statements
    Signal assignment statements
    Wait statements
Process statement is the primary mechanism used to model the behavior of an entity. It contains
sequential statements, variable assignment (:=) statements or signal assignment (<=) statements
etc. It may or may not contain sensitivity list. If there is an event occurs on any of the signals in
the sensitivity list, the statements within the process is executed.

Inside the process the execution of statements will be sequential and if one entity is having two
processes the execution of these processes will be concurrent. At the end it waits for another
event to occur. 

3.      Structural modeling: The implementation of an entity is done through set of interconnected
components.

It contains:

  Signal declaration.
  Component instances
  Port maps.
  Wait statements.
 Component declaration:

 WHY XILINX?

Xilinx FPGAs contain sophisticated I/O mechanisms that can handle a wide range of bandwidth
and voltage requirements. Xilinx ISE tool is used for implementation of systems in FPGA.
Xilinx System Generator for DSP manages the entire design flow from a single environment
.The System Generator tool automatically generates highly efficient VHDL or Verilog code. To
synthesize the VHDL/Verilog, we make use of Xilinx Synthesis Technology (XST).

Following files are created by Xilinx System Generator

 .vhd - the top level VHDL file for your project. There are additional VHDL files included
when your design has more hierarchy.
 core - files associated with the generated multiplier core, such as the behavioral simulation
models and EDIF file.
 corework - subdirectory containing the CORE Generator log file.
 .xcf - generated constraints file when XST synthesis is chosen in the System Generator block.
Buses in this file are denoted with angle brackets.
 .ncf - generated constraints file when Synplify or Leonardo Spectrum is chosen as the
synthesis tool. Buses are denoted with parentheses.
 .npl - project file for opening the design in Xilinx ISE 6.2i Project Navigator, using your
chosen synthesis compiler and ModelSim simulator.
 testbench.vhd - the top level VHDL testbench file, associated with the top level VHDL
source file in the project
 <gateways>.dat - stimulus files for inputs to testbenches, or predicted outputs of testbenches.
The .dat files are generated by Simulink simulation and saved for running in Xilinx
testbenches to verify design behavior. In this example, <gateways> refers to the names of the
Xilinx gateway blocks, which collect and save the data.
 VhdlFiles - a list of VHDL files, and their dependency order, needed for synthesis projects.
System Generator's Perl scripts read from this file when creating project files.

3. SYSTEM DEVELOPMENT

 RS-232 AND ITS FEATURES

 RS-232 STANDARDS:
RS 232 is one of the most widely used standards for sending serial data that is in use today. The
RS-232 standard is used for many applications where it is necessary to send data over a relatively
straightforward set of cables. The RS-232 system for serial data transmission has the advantages
of simplicity while still offering a high level of capability

 RS 232 Voltage levels

In order that the RS 232 transmitters and receivers can be designed to a common standard, it is
necessary to define the voltage levels that constitute the two logical states required for data
transmission. The two states are defined as in the table below.

Signal
Voltage levels Logical State
Volts

-3 to -25 1
+3 to +25 0

It is also necessary to define the voltage states for the control signals as these are widely used
within RS 232.

 RS 232 Handshaking

In order that data can be exchanged on an RS 232 link, the control signals must indicate that the
equipment at either end of the link is ready to send the data and ready to receive the data. This
can be achieved in a number of ways, but one of the more common is to use the RTS , CTS, and
DTR lines.

These lines are found in the Data Terminal Equipment, DTE and Data Communications
Equipment, DCE

A DTE device is "Data Terminal Equipment", this includes Computers, Serial Printers, PLC's,
Video Cameras, Video Recorders, Video Editors

A DCE device is "Data Communications Equipment", this includes devices intended to plug
directly into a DTE port, PDA cables, Modems and devices that extend communications like a
modem, such as RS-422, RS-485, or Fiber Optic converters or Radio Modems. The Output
signals on a DTE port are Inputs to a DCE port, and Output signals on a DCE port are Inputs to
a DTE port

The handshaking exchange to start the data flow is quite straightforward and can be seen as a
number of distinct stages:

1. RTS is put in the ON state by the DTE

2. The DCE then put the CTS line into the ON state

3. The DTE then responds by placing the DTR line into the ON state.

4. The DTR line remains on while data is being transmitted.

At the end of the transmission, DTR and RTS are pulled to the OFF state and then the DCE pulls
the CTS line to the OFF state. This series of handshake controls was devised to allow the DTE to
request control of the communications link from the related modem, and then to let the modem
inform the terminal equipment that the control has been acquired. In this way the
communications will only take place when both ends of the link are ready.

RS232 handshaking signals

 RS232 serial data transmission

The data is sent serially on RS232, each bit is sent one after the next because there is only one
data line in each direction. This mode of data transmission also requires that the receiver knows
when the actual data bits are arriving so that it can synchronize itself to the incoming data. To
achieve this logic 0 is sent as a start bit for the synchronization. This is followed by the data itself
and there are normally seven or eight bits. The receiver obviously has to know how many data
bits to expect, and there are often small dual in line switches either on the back of the equipment
or inside it to set this information.

After the data itself a parity bit is sent. Again this requires setting because it is optional and it can
be even or odd parity. This is used to check the correctness of the received data and it can
indicate whether the data has an odd or even number of logic ones. Finally a stop bit is sent. This
is normally one bit long and is used to signify the end of a particular byte. Sometimes two stop
bits are required and again this is an option that can often be set on the equipment.

RS232 data transmission is normally asynchronous. However transmit and receive speeds must
obviously be the same. Once the start bit is sent the receiver will sample the centre of each bit to
see the level. Within each data word the synchronization must not differ by more than half a bit
length otherwise the incorrect data will be seen. Fortunately this is very easy to achieve with
today's accurate bit or baud rate generators.
 SERIAL DATA TO PARALLEL DATA CONVERSION

START 1 2 3 4 5 6 7 PARITY STOP

BIT BIT BIT

PARALLEL DATA

 USE OF PARALLEL PORT:

Parallel ports are easy to program and faster compared to the serial ports. Parallel ports are
mainly meant for connecting the printer to the PC. But main disadvantage is it needs more
number of transmission lines. Because of this reason parallel ports are not used in long distance
communications.

The basic difference between working of parallel port and serial port. In serial ports, there will be
two data lines: One transmission and one receive line. To send a data in serial port, it has to be
sent one bit after another with some extra bits like start bit, stop bit and parity bit to detect errors.
But in parallel port, all the 8 bits of a byte will be sent to the port at a time and an indication will
be sent in another line. There will be some data lines, some control and some handshaking lines
in parallel port.

The port is composed of 4 control lines, 5 status lines and 8 data lines. It's found commonly on
the back of your PC as a D-Type 25 Pin female connector. A D-Type 25 pin male connector is a
serial RS-232 port

WHAT IS Centronics?
Centronics is an early standard for transferring data from a host to the printer. The majority of
printers use this handshake. This handshake is normally implemented using a Standard Parallel
Port under software control. Below is a simplified diagram of the `Centronics' Protocol.

Data is first applied on the Parallel Port pins 2 to 7. The host then checks to see if the
printer is busy i.e. the busy line should be low. The program then asserts the strobe, waits
a minimum of 1uS, and then de-asserts the strobe. Data is normally read by the
printer/peripheral on the rising edge of the strobe. The printer will indicate that it is busy
processing data via the Busy line. Once the printer has accepted data, it will acknowledge
the byte by a negative pulse about 5uS on the nAck line.

Quite often the host will ignore the nAck line to save time. Latter in the Extended
Capabilities Port, you will see a Fast Centronics Mode, which lets the hardware do all the
handshaking for you. All the programmer must do is write the byte of data to the I/O port.
The hardware will check to see if the printer is busy, generate the strobe. Note that this
mode commonly doesn't check the nAck either.
  SPARTAN-3 KIT AND ITS FEATURES

SPARTAN-3 based Universal DSP ProtoBoard (MXS3FK-004-DSP) provides easy to

use development platform, useful to physically verify DSP algorithms or simple digital
designs around SPARTAN -3 FPGA.

Features

Figure 1 shows the SPARTAN-3 ProtoBoard, which includes the following components and
features:

 SPARTAN -3 FPGA : 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat
Package (MXS3FK-004-DSP)
 Three families Spartan 3 /Spartan 3L/Spartan 3 XA.

 Very low cost, high-performance logic solution for high-volume, consumer-oriented

applications.
- Densities as high as 74,880 logic cells.

- Three power rails for core (1.2V), I/O’s (1.2V to 3.3V) and Auxiliary purposes
(2.5V).
- 326 MHz system clock rate.

 Select IO™ Signaling.

- Up to 784 I/O pins.
- 622 Mb/s data transfer rate per IO.
- 18 single-ended signal standards.
- 6 differential I/O standards including LVDS, RSDS.
- Termination by Digitally Controlled Impedance.
- Double data Rate (DDR) support.

 Logic Resources
- Abundant Logic cells with shift register capability.
- Wide Multiplexers.
- Fast look-ahead carry logic
Figure 1: Block Diagram
4.1 RS- 232 Interface

The RS-232 transmit and receive signals appear on the female DB9 connector, indicated as in
Figure 8. The connector is a DCE-style port and connects to the DB9 DTE-style serial port
connector available on most personal computers and workstations. Use a standard straight-
through serial cable to connect the SPARTAN -3 protoboard to the PC’s serial port.

Figure 2: FPGA – RS232 Interface

Figure 8 shows the connection between the FPGA and the DB9 connector, including the Maxim
MAX3223 RS-232 voltage converter. The FPGA supplies serial output data as LVTTL or
LVCMOS levels to the Maxim device, which in turn converts the logic value to the appropriate
RS-232 voltage level. Likewise, the Maxim device converts the RS-232 serial input data to
LVTTL levels for the FPGA.

Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR
signals are left unconnected. Similarly, the port’s CTS and Ring Indicator are used as an
auxiliary RS232 channel signals

The FPGA connections to the Maxim RS-232 translator appear in Table 7.

RS232 Interface to SPARTAN -3 FPGA

Control Bit FPGA Pin
"TXD1-F" 204
"RXD1-F" 205
4. RESULTS

CHARACTER HEX-VALUE DECIMAL VALUE

a 61 97

b 62 98

c 63 99

d 64 100

z 7A 122

A 41 65

B 42 66

Z 5A 90

0 30 48

1 31 49

9 39 57
Our desired simulation results are as follows:
5. CONCLUSION:

Thus we made the use of SPARTAN-3 kit efficiently. Our aim of receiving serial data from
computer through RS-232 cable is achieved. The data is converted into parallel data by the
means of our VHDL code.