Lab Manual

SUB: ELECTRONICS SYSTEM DESIGN LABORATORY I

Prepared By HOD Principal

 VV COLLEGE OF ENGINEERING
VV Nagar, Arasoor, Sathankulam (TK)
Tisaiyanvillai (Via), Tuticorin-628656.
Ph: 04637-273312
www.vvcoe.org

ELECTRONICS SYSTEM DESIGN LABORATORY I

RECORD NOTE

NAME

REG.NO

DEPT

YEAR/SEM

SUBJECT .
 VV COLLEGE OF ENGINEERING
VV Nagar, Arasoor, sathankulam (TK)
Tisaiyanvillai (Via), Tuticorin-628656.
Ph: 04637-273312
www.vvcoe.org

BONAFIDE CERTIFICATE
Certified that this is bonafide record of work done by
Mr/Ms................................................................................of the..................................

Semester in................................................................of this college in the............................

.........................................................................during.........................................................in
the partial fulfilment of the requirements of the M.E degree course of the ANNA
UNIVERSITY.

Staff in charge Head of the Department

University Registration No........................................................

University Examination held on..............................................

Internal Examiner External Examiner

 TABLE OF CONTENTS

EXPT DATE NAME OF THE EXPERIMENT PAGE SIGN

NO NO

SYSTEM DESIGN USING PIC MICROCONTROLLER

1.A

1.B SYSTEM DESIGN USING 16 BIT MICROPROCESSOR-8086

1.C SYSTEM DESIGN USING 8 BIT MICROCONTROLLER-8051

STUDY OF DIFFERENT INTERFACE (EMBEDDED

2.
MICROCONTROLLER)

3. IMPLEMENTATION OF ADAPTIVE FILTRS AND

MULTISTAGE MULTIRATE SYSTEM IN DSP

4. SIMULATION OF QMF USING SIMULINK PACKAGE

5. ANALYSIS OF CLOCKED SYNCHRONOUS AND

ASYNCHRONOUS SQUENTIAL CIRCUITS

BUILT-IN SELF TEST AND

6.
FAULT DIAGONISIS
DESIGN AND ANALYSIS OF REAL TIME SIGNAL
7.
PROCESSING SYSTEM- GENERATION OF DIFFERENT
TYPES OF SIGNALS
EX.NO: SYSTEM DESIGN USING PIC MICROCONTROLLER
DATE:

AIM:
To write a C program to control various I/O devices on PIC 16F877A board..
APPARATUS REQUIRED:
PIC 16F877A
RS 232 cable
SOFTWARE USED:
MPLAB IDEv8.36
PIC Tiny bootloader
THEORY:
PIC MICROCONTROLLER
PIC Microcontroller is a family of modified Harvard architecture. Micro controllers are made by
Microchip Technology, derived from the PIC 1650 originally developed by general Instruments
Microelectronics Division. The name PIC initially referred to Peripheral Interface Controller
PICs are popular with both industrial developers & hobbyists alike due to their low cost, wide
availability larger user base, extensive collection of application notes, availability of low cost or
free development tools and serial programming and re-programming with flash memory capability.
They are also commonly used in educational programming as they often come with the easy to use
PIC logicator software.
The PIC architecture is Characterized by its multiple attributes
Separate code & data spaces (Harvard architecture)
A small number of fixed length instructions
Most instructions are single cycle execution (2 clock cycles or 4 clock cycles in 8 bit models) with
one delay cycle on branches and skips.
One accumulator, the use of which (as source operand) is implied (i.e., is not encoded in the
opcode)
All RAM location function as registers as both source and/or destination of math and other
functions.
A fairly small amount of addressable data space (typically 256 bytes), extended through banking.
Data space mapped CPU, port and peripheral registers.
The program counter is also mapped into the data space and writable.
 There is no distinction between memory space and register space because the RAM serves the job
of both memory & registers and the RAM is usually just referred to as the register file or simply as
the registers.
PROCEDURE:
Open MPLAB IDE v8.36.
Click projectproject wizardselect deviceselect language toolsuitecreate new project
fileadd existing filesfinish.
Filenewtype the program on the editor window.
Save the fileadd source filesave and built
Power ON the Target board(EM-05) using 7.5V adapter or by USB cable
By using Tiny Bootloader download the EM05 code (hex file) in to the target board in either USB
or serial communication.
For usb programming select the specific COM PORT and select Baud Rate as 115200
For serial programming select the COM1 PORT and select Baud Rate as 115200
Power ON all the Power control switches
SW0Lcd demo
Sw1Led up counter(0-255).
Sw2Segment Multiplexing(0000-9999)
Sw3Led counter using Push Key
Sw4Segment counter using Push Key
Sw5ADC CH0 in LCD(connect POT pin in green connector to ADC0 pin in green connector and
place a jumper on ADC0 near ADC_POT )
SW6ADC CH1 in segment(connect POT pin in green connector to ADC1 pin in green connector
and place a jumper on ADC1 near ADC_POT )
Sw7serial Communication (switch RX and TX to low(0) in target board)
RESULT:
Thus the C program was written to control various I/O devices on PIC 16F877A microcontroller
board.
EX.NO: SYSTEM DESIGN USING 16-BIT 8086 MICROPROCESSOR
DATE:

AIM:
To write an assembly language programs for performing arithmetic operations and controlling a
stepper motor using microprocessor 8086
APPARATUS REQUIRED:

8051 Microprocessor kit

Stepper Motor
Stepper Motor Interfacing Board
Keyboard
a) ARITHMETIC OPERATIONS:
ADDITION OPERATION ALGORITHM:-
1. Get the first data.
2. Get the second data.
3. Add two data.
4. Store the result.
PROGRAM:

MNEMONICS
ADDRESS LABEL HEX CODE
OPCODE OPERAND

1000 START MOV AX,[1100] 8B 06 00 11

1004 ADD AX,[1101] 03 06 02 11

1008 MOV [1200],AX 89 06 00 12

100C HLT F4
FLOW CHART: ADDITION OPERATION

Start

Get the data

Adding the data

Store the result

Stop

OUTPUT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
1100 02 1200 06
1101 03 1201 08
1102 04
1103 05

MULTIPLICATION OPERATION ALGORITHM:-

1. Get the first data.
2. Get the second data.
3. Add two data.
4. Store the result.
PROGRAM:

MNEUMONICS
ADDRESS LABEL HEX CODE
OPCODE OPERAND

1000 START MOV DX,[1100] 8B 16 00 11

1004 MOV AX,[1102] 8B 06 02 11

1008 MUL DX F7 E2

100A MOV [1200],DX 89 06 00 12

100E MOV [1202],AX 89 06 02 12

1017 HLT F4

FLOW CHART: MULTIPLICATION OPERATION

Start

Get the data

Multiply the data

Store the result

OUTPUT: Stop

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
1100 04 1200 14
1101 06 1201 3A
1102 05 1202 2A
 1103 07 1203 00

b) STEPPER MOTOR:

THEORY:

A stepper motor (or step motor) is a brushless DC electric motor that divides a full rotation into a
number of equal steps. The motor's position can be commanded to move and hold at one of these steps
without any feedback sensor (an open-loop controller), as long as the motor is carefully sized to the
application. DC brush motors rotate continuously when voltage is applied to their terminals. Stepper
motors, on the other hand, effectively have multiple "toothed" electromagnets arranged around a central
gear-shaped piece of iron. The electromagnets are energized by an external control circuit, such as a
microcontroller. To make the motor shaft turn, first, one electromagnet is given power, which makes the
gear's teeth magnetically attracted to the electromagnet's teeth. When the gear's teeth are aligned to the first
electromagnet, they are slightly offset from the next electromagnet. So when the next electromagnet is
turned on and the first is turned off, the gear rotates slightly to align with the next one and from there the
process is repeated. Each of those slight rotations is called a "step", with an integer number of steps making
a full rotation. In that way, the motor can be turned by a precise angle.

PROCEDURE:

16 BIT MICROPROCESSOR:

Connect 8086 Microprocessor and stepper motor using interfacing board.

Switch on the power supply, and then type the program.
Press RES Button.
And then execute it.
PROGRAM :

MEMORY LABEL MNEMONICS OPCODE

ADDRESS

1000 START MOV DI,1050 C7,C7,50,10

1004 MOV CL,04 C0,C,04

1007 LOOP 1 MOV AL,[DI] 8A,05

OUT OCOH,AL E6,C0

100B MOV DX,1010 BA,1010

100F DELAY DEC DX 4A

1010 JNZ DELAY 75,FD

1012 INC DI 47

1013 LOOP LOOP1 F9,E5

1015 JMP START FF

OUTPUT:

FORWARD DIRECTION :

ADDRESS DATA

1018 09

1019 05

101A 06

101B 0A
 REVERSE DIRECTION:

ADDRESS DATA
1018 0A

1019 06

101A 05

101B 09

RESULT:
Thus an assembly language programs for performing arithmetic operations such as addition and
multiplication and controlling a stepper motor were written and executed successfully using microprocessor
8086.

EX.NO: SYSTEM DESIGN USING 8-BIT 8051 MICROCONTROLLER

DATE:
AIM:
To write an assembly language programs to perform arithmetic operation such as subtraction and
division of two 8-bit numbers and controlling stepper motor using 8051 microcontroller.
APPARATUS REQUIRED:
8051 microcontroller kit
Keyboard
Stepper Motor
Stepper Motor Interfacing Board.
a) ARITHMETIC OPERATIONS
SUBTRACTION OPERATION ALGORITHM:-
1. Clear C register for carry.
2. Move the first data to accumulator.
3. Multiply the second data with accumulator
4. Store the result in memory location pointed by DPTR.
PROGRAM:
MNEUMONICS
ADDRESS LABEL HEX CODE
OPCODE OPERAND

4100 START CLR C C3

4101 MOV A,#data1 74 04

4103 SUBB A,#data2 94 04

4105 MOV DPTR,#4500H 90 45 00

4107 MOVX @DPTR,A F0

4108 LOOP SJMP LOOP 80 FE

FLOW CHART: SUBTRACTION OPERATION

Start

Get the data

Subtracting the data

Store the result

Stop
OUTPUT:

INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
4100 04 4500 02
4101 02

DIVISION OPERATION ALGORITHM:-

1. Move first data to accumulator.
2. Move second data to B register.
3. Divide second data from the first data.
4. The reminder is in B register.
5. Store the result in memory pointed by DPTR.

PROGRAM:
MNEUMONICS
ADDRESS LABEL HEX CODE
OPCODE OPERAND
4100 START MOV A,#data1 74 04
4103 MOV B,#data2 75 F0 02
4106 DIV A,B 84
4107 MOV DPTR,#4500H 90 45 00
410A MOVX @DPTR,A F0
410B INC DPTR A3
410C MOV A,B E5 F0
410E MOVX DPTR,A F0
410F LOOP SJMP LOOP 80 FE
FLOW CHART: DIVISION OPERATION

Start

Get the data

divide the data

Store the result

OUTPUT: Stop
INPUT OUTPUT
ADDRESS DATA ADDRESS DATA
4100 04 4500 02
4101 02

b) STEPPER MOTOR:

PROCEDURE:

Connect 8051 Microcontroller and stepper motor using interfacing board.

Switch on the power supply.
In microcontroller kit, Press RES Button.
Type the program and then execute it.
PROGRAM:

MNEUMONICS
ADDRESS OPCODE OPERAND HEX CODE
LABEL
4100 ORG 4100H
 4100 START MOV DPTR,#4500H 90,45,00
4103 MOV R0,#04 78,04
4105 JO MOVX A,@DPTR E0
4106 PUSH DPH C0,83
4108 PUSH DPL C0,82
410A MOV DPTR,#FFCOH 90,FF,C0
410D MOV R2,#04H 7A,04
410F MOV R1,#0FH 79,0F
4111 DLY1 MOV R3,#0FH 7B,0F
4113 DLY DJNZ R3,DLY DB,FE
4115 DJNZ R1,DLY1 D9,FA
4117 DJNZ R2,DLY1 F0
4119 MOVX @DPTR,A D0,82
411A POP DPL D0,83
411C POP DPH A3
411E INC DPTR D8,E4
411F DJNZ R0,JO 80,DD
4121 SJMP START
4123 END
4500 DB 09,05,06,0A 09,05,06,0A

OUTPUT:
FORWARD DIRECTION:

ADDRESS DATA
1018 09

1019 05

101A 06

101B 0A
REVERSE DIRECTION:

ADDRESS DATA
1018 0A

1019 06

101A 05

101B 09

RESULT:
Thus an assembly language programs for performing arithmetic operations such as subtraction,
division and controlling a stepper motor were written and executed successfully using 8051
microcontroller.
EX.NO:
DATE:
STUDY OF DIFFERENT INTERFACE (EMBEDDED MICROCONTROLLER)
AIM:
To study the modern train control interface using PIC Microcontroller.

APPARATUS REQUIRED:
Modern Train Controller Interface Card
Embedded Development Board(PIC 16F877A)
USB cable
GPIO Connector
Data cable
THEORY:

MODERN TRAIN CONTROLLER

The Model Train Control(MTC) interface card provides the ability to independently control all
aspects of operating a modern train using signal(slide) switches A,B,C,D. A signal switch is used to select
manual/automatic mode operation. It has been designed with LEDs. LEDs are visually indicates the state
of I/O operations controlled by the target boards .Slide switches are devices that have two positions ON
and OFF, which have a role to establish or break a connection between two contacts. GPIO connector is
used to interface the target boards to interface board.
MODERN TRAIN CONTROLLER: MANUAL FLOW CHART
MODERN TRAIN CONTROLLER: AUTOMATIC FLOW CHART

RESULT:
Thus the modern train controller was successfully interfaced with PIC microcontroller and its
operation was observed both manually and automatically.
EX.NO:
DATE:
IMPLEMENTATION OF ADAPTIVE FILTERS AND MULTISTAGE
MULTIRATE SYSTEM IN DIGITAL SIGNAL PROCESSING
AIM:

To implement adaptive filters and to implement interpolation and decimation FIR filter algorithm in
multirate signal processing by using DSP processor

APPARATUS REQUIRED:

Cc studio v3.1

TMS320c6713 kit

DSP processor

PC

THEORY

ADAPTIVE FILTER
Digital signal processing (DSP) has been a major player in the current technical advancements such
as noise filtering, system identification, and voice prediction. Standard DSP techniques, however, are not
enough to solve these problems quickly and obtain acceptable results. Adaptive filtering techniques must
be implemented to promote accurate solutions and a timely convergence to that solution.

ADAPTIVE FILTERING SYSTEM CONFIGURATIONS

There are four major types of adaptive filtering configurations: adaptive system identification,
adaptive noise cancellation, adaptive linear prediction, and adaptive inverse system. All of the above
systems are similar in the implementation of the algorithm, but different in system configuration. All 4
systems have the same general parts: an input x(n), a desired result d(n), an output y(n), an adaptive
transfer function w(n) and an error signal e(n) which is the difference between the desired output u(n) and
the actual output y(n). In addition to these parts, the system identification and the inverse systems
configurations have an unknown linear system u(n) that can receive an input and give a linear output to the
given input.

ADAPTIVE SYSTEM IDENTIFICATION CONFIGURATION

The adaptive system identification is primarily responsible for determining discrete estimation of the
transfer function for an unknown digital or analog system. The same input x(n) is applied to both the
adaptive filter and the unknown system from which the outputs are compared(figure). The output of the
adaptive filter y(n) is subtracted from the output of the unknown system resulting in a desired signal d(n).
The resulting difference is an error signal e(n) used to manipulate the filter co-efficient of the adaptive
system trending towards an error signal of zero.

PROCEDURE:

Start up the cc studio v3.3 & open it, go project give project name and save it (Local disk
D(DSP) and create your project

Click local disk D DSP already create your folder (Cg int) and save the save the start asm file,
and file codec file, lib file, IPF file.

Click fileNew Source file & type the c program and save it the same folder.

Click Add to Project files and all files listed above included c file.

Go Project Build options. Click linker Basic, set static size: 1000 & library Inc, set rts6700.lib and
click OK.

Click linker order add all files and arrange in this order. (Start asm, c file, and file, codec fle, IPF
file).

Go Project Build, then go to start All program Top view DSP debugger click file load program
and load the c program into kit. Click OK.

Output is viewed on CRO through Kit connection.

PROGRAM: ADAPTIVE FILTERS

typedef unsigned int Uint32;

typedef int Int32;
typedef short Int16;
typedef unsigned short Uint16;

int main(void)
{
Int16 outCh1;
Int16 outCh2;
Int16 *origSig;
Int16 *noiseSig;
Int16 alteredSig;
Int 16 noiseEst;
double *kern;
Int16 errorSig;
Int32 outValue;
Int32 filtCount;
Uint32 *socValue;
Uint32 socRead;
Uint32 *adcValue;
Uint32 *dacCh1;
Uint16 *dacCh2;
Uint16 adcOut;
socValue=(Uint32 *)0x9004000c;
adcValue = (Uint32 *)0x90040008;
dacCh1 = (Uint32 *)0x90040008;
dacCh2 = (Uint16 *)0x9004000a;
origSig = (Int16 *)0x00013000;
noiseSig = (Int16 *)0x00014000;
 kern = (double *)0x00016000;
for(filtCount = 0; filtCount < 32; filtCount++)
{
*(noiseSig + filtCount) = 0x00000000;
*(kern + filtCount) = 0x00000000;
}
while(1)
{
socRead = *socValue;

adcOut = *adcValue;
adcOut &= 0x0fff;
//adcOut ^= 0x0800;

*origSig = adcOut;
adcOut = *adcValue;
adcOut &= 0x0fff;
adcOut ^= 0x0800;

*noiseSig = adcOut;
alteredSig = *origSig + *noiseSig;

outValue = 0;

for(filtCount = 0; filtCount < 32; filtCount++)

outValue += *(noiseSig + filtCount) * *(kern + filtCount);

noiseEst = outValue >> 12;

errorSig = alteredSig - noiseEst;

for(filtCount = 31; filtCount >= 0; filtCount--)

{
*(kern + filtCount) = *(kern + filtCount) + (2 * 0.0000001 * errorSig) *
*(noiseSig + filtCount);
*(noiseSig + filtCount + 1) = *(noiseSig + filtCount);
}
outCh1 = alteredSig;
//*dacCh1 = adcOut;
*dacCh1 = outCh1;
outCh2 = errorSig;
//*dacCh2 = adcOut;
*dacCh2 = outCh2;
}
return 0;
}
PROGRAM: MULTISTAGE MULTIRATE SYSTEM

#include "deci3.h"
#include "deci4.h"
#include <stdio.h>
/* Specifications for the filters used: fs = 8 KHz, fp1 = fp2 = 700 Hz, fs1 = 3000 Hz, fs2 = 1000 Hz, dp1 =
dp2 = 0.005, ds1 = ds2 = 0.001, N1 = 8, N2 = 37, M1 = M2 = L2 = L1 = 2.
For every 4 samples read from the adc the following approximate times apply without using any additional
delays:
samples 1 and 3: 16 us, sample 2: 28 us, sample 4: 0.1 ms
sample 1 = indexSamp 1
sample 2 = indexSamp 2
sample 3 = indexSamp 3
sample 4 = indexSamp 0
This means that without using additional delays the samples are not read at the 8 Khz rate.
Therefore appropriate delays are added for samples 1, 2, 3 and 4 so that each sample would be read at a rate
close to 8 KHz (0.125 ms). */
typedef unsigned int Uint32;
typedef int Int32;
typedef short Int16;
typedef unsigned short Uint16;
typedef unsigned char Uchar;

adcValue = (Uint32 *)0x90040008;

dacValue = (Uint32 *)0x90040008;
fInterpL2 = (Int16 *)0x0000a000; fInterpL1 = (Int16 *)0x0000b000; inDeciM1 = (Uint32 *)0x00011000;
inDeciM2 = (Uint32 *)0x00012000;
inInterpL2 = (Uint32 *)0x00013000;
inInterpL1 = (Uint32 *)0x00014000;
storeL1= (Uint32 *)0x00016000;
outL1 = (Uint32 *)0x00017000;
led = (Uchar *)0x90040016;
inTest = (Uint32 *)0x00015000;
for(filtCount = 0; filtCount < 50; filtCount++)
*(inTest + filtCount) = filtCount + 0x300;
for(filtCount = 0; filtCount < 37; filtCount++)
*(fInterpL2 + filtCount) = *(fDeciM2 + filtCount) * 2;
for(filtCount = 0; filtCount < 8; filtCount++)
*(fInterpL1 + filtCount) = *(fDeciM1 + filtCount) * 2;
for(filtCount = 0; filtCount < 200; filtCount++)
{
*(inDeciM1 + filtCount) = 0;
*(inDeciM2 + filtCount) = 0;
*(inInterpL2 + filtCount) = 0;
*(inInterpL1 + filtCount) = 0;
}
indexL2 = 1;
indexL1 = 1;
countM1 = 1;
countM2 = 0;
countL2 = 0;
countL1 = 0;
indexSamp = 1;
while(1)
{
if(indexSamp == 0)
for(tCount = 0; tCount < 200; tCount++);
else if ((indexSamp == 1) || (indexSamp == 3))
for(tCount = 0; tCount < 700; tCount++); socRead = *socValue;
adcOut = *adcValue;
adcOut &= 0x0fff;
adcOut ^= 0x0800;
*inDeciM1 = adcOut;
if(countM1 == 2)
{
deciM1();
countM1 = 0;
countM2++;
}
if(countM2 == 2)
{
deciM2();
countM2 = 0;
}
if((countM1 == 0) && (countM2 == 0))
{
while(countL2 < 2)
{
interpL2();
for(filtCount = 36; filtCount >= 0; filtCount--)
*(inInterpL2 + filtCount + 1) = *(inInterpL2 + filtCount);
indexInit = 1;
countL2++;
}
}
storeL1= (Uint32 *)0x00016000;
if((countM1 == 0) && (countM2 == 0) && (countL2 == 2))
{
while(countL1 < 4)
{
if(countL1 == 0)
else if(countL1 == 2) {
valueL1 = *(storeL1 + 1);
*inInterpL1 = valueL1;
}
interpL1();
for(filtCount = 7; filtCount >= 0; filtCount--)
*(inInterpL1 + filtCount + 1) = *(inInterpL1 + filtCount);
countL1++;
}
}
outL1 = (Uint32 *)0x00017000;
if(indexInit == 0)
outValue = 0x800;
else
outValue = *(outL1 + indexSamp);
*dacValue = outValue;
indexSamp++;
countL1 = 0;
countL2 = 0;
for(filtCount = 7; filtCount >= 0; filtCount--)
*(inDeciM1 + filtCount + 1) = *(inDeciM1 + filtCount);
countM1++;
if(indexSamp == 4)
indexSamp = 0;
}
return 0;
}
int deciM1(void)
{
for(filtCount = 36; filtCount >= 0; filtCount--)
*(inDeciM2 + filtCount + 1) = *(inDeciM2 + filtCount);
outValue = 0;
for(filtCount = 0; filtCount < 8; filtCount++)
outValue += *(inDeciM1 + filtCount) * *(fDeciM1 + filtCount);
outValue >>= 14;
*inDeciM2 = outValue;
return 0;
}
int deciM2(void)
{
outValue = 0;
for(filtCount = 0; filtCount < 37; filtCount++)
outValue += *(inDeciM2 + filtCount) * *(fDeciM2 + filtCount);
outValue >>= 14;
*inInterpL2 = outValue;
return 0;
}
int interpL2(void)
{
indexL2 ^= 0x01;
if(indexL2 == 0)
filtCount = 0;
else
filtCount = 1;
outValue = 0;
while(filtCount < 37)
{
outValue += *(inInterpL2 + filtCount) * *(fInterpL2 + filtCount);
filtCount += 2;
}
outValue >>= 16;
*storeL1++ = outValue;
return 0;
}
int interpL1(void)
{
indexL1 ^= 0x01;
if(indexL1 == 0)
filtCount = 0;
else
filtCount = 1;
outValue = 0;
while(filtCount < 8)
{
outValue += *(inInterpL1 + filtCount) * *(fInterpL1 + filtCount);
filtCount += 2;
}
outValue >>= 16;
*outL1++ = outValue;
return 0;
}

RESULT:

Thus the adaptive filters and multistage multirate system were implemented in DSP Processor
successfully and the corresponding output was obtained.
EX.NO:
DATE:
SIMULATION OF QMF USING SIMULATION PACKAGES
AIM:
To simulate QMF using simulation package (Matlab).
SOFTWARE REQUIRED:
System with MATLAB R2011b.
ALGORITHM:
1. Start the program.
2. Get the denominator coefficient.
3. Get the input sequence.
4. Get the initial condition vector.
5. Calculate first all pass, second all pass and time reversal output of cascade.
6. Stop the program.
PROCEDURE:
Open MATLAB.
File New M-File.
In the editor untitled window type program save.
Debug Save and Run.
Then the output will be displayed.
THEORY:
In digital signal processing, a Quadrature Mirror Filter (QMF) is a filter most commonly used to
implement a filter bank that splits an input signal into two bands. The resulting high-pass and low-pass
signals are often reduced by a factor of 2, giving a critically sampled two-channel representation of the
original signal.
Multirate filter banks are so named because they effectively alter the sampling rate of a
digital system, as indicated by the decimators (downsamplers) following the analysis filters, A0 and A1,
and the expanders (upsamplers) preceding the synthesis filters, S0 and S1. Properly designed analysis and
synthesis filters combined with the properties of decimation and expansion allow filter banks to partition a
wideband input signal into multiple frequency bands (often called sub bands or channels) and to recombine
these sub band signals back into the original signal. In the case of Figure a, the analysis filters, A0 and A1,
are typically complementary low pass and high pass filters that mirror each other about the digital
frequency shown in Figure b .Such filters are often called Quadrature Mirror Filter(QMF).
PROGRAM (USING MATLAB PROMPT):
%Load scaling filter associated with an orthogonal wavelet.
load db10;
subplot (321); stem (db10);title(db10 low-pass filter);
%Compute the quadrature mirror filter.
qmfdb10=qmf (db10);
subplot (322); stem(qmfdb10);title(QMF db10 filter);
%Check for frequency condition (necessary for orthogonality).
%abs(fft(filter))^2+abs(fft(qmf(filter)) ^2)=1 at each %frequency.
m=fft (db10);
mt=fft (qmfdb10);
freq= [1: length (db10)]/ length(db10);
subplot (323); plot (freq,abs(m));
title (Transfer modulus of db10);
subplot (324); plot(freq,abs(mt));
title (Transfer modulus of QMF db10);
subplot (325); plot (freq,abs(m).^2+abs(mt).^2);
title (Check QMF condition for db10 and QMF db10);
xlabel(abs(fft(db10))^2+abs(fft(qmf(db10))^2)=1)

OUTPUT:
 Figure (a) Block diagram of a simple two-channel Multirate system, and (b) approximate magnitude
responses of analysis filters, A0 and A1 .
PROGRAM (USING MATHEMATICAL EXPRESSIONS):
clear all;
a=input ('Enter the denominator coefficient :');
N=length (a)-1;
k= [0: N];
b (1+k)=a(1+N-k);
x1=input('Enter the input sequence:');
M=length(x1);
zi=input('Enter the initial condition vector:');
N=length (zi);
[yf1, zf1]=filter (b, a, x1, zi);
zf2=fliplr (zf1);
x2=fliplr (yf1);
yf2=filter (b, a, x2, zf2);
yf3=fliplr (yf2);
disp ('Input=');
disp(x1);
disp('Output of first all pass=');
disp(yf1);
disp('Output of second all pass=');
disp(yf2);
disp('Time reversed output of cascade=');
disp(yf3);

OUTPUT:
Enter the denominator coefficient: [1 3 5 7]
Enter the input sequence: [4 6 8 0]
Enter the initial condition vector: [20 40 60]
Input= 4 6 8 0
Output of first all pass= 48 -42 44 -196
Output of second all pass= -680 2048 -2034 684
Time reversed output of cascade=684 -2034 2048 -680
RESULT:
Thus the QMF was designed using simulation package and its output was verified.
EX.NO:
DATE:
ANALYSIS OF CLOCKD SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

AIM:

To design and analyses the synchronous and asynchronous sequential circuits and to verify its input
& output characteristics using verilog.

SOFTWARE REQUIRED:

Modelsim ALTERA STARTER EDITION 6.6c

Personal computer
PROCEDURE:

Open the Modelsim simulation software, click jumpstart, create a new project and new file.
Type the code on the new file, save the file.
Compile the code.
Stimulate the code by clicking start simulation.
Give the input values and click run.
Corresponding output will be displayed.
continue the procedure for different input values and check the output
THEORY:

ASYNCHRONOUS COUNTERS:

Only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the
output of the preceding flip-flop. Asynchronous counters are slower than synchronous counters because of
the delay in the transmission of the pulses from flip -flop to flip-flop. Asynchronous counters are also called
ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
SYNCHRONOUS COUNTERS:

The asynchronous counters are simple, but not very fast. If a counter with a larger number of bits is
constructed in this manner, then the delays caused by the cascaded clocking scheme may become too long
to meet the desired performance requirements. A 4-bit synchronous counter built from D-flip flops with
carry-input (count-enable) and carry-output. In this circuit, the single clock signal is directly connected to
all flip flops, so that all flip flops change state at the same time. It is possible to devise a counter like circuit
in which each flip -flop reaches the state Qi = 1 for exactly one count, while for all other counts Qi = 0.
Then Qi indicates directly an occurrence of the corresponding count. Actually, since this does not represent
binary numbers, t is better to say that the outputs of the flips-flops represent a code. Such a circuit can be
constructed from a simple shift register, as indicated in Figure. The Q output of the last stage in the shift
register is fed back as the input to the first stage, which creates a ring like structure. If a single 1 is injected
into the ring, this 1 will be shifted through the ring at successive clock cycles. For example, in a four-bit
structure, the possible codes Q0 ,Q1 .Q2, Q3 will be 1000, 0100, 0010, and 0001.
PROGRAMS:

ASYNCHRONOUS (RIPPLE) COUNTER:

module dff (d, clk, q, qbar);

input d;

input clk;

output q, qbar;

reg q, qbar;

always@ (posedge clk)

begin

q=d;

qbar=~d;

end

endmodule

module Ripple Counter(Count,RST,A0,A1,A2,A3);

output A0,A1,A2,A3;

input Count, RST;

//add d0, d1, d2, d3 as instance for each D_FF:

D_FF d0 (~A0,A0,Count,RST);

D_FF d1 (~A1,A1,A0,RST);

D_FF d2 (~A2,A2,A1,RST);

D_FF d3 (~A3,A3,A2,RST);

endmodule

module D_FF (D,Q,CLK,RST);

output Q;
input D,CLK,RST;

reg Q;

always @ (posedge CLK or negedge RST)

if(~RST)

Q=1'b0;

else

Q=D;

endmodule

SYNCHRONOUS COUNTER (RING COUNTER):

module dff(q,d,c);

output q;

input d,c;

reg q;

initial

q=1'b1;

always @ (posedge c)

q=d;

endmodule

module dff1(q,d,clk);

output q;

input d,clk;

reg q;

initial

q=1'b0;
always @ (posedge clk)

q=d;

endmodule

module ring(q,clk);

inout [3:0]q;

input clk;

dff u1(q[0],q[3],clk);

dff1 u2(q[1],q[0],clk);

dff1 u3(q[2],q[1],clk);

dff1 u4(q[3],q[2],clk);

endmodule

OUTPUT:

SYNCHRONOUS (RING) COUNTER:

ASYNCHRONOUS (RIPPLE) COUNTER:

RESULT:

Thus the synchronous and asynchronous sequential circuits are designed and analysed using verilog and its
output are verified.
 BUILT-IN SELF TEST AND FAULT DIAGNOSIS

EX.NO:
DATE:

AIM:
To generate test vectors internally and verify the functionality of the integrated circuits on chip to
diagnose fault in the circuits by using built-in self test and fault diagnosis.

APPARATUS REQUIRED:

Modelsim ALTERA STARTER EDITION 6.6c

Personal computer.
THEORY:

Self-test and built-in test techniques rely on augmenting circuits to allow them to perform operations
upon themselves that prove correct operation these techniques add area to the chip for the test logic, but
reduce the test time required and thus can lower the overall system cost.

One method of testing a module is to use signature analysis or cyclic redundancy checking. This
involves using a pseudo-random sequence generator to produce the input signals for a section of
combinational circuitry and a signature analyzer to observe the output signals.

A PRSG is defined by a polynomial of some length n. it is constructed from a linear feedback shift
register, LFSR which in turn is made of n flip-flops connected in a serial fashion. The XOR of particular
outputs are fed back to the input of the LFSR will cycle through 2n-1 states before repeating the sequence

The linear-feed back shift register consist of N registers connected together as a shift register. The
input to the shift register comes from the XOR of particular bits of the register. On reset, the registers must
be initialized to a nonzero value. The inputs fed to the XOR are called the tap sequence and are specified
with a characteristic polynomial. The output Y in the diagram follows the 7-bit sequence [1110010]. This is
an example of a pseudorandom bit sequence because it is random. These are handy for built-in self test and
bit-error-rate testing in communication links.

PROCEDURE:

Open the modelsim simulation software, click jumpstart, create a new project and new file.
Type the code on the new file, save the file.
Compile the code.
 Stimulate the code by clicking start simulation.
Give the input values and click run.
Corresponding output will be displayed
LOGIC DIAGRAM OF 3-BIT LFSR:

Da Db Dc

TRUTH TABLE OF LFSR:

Q2 Q1 Q0 OUTPUT Y

1 1 1 1

0 1 1 1

0 0 1 1

1 0 0 0

0 1 0 0

1 0 1 1

1 1 0 0

1 1 1 1
PROGRAM OF LFSR:

module lfsr (clk,rst,y);

input clk,rst:

output y;

reg y;

reg [2:0]tmp;

always @(posedge clk)

begin

if (rst)

tmp=3`b111;

else

begin

tmp={tmp[0]^tmp[1],tmp[2],tmp[1]};

end

assign y=tmp[0];

end

endmodule
OUTPUT:

RESULT:

Thus the test vectors are generated by using pseudo random sequence generator in order to test the
functionality of the ICs internally.
 DESIGN AND ANALYSIS OF REAL TIME SIGNAL PROCESSING SYSTEM-
GENERATION OF DIFFERENT TYPES OF SIGNALS
EX.NO:
DATE:

AIM:
To design the real time signal processing system to generation of different types of signals and to
analyse the output by using DSP processor.

APPARATUS REQUIRED:

Top view

TMS320c65xx kit

DSP processor

PC

THEORY:

A set of independent variable which convey information is called signal. There are two types of
signals, they are continuous time signal and discrete time signal. A continuous time signal is a set of
independent variables which varies continuously with time. Exa: speech signal. A discrete time signal is a
set of independent variable which depends on discrete set of values. Exa: crime rate vs total population.
There are some standard input or test signals, they are step signal, ramp signal, impulse signal, rectangular
pulse, exponential signal, sine and cosine signals.

RAMP FUNCTION

The ramp function is closely related to the unit-step discussed above. Where the unit step goes
from zero to one instantaneously, the ramp function better resembles a real-world signal, where there is
some time needed for the signal to increase from zero to its set value, one in this case. We define a ramp
function as follows
UNIT-STEP FUNCTION

Another very basic signal is the unit-step function that is defined as

Note that the step function is discontinuous at the origin; however, it does not need to be defined
here as it does not matter in signal theory. The step function is a useful tool for testing and for defining oth -
er signals. For example, when different shifted versions of the step function are multiplied by other signals,
one can select a certain portion of the signal and zero out the rest.

UNIT IMPULSE FUNCTION

The unit impulse function is a signal that has infinite height and infinitesimal width. However, be-
cause of the way it is defined, it actually integrates to one. While in the engineering world, this signal is
quite nice and aids in the understanding of many concepts, some mathematicians have a problem with it be-
ing called a function, since it is not defined at t = 0.

SINUSOIDS

Probably the most important elemental signal that you will deal with is the real-valued sinusoid. In
its continuous-time form, we write the general form as

where A is the amplitude, ! is the frequency, and _ represents the phase. Note that it is common to see !t re-
placed with 2_ft. Since sinusoidal signals are periodic, we can express
the period of these, or any periodic signal, as

PROCEDURE:

Start up the cc studio v3.3 & open it, go project give project name and save it (Local disk
D(DSP) and create your project

Click local disk D DSP already create your folder (Cg int) and save the save the start asm file,
and file codec file, lib file, IPF file.
 Click fileNew Source file & type the c program and save it the same folder.

Click Add to Project files and all files listed above included c file.

Go Project Build options. Click linker Basic, set static size: 1000 & library Inc, set rts6700.lib and
click OK.

Click linker order add all files and arrange in this order. (Start asm, c file, and file, codec fle, IPF
file).

Go Project Build, then go to start All program Top view DSP debugger click file load program
and load the c program into kit. Click OK.

Output is viewed on CRO through Kit connection.

PROGRAM (GENERATION OF SINE WAVE):

;---------------------------------------------------------

;Frontline Electronics Pvt Ltd, Salem, INDIA. 02-03-2002

;sine.asm - Example program to generate sinewave.

; (FEPL 5X DSK target board).

;---------------------------------------------------------

.mmregs ;initialise all registers.

.ds 1000h

.include "sinetbl.dat" ;load 800 point wavetable

;f1= fs/D = 8000/800 = 10hz.

.ds 0f00h
temp .word 0

mod .word 100 ;Required freq. = mod * f1 = 100*10 = 1000hz.

scale .q15 0.5

;---------------------------------

;Interrupt vectors

;---------------------------------

.ps 080ah

rint b getdata ;receive interrupt

xint b xint ;transmit interrupt

.ps 0a00h ;program entry point

.entry

;---------------------------------

;Processor initialization

;---------------------------------

.include "c:\fepl\c5xinz.asm"

splk #012h,IMR ;enable RINT & INT2.

call ac01_init ;call to initialize serial port & AC01.

 clrc INTM ;enable all interrupts.

wait: nop ;wait for interrupt.

b wait

;---------------------------------

;Receive interrupt handler

;---------------------------------

getdata splk #1,gotflag ;set a flag to indicate data available.

lamm DRR

ldp #mod ;set data page pointer.

lacc mod ;load modifier

samm INDX ;store modifier in INDX register.

call wavgen ;calculate current sample output from wavetable.

and #0FFFCh,0 ;only 14 MSBs are used in ADC & DAC,So

; mask unused two LSBs.

samm DXR ;send digital data to DAC to produce analog o/p.

clrc INTM ;enable interrupt.

rete ;return back to main from interrupt routine.

offset .set 1320h ;table length = 800 + table start address.

.include "c:\fepl\wavgen.asm" ;include wavgen module.

;---------------------------------

;AC01 register initialization.

;---------------------------------

REG1 .set 0124h

; 0000000100100100b ;36 -> 8ks/sec @ 10.368Mhz clockin

REG2 .set 0212h

; 0000001000010010b ;reg 2 = B register 18(18,default),8ks/sec

; ||||||||||||||||

; ||||||||++++++++-- data

; |||+++++---------- address

; ||+--------------- 0 = write

; ++---------------- phase shift

REG4 .set 0417h

; 0000010000010111b ;reg4 amplifier gain sellect

; ||||||||||||||++-- output 0=sq, 1=0 dB, 2=-6 dB, 3=-12 dB

; ||||||||||||++---- input 0=sq, 1=0 dB, 2=+6 dB, 3=+12 dB

; ||||||||||++------ monitor 0=sq, 1=0 dB, 2=-8 dB, 3=-18 dB

; ||||||||++-------- not used

; |||+++++---------- address

; ||+--------------- 0 = write

; ++---------------- phase shift

REG5 .set 0505h

 ; 0000010100000101b ;reg5 Analog configuration

; ||||||||||||||++-- 0=loopback, 1=norm i/p, 2=aux i/p, 3=both

; |||||||||||||+---- 0=hp filter on, 1=hpfilter off

; ||||||||||||+----- 0=echo off, 1=echo on

; ||||||||++++------ not used

; |||+++++---------- address

; ||+--------------- 0 = write

; ++---------------- phase shift

;---------------------------------

;Serial port and AC01 initialization

;---------------------------------

.include "c:\fepl\ac01inz.asm"

.END ;end of program.

RESULT:

Thus a real time signal processing system was designed and output was analysed for a sine signal.