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Lab 2

1. The document describes an experiment to draw the layouts of NMOS and PMOS transistors using L-Edit software. 2. Students are instructed to draw the layouts by first drawing the active contact, metal, polysilicon, and active layers for both NMOS and PMOS, and to then check for errors using design rule checking. 3. The key differences between NMOS and PMOS layouts are explained as the select icon used - N-select for NMOS and P-select for PMOS.

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Aminah Ismail
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388 views

Lab 2

1. The document describes an experiment to draw the layouts of NMOS and PMOS transistors using L-Edit software. 2. Students are instructed to draw the layouts by first drawing the active contact, metal, polysilicon, and active layers for both NMOS and PMOS, and to then check for errors using design rule checking. 3. The key differences between NMOS and PMOS layouts are explained as the select icon used - N-select for NMOS and P-select for PMOS.

Uploaded by

Aminah Ismail
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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POLITEKNIK TUANKU SULTANAH BAHIYAH

KULIM HI-TECH PARK


09000 KULIM, KEDAH DARUL AMAN

JABATAN KEJURUTERAAN ELEKTRIK

E 5163
INTEGRATED CIRCUIT DESIGN

EXPERIMENT : LAB 2

TITLE : DRAW THE NMOS & PMOS LAYOUT

A. OBJECTIVE:

1. Draw the NMOS layout


2. Draw the PMOS layout
3. State the difference between NMOS and PMOS.
4. State the layer used in both drawing layout
5. Run cross section and evaluate the process for that transistor

B. EQUIPMENT:

• Computer with L-Edit software

C. THEORY:

L-EDIT is the software that uses to create VLSI (Very Large Scale
Integration) design from Tanner Research Company, Inc. In process construction
layout, firstly we advised to draw followed the turn as show below:
Active, Poly, Contact, N-select, P-select, N-well and Metal so that it can follow
the layout rules for N-well 1.2um AMI process (find as SCN process).

D. PROCEDURE:

1. First of all, draw the nMOS layout as picture 1 below. Put the port vdd,
vss, in and out. Drawing the port with the one dimension only.
2. Then we make sure the drawing doesn’t have error. Using DRC (Design
Rule Check) to check
3. Running cross section. We evaluate the cross section.
4. Then, save the drawing as “nMOS”.
Step drawing:

i. Draw active contact layer


ii. Draw metal layer
iii. Draw polysilicon layer
iv. Draw active area layer-green
v. Draw n-select layer

Step to run cross section:

Click tab Tools > Cross Section > Click browse > Local Disk (C) > Tanner >
Ledit101 > Samples > Tech > Mosis > morbn20.xst > click ‘OK’ until cross
section appear.

5. I draw the pMOS layout as picture 1 below and the port vdd, vss, in and
out. It only one dimensions port that I draw.
6. I make sure the drawing doesn’t have error. Check it using DRC (Design
Rule Check)
7. Run cross section with it and evaluate the cross section.
8. Then I save the drawing as “pMOS”.
Step drawing:

i. Draw active contact layer


ii. Draw metal layer
iii. Draw polysilicon layer
iv. Draw active area layer-green
v. Draw p-select layer

Step to run cross section:

Click tab Tools > Cross Section > Click browse > Local Disk (C) > Tanner >
Ledit101 > Samples > Tech > Mosis > morbn20.xst > click ‘OK’ until cross
section appear.

Report must be containing:

i. Layout with label


ii. Cross section
iii. Cross section evaluation
iv. Discussion
v. Conclusion

E. QUESTION AND TASK

1. What the difference between nMOS and pMOS?


-Differences between it is the select icon when we creating the layout.
-If it is nMos, use N select to use it and if is pMos, use P select.

2. How much spacing between active contact and polysilicon?


-4um as a min spacing.

3. Why we must run the cross section?


-To evaluate the layout.
-See every each layout whether it’s in correct order.

4. What the minimum width for metal?


-3um.

5. What the function of L-Edit software?


-To design our mask/layout according to user.
-Can detect a mistake if something does suit it.
-Can see every layout that we design as we done create it.
DISCUSSION

Drawing the layout whether it nMOS or pMOS. Before I starting to design it, I
determine the scale for my layout. After that, the layout been create by following
each step that been state. I evaluate the layout and see if there are be some
mistake to the layout. If there no mistake, the design can be use to create a
layout for the transistor.

CONCLUSION

In this experiment, I have learned how to design a layout for a transistor. As a


result, it was a success. I managed to create nMOS ad pMOS layout. By using
this software (L-EDIT), it makes an easy ways to create it and it also can detect
mistake when we design it. Every active contact, metal 1, active, poly and nMOS
or pMOS must be correct scale according to what we wanted it. For overall this
experiment, it was a successes job.

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