7-1. Control Memory 1 / 14 7-1.

Control Memory 3 / 14

l 4) Control Data Register (= Pipeline Register )

n 7-1 Control Memory
Hold the microinstruction read from control memory
u Control Unit Allows the execution of the microoperations specified by the control word
l Initiate sequences of microoperations simultaneously with the generation of the next microinstruction
Control signal (that specify microoperations) in a bus-organized system u RISC Architecture Concept
n groups of bits that select the paths in multiplexers, decoders, and arithmetic logic units
l RISC(Reduced Instruction Set Computer) system use hardwired control rather
l Two major types of Control Unit than microprogrammed control : Sec. 8-8
Hardwired Control : in Chap. 5
n The control logic is implemented with gates, F/Fs, decoders, and other digital circuits n 7-2 Address Sequencing
n + Fast operation, - Wiring change(if the design has to be modified) u Address Sequencing = Sequencer : Next Address Generator
Microprogrammed Control : in this Chapter
l Selection of address for control memory
n The control information is stored in a control memory, and the control memory is programmed
to initiate the required sequence of microoperations u Routine Subroutine : program used by other ROUTINES
+ Any required change can be done by updating the microprogram in control memory,
l Microinstruction are stored in control memory in groups
n
- Slow operation

u Control Word u Mapping

l The control variables at any given time can be represented by a string of 1s and l Instruction Code Address in control memory(where routine is located)
0s. u Address Sequencing Capabilities : control memory address
u Microprogrammed Control Unit l 1) Incrementing of the control address register

l A control unit whose binary control variables are stored in memory (control l 2) Unconditional branch or conditional branch, depending on status bit conditions
memory). l 3) Mapping process ( bits of the instruction address for control memory )
l 4) A facility for subroutine return
Computer System Architecture Chap. 7 Microprogrammed Control Computer System Architecture Chap. 7 Microprogrammed Control

7-1. Control Memory 2 / 14 7-2. Address Sequencing 4 / 14

u Microinstruction : Control Word in Control Memory u Selection of address for control memory : Fig. 7-2
l The microinstruction specifies one or more microoperations l Multiplexer
u Microprogram
CAR Increment Instruction code
l A sequence of microinstruction
Dynamic microprogramming : Control Memory = RAM JMP/CALL Mapping
logic
RAM can be used for writing (to change a writable control memory)
n
Mapping
n Microprogram is loaded initially from an auxiliary memory such as a magnetic disk
Static microprogramming : Control Memory = ROM Subroutine Return Status
bits
Branch
logic
MUX
select
Multiplexers
n Control words in ROM are made permanent during the hardware production.
l CAR : Control Address Register Subroutine

u Microprogrammed control Organization : Fig. 7-1 regiser

(SBR)
CAR receive the address from Control address register
l 1) Control Memory Clock
(CAR)
User Program 4 different paths
A memory is part of a control unit : Microprogram
1) Incrementer
Computer Memory (employs a microprogrammed control unit) Machine Instruction
Incrementer

n Main Memory : for storing user program (Machine instruction/data) 2) Branch address from
n Control Memory : for storing microprogram (Microinstruction) Microprogram control memory
l 2) Control Address Register 3) Mapping Logic Control memory
Microinstruction
Specify the address of the microinstruction 4) SBR : Subroutine Register
l 3) Sequencer (= Next Address Generator) Microoperation l SBR : Subroutine Register Select a status Microoperations
bit
Determine the address sequence that is read from control memory Return Address can not be stored Branch address
Next address of the next microinstruction can be specified several way depending on in ROM
the sequencer input : p. 217, [1, 2, 3, and 4]
Return Address for a subroutine is
stored in SBR

Computer System Architecture Chap. 7 Microprogrammed Control Computer System Architecture Chap. 7 Microprogrammed Control
 7-2. Address Sequencing 5 / 14 7-3. Microprogram Example 7 / 14

u Conditional Branching u Instruction Format

l Status Bits
l Instruction Format : Fig. 7-5(a)
Control the conditional branch decisions generated in the Branch Logic
I : 1 bit for indirect addressing
l Branch Logic MUX
Opcode : 4 bit operation code
Test the specified condition and Branch to the indicated address if the condition is met ; 10 0
otherwise, the control address register is just incremented. Address : 11 bit address for system memory AR

l Status Bit Test Branch Logic : Fig. 7-8 l Computer Instruction : Fig. 7-5(b) Address Memory
204816

4 X 1 Mux Input Logic(Tab. 7-4) 16 4 10 0

PC

u Mapping of Instruction : Fig. 7-3 Opcode u Microinstruction Format : Fig. 7-6

l Computer Instruction 1 0 1 1 Address l 3 bit Microoperation Fields : F1, F2, F3 MUX

21 Microoperation : Tab. 7-1 6 0 6 0

Mapping bits 0 x x x x 0 0 3 microoperation SBR CAR
15 0
DR

n 3 , 000(no operation)
Microinstruction Address 0 1 0 1 1 0 0 two or more conflicting microoperations can
not be specified simultaneously Control memory
Arithmetic

l 4 bit Opcode = specify up to 16 distinct instruction 12820

logic and
shift unit
n ) 010 001 000
l Mapping Process : Converts the 4-bit Opcode to a 7-bit control memory address Clear AC to 0 and subtract DR from AC at the Control unit

1) Place a 0 in the most significant bit of the address same time 15 0

AC
2) Transfer 4-bit Operation code bits Symbol DRTAC(F1 = 100)
3) Clear the two least significant bits of the CAR (, 4 Microinstruction ) n stand for a transfer from DR to AC (T = to)
l Mapping Function : Implemented by Mapping ROM or PLD
l Control Memory Size : 128 words (= 27)

Computer System Architecture Chap. 7 Microprogrammed Control Computer System Architecture Chap. 7 Microprogrammed Control

7-2. Address Sequencing 6 / 14 7-3. Microprogram Example 8 / 14

u Subroutine l 2 bit Condition Fields : CD

l Subroutines are programs that are used by other routines 00 : Unconditional branch, U = 1
Subroutine can be called from any point within the main body of the microprogram 01 : Indirect address bit, I = DR(15)
10 : Sign bit of AC, S = AC(15)
l Microinstructions can be saved by subroutines that use common section of
microcode 11 : Zero value in AC, Z = AC = 0
) Memory Reference Operand Effective Address Subroutine l 2 bit Branch Fields : BR
n p. 228, Tab. 7-2 INDRCT ( FETCH INDRCT Subroutine) 00 : JMP
n Subroutine ORG 64, 1000000 - 1111111 (Routine 0000000 - 0111111) n Condition = 0 : 1 CAR CAR + 1
l Subroutine must have a provision for n Condition = 1 : 2 CAR AD
01 : CALL Save Return Address
storing the return address during a subroutine call CAR CAR + 1
n Condition = 0 : 1
restoring the address during a subroutine return CAR AD, SBR CAR + 1
n Condition = 1 : 2
n Last-In First Out(LIFO) Register Stack : Sec. 8-7 Restore Return Address
10 : RET 3 CAR SBR
n 7-3 Microprogram Example 11 : MAP 4 CAR (2 5) DR (11 14), CAR (0, 1, 6) 0
u Computer Configuration : Fig. 7-4 l 7 bit Address Fields : AD
l 2 Memory : Main memory(instruction/data), Control memory(microprogram) 128 word : 128 X 20 bit
Data written to memory come from DR, and Data read from memory can go only to DR u Symbolic Microinstruction
l 4 CPU Register and ALU : DR, AR, PC, AC, ALU Label Field : Terminated with a colon ( : )
DR can receive information from AC, PC, or Memory (selected by MUX)
Microoperation Field : one, two, or three
AR can receive information from PC or DR (selected by MUX) Label Microoperat CD BR AD
PC can receive information only from AR symbols, separated by commas ORG 64
FETCH: PCTAR U JMP NEXT
ALU performs microoperation with data from AC and DR ( AC ) CD Field : U, I, S, or Z READ, INCPC U JMP NEXT
l 2 Control Unit Register : SBR, CAR BR Field : JMP, CALL, RET, or MAP DRTAR U MAP 0

Computer System Architecture Chap. 7 Microprogrammed Control Computer System Architecture Chap. 7 Microprogrammed Control
 7-3. Microprogram Example 9 / 14 7-3. Microprogram Example 11 / 14

AD Field BRANCH instruction

n 1) BRANCH Address 4 CD Bit Sign(S) = 1 Address 6
a. Symbolic Address : Label ( = Address )
Indirect ARTPC Address Branch , FETCH PC
b. Symbol NEXT : next address .
c. Symbol RET or MAP : AD field = 0000000 n 2) BRANCH Address 4 Sign = 0 Branch FETCH PC
.
l ORG : Pseudoinstruction(define the origin, or first address of routine)
STORE instruction
u Fetch (Sub)Routine EXCHANGE instruction
l Memory Map(128 words) : Tab. 7-2, Tab. 7-3
u Binary Microprogram : Tab. 7-3
Address 0 to 63 : Routines for the 16 instruction( 4 instruction)
Address 64 to 127 : Any other purpose( Subroutines : FETCH, INDRCT) l Symbolic microprogram(Tab. 7-2) must be translated to binary either by means

l Microinstruction for FETCH Subroutine of an assembler program or by the user

AR PC Opcode Fetch l Control Memory
DR M [ AR], PC PC + 1 Most microprogrammed systems use a ROM for the control memory
AR DR(0 10), CAR(2 5) DR(11 14), CAR(0, 1, 6) 0 Opcode Decode n Cheaper and faster than a RAM
n Prevent the occasional user from changing the architecture of the system
Instruction Format
Operand Address Mapping n 7-4 Design of Control Unit
15 14 11 10 . 0

l Fetch Subroutine : address 64 I Opcode Address u Decoding of Microinstruction Fields : Fig. 7-7
Label Microoperat CD BR AD n l F1, F2, and F3 of Microinstruction are decodedo with a 3 x 8 decoder
ORG 64 l Output of decoder must be connected to the proper circuit to initiate the
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
corresponding microoperation (as specified in Tab. 7-1)
DRTAR U MAP 0

Computer System Architecture Chap. 7 Microprogrammed Control Computer System Architecture Chap. 7 Microprogrammed Control

7-3. Microprogram Example 10 / 14 7-3. Microprogram Example 12 / 14

u Symbolic Microprogram : Tab. 7-2

F1 F2 F3
l The execution of MAP microinstruction in FETCH subroutine
Branch to address 0xxxx00 (xxxx = 4 bit Opcode) ) F1 = 101 (5) : DRTAR
n ADD : 0 0000 00 = 0 F1 = 110 (6) : PCTAR 38 decoder 38 decoder 38 decoder
n BRANCH : 0 0001 00 = 4 n Output 5 and 6 of decoder F1 are 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
n STORE : 0 0010 00 = 8 connected to the load input of AR
n EXCHANGE : 0 0011 00 = 12, ( 16, 20, , 60 ) (two input of OR gate)
From DR
Multiplexer select the data from
l Indirect Address : I = 1 n
DR when output 5 is active
AND
ADD
Indirect Addressing : AR M [ AR ] n Multiplexer select the data from Arithmetic
DRTAC
n AR DR , AR AC when output 5 is inactive logic shift
INDRCT subroutine unit

Label Microoperat CD BR AD n PCTAR DRTAR o

l Arithmetic Logic Shift Unit
INDRCT: READ U JMP NEXT DR M [ AR ]
DRTAR U RET 0 Control signal of ALU in hardwired
AR DR From From Load
control : p. 164, Fig. 5-19, 20 PC DR(0-10) AC
l Execution of Instruction Control signal will be now come
ADD instruction from the output of the decoders 0 1
1) ADD FETCH subroutine Opcode fetch , MAP MAP Select
n associated with the AND, ADD, Multiplexers
Process CAR = 0 0000 00 branch ( Opcode = 0000, Fig. 7-5(b) ) and DRTAC.
n 2) ADD Address 0 CD Indirect = 1 INDRCT subroutine
Effective Address AR Return .
n 3) ADD Address 1 AR Memory DR .
Load
n 4) ADD Address 2 AC + DR AC , FETCH subroutine Clock
AR
Branch 1) PC Fetch MAP
Routine Address Branch .

Computer System Architecture Chap. 7 Microprogrammed Control Computer System Architecture Chap. 7 Microprogrammed Control
 7-3. Microprogram Example 13 / 14

u Microprogram Sequencer : Fig. 7-8

l Microprogram Sequencer select the next
External
address for control memory (MAP)

l MUX 1
L 3 2 1 0
Io
Select an address source and route to CAR Input Load
I1 S1 MUX 1 SBR
logic
CAR + 1 T S0

JMP/CALL
Mapping
Subroutine Return 1 Incrementer
I Test
MUX 2
JMP CALL S
Z Select
n JMP : AD MUX 1 2 CAR
Clock CAR
n CALL : AD MUX 1 2 CAR
, CAR + 1(Return Address)
LOAD SBR .
l MUX 2
Test a status bit and the result of the test is Control memory
applied to an input logic circuit Microops CD BR AD
One of 4 Status bit is selected by Condition bit (CD)
l Design of Input Logic Circuit
Select one of the source address(S0, S1) for
CAR
Enable the load input(L) in SBR

Computer System Architecture Chap. 7 Microprogrammed Control

7-3. Microprogram Example 14 / 14

l Input Logic Truth Table : Tab. 7-4

Input :
n I0, I1 from Branch bit (BR)
BR Field Input MUX 1 Load SBR
n T from MUX 2 (T)
I1 I0 T S1 S0 L
Output : 0 0 0 0 0 0 0 0 CAR + 1
n MUX 1 Select signal (S0, S1) 0 0 0 0 1 0 1 0 JMP
S1 = I1I0+ I1I0 = I1(I0+ I0) = I1 0 1 0 1 0 0 0 0 CAR + 1
S0 = I1I0T + I1I0T + I1I0 0 1 0 1 1 0 1 1 CALL
= I1T(I0+ I0) + I1I0
1 0 1 0 x 1 0 0 MAP
1 1 1 1 x 1 1 0 RET
= I1T + I1I0
n SBR Load signal (L)
L = I1I0T
CALL

Computer System Architecture Chap. 7 Microprogrammed Control